Skip to content

Commit cebd80e

Browse files
committed
Update formatting
1 parent 98ecfaa commit cebd80e

File tree

1 file changed

+3
-3
lines changed
  • ports/espressif/boards/lilygo_twatch_s3

1 file changed

+3
-3
lines changed

ports/espressif/boards/lilygo_twatch_s3/board.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
#define DELAY 0x80
1818

19-
// display init sequence according to LilyGO example app
19+
// Display init sequence according to LILYGO factory firmware
2020
uint8_t display_init_sequence[] = {
2121
// sw reset
2222
0x01, 0 | DELAY, 150,
@@ -58,8 +58,8 @@ void board_init(void) {
5858
bus,
5959
spi,
6060
&pin_GPIO38, // DC
61-
&pin_GPIO12, // CS
62-
NULL, // RST
61+
&pin_GPIO12, // CS
62+
NULL, // RST
6363
40000000, // baudrate
6464
0, // polarity
6565
0 // phase

0 commit comments

Comments
 (0)