Skip to content

Commit cf116f1

Browse files
StellasFunStellasFun
committed
create m5stack_stamps3 board
1 parent 27beb0e commit cf116f1

File tree

5 files changed

+300
-0
lines changed

5 files changed

+300
-0
lines changed

‎ports/espressif/boards/m5stack_stamp_s3/board.c‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
1+
// This file is part of the CircuitPython project: https://circuitpython.org
2+
//
3+
// SPDX-FileCopyrightText: Copyright (c) 2020 Scott Shawcroft for Adafruit Industries
4+
//
5+
// SPDX-License-Identifier: MIT
6+
7+
#include "mpconfigboard.h"
8+
#include "supervisor/board.h"
9+
#include "supervisor/shared/serial.h"
10+
#include "shared-bindings/busio/SPI.h"
11+
#include "shared-bindings/fourwire/FourWire.h"
12+
#include "shared-bindings/microcontroller/Pin.h"
13+
#include "shared-module/displayio/__init__.h"
14+
#include "shared-module/displayio/mipi_constants.h"
15+
#include "shared-bindings/board/__init__.h"
16+
#include "py/runtime.h"
17+
#include "py/ringbuf.h"
18+
#include "shared/runtime/interrupt_char.h"
19+
20+
21+
#define DELAY 0x80
22+
23+
uint8_t display_init_sequence[] = {
24+
// SWRESET and Delay 140ms
25+
0x01, 0 | DELAY, 140,
26+
// SLPOUT and Delay 10ms
27+
0x11, 0 | DELAY, 10,
28+
// COLMOD 65k colors and 16 bit 5-6-5
29+
0x3A, 1, 0x55,
30+
// INVON Iiversion on
31+
0x21, 0,
32+
// NORON normal operation (full update)
33+
0x13, 0,
34+
// MADCTL columns RTL, page/column reverse order
35+
0x36, 1, 0x60,
36+
// RAMCTRL color word little endian
37+
0xB0, 2, 0x00, 0xF8,
38+
// DIPON display on
39+
0x29, 0,
40+
};
41+
42+
43+
// Overrides the weakly linked function from supervisor/shared/board.c
44+
void board_init(void) {
45+
busio_spi_obj_t *spi = common_hal_board_create_spi(0);
46+
fourwire_fourwire_obj_t *bus = &allocate_display_bus()->fourwire_bus;
47+
bus->base.type = &fourwire_fourwire_type;
48+
49+
// see here for inspiration: https://github.com/m5stack/M5GFX/blob/33d7d3135e816a86a008fae8ab3757938cee95d2/src/M5GFX.cpp#L1350
50+
common_hal_fourwire_fourwire_construct(
51+
bus,
52+
spi,
53+
&pin_GPIO34, // DC
54+
&pin_GPIO37, // CS
55+
&pin_GPIO33, // RST
56+
40000000, // baudrate
57+
0, // polarity
58+
0 // phase
59+
);
60+
busdisplay_busdisplay_obj_t *display = &allocate_display()->display;
61+
display->base.type = &busdisplay_busdisplay_type;
62+
63+
common_hal_busdisplay_busdisplay_construct(
64+
display,
65+
bus,
66+
240, // width (after rotation)
67+
135, // height (after rotation)
68+
40, // column start
69+
53, // row start
70+
0, // rotation
71+
16, // color depth
72+
false, // grayscale
73+
false, // pixels in a byte share a row. Only valid for depths < 8
74+
1, // bytes per cell. Only valid for depths < 8
75+
false, // reverse_pixels_in_byte. Only valid for depths < 8
76+
false, // reverse_pixels_in_word
77+
MIPI_COMMAND_SET_COLUMN_ADDRESS, // set column command
78+
MIPI_COMMAND_SET_PAGE_ADDRESS, // set row command
79+
MIPI_COMMAND_WRITE_MEMORY_START, // write memory command
80+
display_init_sequence,
81+
sizeof(display_init_sequence),
82+
&pin_GPIO38, // backlight pin
83+
NO_BRIGHTNESS_COMMAND,
84+
1.0f, // brightness
85+
false, // single_byte_bounds
86+
false, // data_as_commands
87+
true, // auto_refresh
88+
60, // native_frames_per_second
89+
true, // backlight_on_high
90+
false, // SH1107_addressing
91+
350 // backlight pwm frequency
92+
);
93+
}
94+
95+
// TODO: Should we turn off the display when asleep, in board_deinit() ?

‎ports/espressif/boards/m5stack_stamp_s3/mpconfigboard.h‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
// This file is part of the CircuitPython project: https://circuitpython.org
2+
//
3+
// SPDX-FileCopyrightText: Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
4+
//
5+
// SPDX-License-Identifier: MIT
6+
7+
#pragma once
8+
9+
// Micropython setup
10+
11+
#define MICROPY_HW_BOARD_NAME "M5Stack Stamp-S3"
12+
#define MICROPY_HW_MCU_NAME "ESP32S3"
13+
14+
#define MICROPY_HW_NEOPIXEL (&pin_GPIO21)
15+
16+
#define DEFAULT_I2C_BUS_SCL (&pin_GPIO15)
17+
#define DEFAULT_I2C_BUS_SDA (&pin_GPIO13)
18+
19+
#define DEFAULT_UART_BUS_RX (&pin_GPIO44)
20+
#define DEFAULT_UART_BUS_TX (&pin_GPIO43)
21+
22+
#define CIRCUITPY_BOARD_SPI (2)
23+
#define CIRCUITPY_BOARD_SPI_PIN {{.clock = &pin_GPIO36, .mosi = &pin_GPIO35}, \
24+
{.clock = &pin_GPIO40, .mosi = &pin_GPIO14, .miso = &pin_GPIO39}}

‎ports/espressif/boards/m5stack_stamp_s3/mpconfigboard.mk‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
USB_VID = 0x303A
2+
USB_PID = 0x816B
3+
USB_PRODUCT = "M5Stack StampS3 - CircuitPython"
4+
USB_MANUFACTURER = "M5STACK"
5+
6+
IDF_TARGET = esp32s3
7+
8+
CIRCUITPY_ESP_FLASH_MODE = qio
9+
CIRCUITPY_ESP_FLASH_FREQ = 80m
10+
CIRCUITPY_ESP_FLASH_SIZE = 8MB
11+
CIRCUITPY_ESPCAMERA = 0
12+
13+
CIRCUITPY_GIFIO = 1
14+
CIRCUITPY_MAX3421E = 0

‎ports/espressif/boards/m5stack_stamp_s3/pins.c‎

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,153 @@
1+
// This file is part of the CircuitPython project: https://circuitpython.org
2+
//
3+
// SPDX-FileCopyrightText: Copyright (c) 2020 Scott Shawcroft for Adafruit Industries
4+
//
5+
// SPDX-License-Identifier: MIT
6+
7+
#include "shared-bindings/board/__init__.h"
8+
9+
#include "shared-module/displayio/__init__.h"
10+
CIRCUITPY_BOARD_BUS_SINGLETON(sd_spi, spi, 1)
11+
static const mp_rom_map_elem_t board_module_globals_table[] = {
12+
CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
13+
14+
// Button
15+
{ MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_GPIO0) },
16+
{ MP_ROM_QSTR(MP_QSTR_BOOT0), MP_ROM_PTR(&pin_GPIO0) },
17+
{ MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_GPIO0) },
18+
{ MP_ROM_QSTR(MP_QSTR_G0), MP_ROM_PTR(&pin_GPIO0) },
19+
20+
// GPIO
21+
{ MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_GPIO1) },
22+
{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO1) },
23+
{ MP_ROM_QSTR(MP_QSTR_G1), MP_ROM_PTR(&pin_GPIO1) },
24+
{ MP_ROM_QSTR(MP_QSTR_TCH1), MP_ROM_PTR(&pin_GPIO1) },
25+
26+
{ MP_ROM_QSTR(MP_QSTR_IO2), MP_ROM_PTR(&pin_GPIO2) },
27+
{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO2) },
28+
{ MP_ROM_QSTR(MP_QSTR_G2), MP_ROM_PTR(&pin_GPIO2) },
29+
{ MP_ROM_QSTR(MP_QSTR_TCH2), MP_ROM_PTR(&pin_GPIO2) },
30+
31+
{ MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_GPIO3) },
32+
{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO3) },
33+
{ MP_ROM_QSTR(MP_QSTR_G3), MP_ROM_PTR(&pin_GPIO3) },
34+
{ MP_ROM_QSTR(MP_QSTR_TCH3), MP_ROM_PTR(&pin_GPIO3) },
35+
36+
{ MP_ROM_QSTR(MP_QSTR_IO4), MP_ROM_PTR(&pin_GPIO4) },
37+
{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO4) },
38+
{ MP_ROM_QSTR(MP_QSTR_G4), MP_ROM_PTR(&pin_GPIO4) },
39+
{ MP_ROM_QSTR(MP_QSTR_TCH4), MP_ROM_PTR(&pin_GPIO4) },
40+
41+
{ MP_ROM_QSTR(MP_QSTR_IO5), MP_ROM_PTR(&pin_GPIO5) },
42+
{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO5) },
43+
{ MP_ROM_QSTR(MP_QSTR_G5), MP_ROM_PTR(&pin_GPIO5) },
44+
{ MP_ROM_QSTR(MP_QSTR_TCH5), MP_ROM_PTR(&pin_GPIO5) },
45+
46+
{ MP_ROM_QSTR(MP_QSTR_IO6), MP_ROM_PTR(&pin_GPIO6) },
47+
{ MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_GPIO6) },
48+
{ MP_ROM_QSTR(MP_QSTR_G6), MP_ROM_PTR(&pin_GPIO6) },
49+
{ MP_ROM_QSTR(MP_QSTR_TCH6), MP_ROM_PTR(&pin_GPIO6) },
50+
51+
{ MP_ROM_QSTR(MP_QSTR_IO7), MP_ROM_PTR(&pin_GPIO7) },
52+
{ MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_GPIO7) },
53+
{ MP_ROM_QSTR(MP_QSTR_G7), MP_ROM_PTR(&pin_GPIO7) },
54+
{ MP_ROM_QSTR(MP_QSTR_TCH7), MP_ROM_PTR(&pin_GPIO7) },
55+
56+
{ MP_ROM_QSTR(MP_QSTR_IO8), MP_ROM_PTR(&pin_GPIO8) },
57+
{ MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_GPIO8) },
58+
{ MP_ROM_QSTR(MP_QSTR_G8), MP_ROM_PTR(&pin_GPIO8) },
59+
{ MP_ROM_QSTR(MP_QSTR_TCH8), MP_ROM_PTR(&pin_GPIO8) },
60+
61+
{ MP_ROM_QSTR(MP_QSTR_IO9), MP_ROM_PTR(&pin_GPIO9) },
62+
{ MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_GPIO9) },
63+
{ MP_ROM_QSTR(MP_QSTR_G9), MP_ROM_PTR(&pin_GPIO9) },
64+
{ MP_ROM_QSTR(MP_QSTR_TCH9), MP_ROM_PTR(&pin_GPIO9) },
65+
66+
{ MP_ROM_QSTR(MP_QSTR_IO10), MP_ROM_PTR(&pin_GPIO10) },
67+
{ MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_GPIO10) },
68+
{ MP_ROM_QSTR(MP_QSTR_G10), MP_ROM_PTR(&pin_GPIO10) },
69+
{ MP_ROM_QSTR(MP_QSTR_TCH10), MP_ROM_PTR(&pin_GPIO10) },
70+
71+
{ MP_ROM_QSTR(MP_QSTR_IO11), MP_ROM_PTR(&pin_GPIO11) },
72+
{ MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_GPIO11) },
73+
{ MP_ROM_QSTR(MP_QSTR_G11), MP_ROM_PTR(&pin_GPIO11) },
74+
{ MP_ROM_QSTR(MP_QSTR_TCH11), MP_ROM_PTR(&pin_GPIO11) },
75+
76+
{ MP_ROM_QSTR(MP_QSTR_IO12), MP_ROM_PTR(&pin_GPIO12) },
77+
{ MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_GPIO12) },
78+
{ MP_ROM_QSTR(MP_QSTR_G12), MP_ROM_PTR(&pin_GPIO12) },
79+
{ MP_ROM_QSTR(MP_QSTR_TCH12), MP_ROM_PTR(&pin_GPIO12) },
80+
81+
{ MP_ROM_QSTR(MP_QSTR_IO13), MP_ROM_PTR(&pin_GPIO13) },
82+
{ MP_ROM_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_GPIO13) },
83+
{ MP_ROM_QSTR(MP_QSTR_G13), MP_ROM_PTR(&pin_GPIO13) },
84+
{ MP_ROM_QSTR(MP_QSTR_TCH13), MP_ROM_PTR(&pin_GPIO13) },
85+
86+
{ MP_ROM_QSTR(MP_QSTR_IO14), MP_ROM_PTR(&pin_GPIO14) },
87+
{ MP_ROM_QSTR(MP_QSTR_A14), MP_ROM_PTR(&pin_GPIO14) },
88+
{ MP_ROM_QSTR(MP_QSTR_G14), MP_ROM_PTR(&pin_GPIO14) },
89+
{ MP_ROM_QSTR(MP_QSTR_TCH14), MP_ROM_PTR(&pin_GPIO14) },
90+
91+
{ MP_ROM_QSTR(MP_QSTR_IO15), MP_ROM_PTR(&pin_GPIO15) },
92+
{ MP_ROM_QSTR(MP_QSTR_A15), MP_ROM_PTR(&pin_GPIO15) },
93+
{ MP_ROM_QSTR(MP_QSTR_G15), MP_ROM_PTR(&pin_GPIO15) },
94+
95+
{ MP_ROM_QSTR(MP_QSTR_IO39), MP_ROM_PTR(&pin_GPIO39) },
96+
{ MP_ROM_QSTR(MP_QSTR_G39), MP_ROM_PTR(&pin_GPIO39) },
97+
98+
{ MP_ROM_QSTR(MP_QSTR_IO40), MP_ROM_PTR(&pin_GPIO40) },
99+
{ MP_ROM_QSTR(MP_QSTR_G40), MP_ROM_PTR(&pin_GPIO40) },
100+
101+
{ MP_ROM_QSTR(MP_QSTR_IO41), MP_ROM_PTR(&pin_GPIO41) },
102+
{ MP_ROM_QSTR(MP_QSTR_G41), MP_ROM_PTR(&pin_GPIO41) },
103+
104+
{ MP_ROM_QSTR(MP_QSTR_IO42), MP_ROM_PTR(&pin_GPIO42) },
105+
{ MP_ROM_QSTR(MP_QSTR_G42), MP_ROM_PTR(&pin_GPIO42) },
106+
107+
{ MP_ROM_QSTR(MP_QSTR_IO43), MP_ROM_PTR(&pin_GPIO43) },
108+
{ MP_ROM_QSTR(MP_QSTR_G43), MP_ROM_PTR(&pin_GPIO43) },
109+
110+
{ MP_ROM_QSTR(MP_QSTR_IO44), MP_ROM_PTR(&pin_GPIO44) },
111+
{ MP_ROM_QSTR(MP_QSTR_G44), MP_ROM_PTR(&pin_GPIO44) },
112+
113+
{ MP_ROM_QSTR(MP_QSTR_IO46), MP_ROM_PTR(&pin_GPIO46) },
114+
{ MP_ROM_QSTR(MP_QSTR_G46), MP_ROM_PTR(&pin_GPIO46) },
115+
116+
// I2C
117+
{ MP_ROM_QSTR(MP_QSTR_I2C_SCL), MP_ROM_PTR(&pin_GPIO15) },
118+
{ MP_ROM_QSTR(MP_QSTR_I2C_SDA), MP_ROM_PTR(&pin_GPIO13) },
119+
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
120+
121+
// UART
122+
{ MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO43) },
123+
{ MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO44) },
124+
{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
125+
126+
// Neopixel
127+
{ MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO21) },
128+
129+
// Display
130+
{ MP_ROM_QSTR(MP_QSTR_TFT_RST), MP_ROM_PTR(&pin_GPIO33) },
131+
{ MP_ROM_QSTR(MP_QSTR_TFT_RESET), MP_ROM_PTR(&pin_GPIO33) },
132+
{ MP_ROM_QSTR(MP_QSTR_TFT_DC), MP_ROM_PTR(&pin_GPIO34) },
133+
{ MP_ROM_QSTR(MP_QSTR_TFT_RS), MP_ROM_PTR(&pin_GPIO34) },
134+
{ MP_ROM_QSTR(MP_QSTR_TFT_MOSI), MP_ROM_PTR(&pin_GPIO35) },
135+
{ MP_ROM_QSTR(MP_QSTR_TFT_DATA), MP_ROM_PTR(&pin_GPIO35) },
136+
{ MP_ROM_QSTR(MP_QSTR_TFT_SCK), MP_ROM_PTR(&pin_GPIO36) },
137+
{ MP_ROM_QSTR(MP_QSTR_TFT_CS), MP_ROM_PTR(&pin_GPIO37) },
138+
{ MP_ROM_QSTR(MP_QSTR_TFT_BACKLIGHT), MP_ROM_PTR(&pin_GPIO38) },
139+
{ MP_ROM_QSTR(MP_QSTR_TFT_BL), MP_ROM_PTR(&pin_GPIO38) },
140+
{ MP_ROM_QSTR(MP_QSTR_TFT_SPI), MP_ROM_PTR(&board_spi_obj) },
141+
142+
// Extended Port Pins
143+
{ MP_ROM_QSTR(MP_QSTR_IO16), MP_ROM_PTR(&pin_GPIO16) },
144+
{ MP_ROM_QSTR(MP_QSTR_G16), MP_ROM_PTR(&pin_GPIO16) },
145+
{ MP_ROM_QSTR(MP_QSTR_IO17), MP_ROM_PTR(&pin_GPIO17) },
146+
{ MP_ROM_QSTR(MP_QSTR_G17), MP_ROM_PTR(&pin_GPIO17) },
147+
{ MP_ROM_QSTR(MP_QSTR_IO18), MP_ROM_PTR(&pin_GPIO18) },
148+
{ MP_ROM_QSTR(MP_QSTR_G18), MP_ROM_PTR(&pin_GPIO18) },
149+
150+
// Display object
151+
{ MP_ROM_QSTR(MP_QSTR_DISPLAY), MP_ROM_PTR(&displays[0].display)},
152+
};
153+
MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);

‎ports/espressif/boards/m5stack_stamp_s3/sdkconfig‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
#
2+
# Espressif IoT Development Framework Configuration
3+
#
4+
#
5+
# Component config
6+
#
7+
#
8+
# LWIP
9+
#
10+
# end of LWIP
11+
12+
# end of Component config
13+
14+
# end of Espressif IoT Development Framework Configuration

0 commit comments

Comments
 (0)