@@ -348,6 +348,37 @@ audio_dma_result audio_dma_setup(
348348 }
349349 }
350350
351+ // Start input before output to allow the first two blocks to load.
352+ if (input_register_address ) {
353+ // We keep the audio_dma_t for internal use and the sample as a root pointer because it
354+ // contains the audiodma structure.
355+ MP_STATE_PORT (recording_audio )[dma -> input_channel [0 ]] = dma ;
356+ MP_STATE_PORT (recording_audio )[dma -> input_channel [1 ]] = dma ;
357+
358+ // Special case the DMA for a single buffer.
359+ if (single_buffer ) {
360+ dma_channel_config c = dma_channel_get_default_config (dma -> input_channel [1 ]);
361+ channel_config_set_transfer_data_size (& c , DMA_SIZE_32 );
362+ channel_config_set_dreq (& c , 0x3f ); // dma as fast as possible
363+ channel_config_set_read_increment (& c , false);
364+ channel_config_set_write_increment (& c , false);
365+ channel_config_set_chain_to (& c , dma -> input_channel [1 ]); // Chain to ourselves so we stop.
366+ dma_channel_configure (dma -> input_channel [1 ], & c ,
367+ & dma -> input_buffer [0 ], // write address
368+ & dma_hw -> ch [dma -> input_channel [0 ]].al2_write_addr_trig , // read address
369+ 1 , // transaction count
370+ false); // trigger
371+ } else {
372+ // Enable our DMA channels on DMA_IRQ_1 to the CPU.
373+ dma_hw -> inte1 |= (1 << dma -> input_channel [0 ]) | (1 << dma -> input_channel [1 ]);
374+ irq_set_mask_enabled (1 << DMA_IRQ_1 , true);
375+ }
376+
377+ dma -> input_index = -1 ;
378+ dma -> recording_in_progress = true;
379+ dma_channel_start (dma -> input_channel [0 ]);
380+ }
381+
351382 if (output_register_address ) {
352383 // We keep the audio_dma_t for internal use and the sample as a root pointer because it
353384 // contains the audiodma structure.
@@ -388,36 +419,6 @@ audio_dma_result audio_dma_setup(
388419 dma_channel_start (dma -> output_channel [0 ]);
389420 }
390421
391- if (input_register_address ) {
392- // We keep the audio_dma_t for internal use and the sample as a root pointer because it
393- // contains the audiodma structure.
394- MP_STATE_PORT (recording_audio )[dma -> input_channel [0 ]] = dma ;
395- MP_STATE_PORT (recording_audio )[dma -> input_channel [1 ]] = dma ;
396-
397- // Special case the DMA for a single buffer.
398- if (single_buffer ) {
399- dma_channel_config c = dma_channel_get_default_config (dma -> input_channel [1 ]);
400- channel_config_set_transfer_data_size (& c , DMA_SIZE_32 );
401- channel_config_set_dreq (& c , 0x3f ); // dma as fast as possible
402- channel_config_set_read_increment (& c , false);
403- channel_config_set_write_increment (& c , false);
404- channel_config_set_chain_to (& c , dma -> input_channel [1 ]); // Chain to ourselves so we stop.
405- dma_channel_configure (dma -> input_channel [1 ], & c ,
406- & dma -> input_buffer [0 ], // write address
407- & dma_hw -> ch [dma -> input_channel [0 ]].al2_write_addr_trig , // read address
408- 1 , // transaction count
409- false); // trigger
410- } else {
411- // Enable our DMA channels on DMA_IRQ_1 to the CPU.
412- dma_hw -> inte1 |= (1 << dma -> input_channel [0 ]) | (1 << dma -> input_channel [1 ]);
413- irq_set_mask_enabled (1 << DMA_IRQ_1 , true);
414- }
415-
416- dma -> input_index = -1 ;
417- dma -> recording_in_progress = true;
418- dma_channel_start (dma -> input_channel [0 ]);
419- }
420-
421422 return AUDIO_DMA_OK ;
422423}
423424
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