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spresense: empty rx uart fifo after initialization
1 parent 22ed0ab commit ed3f636

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  • ports/cxd56/common-hal/busio

1 file changed

+11
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ports/cxd56/common-hal/busio/UART.c

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,9 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
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uint32_t baudrate, uint8_t bits, busio_uart_parity_t parity, uint8_t stop,
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mp_float_t timeout, uint16_t receiver_buffer_size, byte* receiver_buffer,
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bool sigint_enabled) {
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int i;
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int count;
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char tmp;
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struct termios tio;
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if ((rts != NULL) || (cts != NULL) || (rs485_dir != NULL) || (rs485_invert)) {
@@ -96,6 +99,14 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self,
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if (busio_uart_dev[self->number].fd < 0) {
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mp_raise_ValueError(translate("Could not initialize UART"));
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}
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// Wait to make sure the UART is ready
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usleep(1000);
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// Clear RX FIFO
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ioctl(busio_uart_dev[self->number].fd, FIONREAD, (long unsigned int)&count);
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for (i = 0; i < count; i++) {
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read(busio_uart_dev[self->number].fd, &tmp, 1);
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}
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}
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ioctl(busio_uart_dev[self->number].fd, TCGETS, (long unsigned int)&tio);

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