From 5123f3d5f0f11c7e94c7a89e3acfe9c1511bfc00 Mon Sep 17 00:00:00 2001 From: Alex Bucknall Date: Wed, 5 Mar 2025 13:55:13 +0000 Subject: [PATCH] feat: add cygnet to ports/stm --- ports/stm/Makefile | 11 +- ports/stm/boards/STM32L433_boot.ld | 27 +++++ ports/stm/boards/STM32L433_default.ld | 29 +++++ ports/stm/boards/blues_cygnet/board.c | 79 +++++++++++++ ports/stm/boards/blues_cygnet/board.h | 12 ++ ports/stm/boards/blues_cygnet/mpconfigboard.h | 47 ++++++++ .../stm/boards/blues_cygnet/mpconfigboard.mk | 105 ++++++++++++++++++ ports/stm/boards/blues_cygnet/pins.c | 52 +++++++++ ports/stm/common-hal/microcontroller/Pin.c | 2 + .../stm/common-hal/microcontroller/__init__.c | 18 +-- ports/stm/mpconfigport.mk | 9 +- ports/stm/packages/LQFP48.c | 63 +++++++++++ ports/stm/peripherals/periph.h | 11 ++ ports/stm/peripherals/pins.h | 3 + ports/stm/peripherals/stm32l4/clocks.c | 49 +++++++- .../peripherals/stm32l4/stm32l433xx/clocks.h | 49 ++++++++ .../peripherals/stm32l4/stm32l433xx/gpio.c | 26 +++++ .../peripherals/stm32l4/stm32l433xx/periph.c | 91 +++++++++++++++ .../peripherals/stm32l4/stm32l433xx/periph.h | 46 ++++++++ .../peripherals/stm32l4/stm32l433xx/pins.c | 50 +++++++++ .../peripherals/stm32l4/stm32l433xx/pins.h | 46 ++++++++ ports/stm/supervisor/internal_flash.c | 15 ++- ports/stm/supervisor/internal_flash.h | 6 + ports/stm/supervisor/usb.c | 23 +++- 24 files changed, 842 insertions(+), 27 deletions(-) create mode 100644 ports/stm/boards/STM32L433_boot.ld create mode 100644 ports/stm/boards/STM32L433_default.ld create mode 100644 ports/stm/boards/blues_cygnet/board.c create mode 100644 ports/stm/boards/blues_cygnet/board.h create mode 100644 ports/stm/boards/blues_cygnet/mpconfigboard.h create mode 100644 ports/stm/boards/blues_cygnet/mpconfigboard.mk create mode 100644 ports/stm/boards/blues_cygnet/pins.c create mode 100644 ports/stm/packages/LQFP48.c create mode 100644 ports/stm/peripherals/stm32l4/stm32l433xx/clocks.h create mode 100644 ports/stm/peripherals/stm32l4/stm32l433xx/gpio.c create mode 100644 ports/stm/peripherals/stm32l4/stm32l433xx/periph.c create mode 100644 ports/stm/peripherals/stm32l4/stm32l433xx/periph.h create mode 100644 ports/stm/peripherals/stm32l4/stm32l433xx/pins.c create mode 100644 ports/stm/peripherals/stm32l4/stm32l433xx/pins.h diff --git a/ports/stm/Makefile b/ports/stm/Makefile index ec5ba752d4143..3611254574033 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -165,7 +165,7 @@ endif # Need this to avoid UART linker problems. TODO: rewrite to use registered callbacks. # Does not exist for F4 and lower -ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx STM32H750xx STM32L4R5xx)) +ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx STM32H750xx STM32L4R5xx STM32L433xx)) SRC_STM32 += $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_hal_uart_ex.c endif @@ -197,9 +197,12 @@ ifneq ($(CIRCUITPY_AUDIOBUSIO_PDMIN),0) endif ifneq ($(CIRCUITPY_USB),0) -SRC_C += \ - lib/tinyusb/src/portable/synopsys/dwc2/dcd_dwc2.c \ - lib/tinyusb/src/portable/synopsys/dwc2/dwc2_common.c + ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32L433xx)) + SRC_C += lib/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + else + SRC_C += lib/tinyusb/src/portable/synopsys/dwc2/dcd_dwc2.c + SRC_C += lib/tinyusb/src/portable/synopsys/dwc2/dwc2_common.c + endif endif SRC_S = \ diff --git a/ports/stm/boards/STM32L433_boot.ld b/ports/stm/boards/STM32L433_boot.ld new file mode 100644 index 0000000000000..686547a8ce6e7 --- /dev/null +++ b/ports/stm/boards/STM32L433_boot.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for STM32L433 with bootloader +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08010000, LENGTH = 4K /* ISR vector. Kind of wasteful. */ + FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 192K-64K-4K + FLASH_FS (rw) : ORIGIN = 0x08030000, LENGTH = 60K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K +} + + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 24K; +_minimum_heap_size = 16K; + +/* Define the top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); diff --git a/ports/stm/boards/STM32L433_default.ld b/ports/stm/boards/STM32L433_default.ld new file mode 100644 index 0000000000000..886a1b8827a20 --- /dev/null +++ b/ports/stm/boards/STM32L433_default.ld @@ -0,0 +1,29 @@ +/* + GNU linker script for STM32L433 with filesystem +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* ISR vector. */ + FLASH_FS (rw) : ORIGIN = 0x08004000, LENGTH = 48K + FLASH_FIRMWARE (rx) : ORIGIN = 0x08010000, LENGTH = 256K - 48K - 16K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 24K; +_minimum_heap_size = 16K; + +/* Define the top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); + +/* ensure the firmware is within bounds */ +ASSERT ( (ORIGIN(FLASH_FIRMWARE) + LENGTH(FLASH_FIRMWARE)) <= (ORIGIN(FLASH)+LENGTH(FLASH)), "FLASH_FIRMWARE out of bounds" ); diff --git a/ports/stm/boards/blues_cygnet/board.c b/ports/stm/boards/blues_cygnet/board.c new file mode 100644 index 0000000000000..f6650fb8f9c33 --- /dev/null +++ b/ports/stm/boards/blues_cygnet/board.c @@ -0,0 +1,79 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries +// +// SPDX-License-Identifier: MIT + +#include "supervisor/board.h" +#include "mpconfigboard.h" + +#include "stm32l4xx.h" +#include "stm32l433xx.h" + +#include "shared-bindings/microcontroller/Pin.h" +#include "shared-bindings/digitalio/DigitalInOut.h" +#include "shared-bindings/digitalio/Direction.h" +#include "shared-bindings/digitalio/DriveMode.h" +#include "board.h" + +digitalio_digitalinout_obj_t power_pin = { .base.type = &digitalio_digitalinout_type }; +digitalio_digitalinout_obj_t discharge_pin = { .base.type = &digitalio_digitalinout_type }; + +void initialize_discharge_pin(void) { + /* Initialize the 3V3 discharge to be OFF and the output power to be ON */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + common_hal_digitalio_digitalinout_construct(&power_pin, &pin_PH00); + common_hal_digitalio_digitalinout_construct(&discharge_pin, &pin_PH01); + common_hal_digitalio_digitalinout_never_reset(&power_pin); + common_hal_digitalio_digitalinout_never_reset(&discharge_pin); + + GPIO_InitTypeDef GPIO_InitStruct; + + /* Set DISCHARGE_3V3 as well as the pins we're not initially using to FLOAT */ + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pin = GPIO_PIN_1; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); /* PH1 DISCHARGE_3V3 */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* PB3 is USB_DETECT */ + GPIO_InitStruct.Pin = GPIO_PIN_15; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* PA15 is CHARGE_DETECT */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* PA4 is BAT_VOLTAGE */ + + /* Turn on the 3V3 regulator */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_LOW; + GPIO_InitStruct.Pin = GPIO_PIN_0; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + HAL_GPIO_WritePin(GPIOH, GPIO_InitStruct.Pin, GPIO_PIN_SET); +} + +void board_init(void) { + // enable the debugger while sleeping. Todo move somewhere more central (kind of generally useful in a debug build) + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + + // Set tick interrupt priority, default HAL value is intentionally invalid + // Without this, USB does not function. + HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_LOW; + GPIO_InitStruct.Pin = GPIO_PIN_8; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET); + HAL_Delay(50); + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); +} + +void reset_board(void) { + initialize_discharge_pin(); +} + +// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here. diff --git a/ports/stm/boards/blues_cygnet/board.h b/ports/stm/boards/blues_cygnet/board.h new file mode 100644 index 0000000000000..ce199359ba496 --- /dev/null +++ b/ports/stm/boards/blues_cygnet/board.h @@ -0,0 +1,12 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries +// +// SPDX-License-Identifier: MIT + +#pragma once + +#include "common-hal/digitalio/DigitalInOut.h" + +extern digitalio_digitalinout_obj_t power_pin; +extern digitalio_digitalinout_obj_t discharge_pin; diff --git a/ports/stm/boards/blues_cygnet/mpconfigboard.h b/ports/stm/boards/blues_cygnet/mpconfigboard.h new file mode 100644 index 0000000000000..f3b1fcc2eb72c --- /dev/null +++ b/ports/stm/boards/blues_cygnet/mpconfigboard.h @@ -0,0 +1,47 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2024 Blues Wireless Contributors. +// +// SPDX-License-Identifier: MIT + +#pragma once + +// Micropython setup + +#define MICROPY_HW_BOARD_NAME "Cygnet" +#define MICROPY_HW_MCU_NAME "STM32L433CCT6" + +#define MICROPY_PY_SYS_PLATFORM MICROPY_HW_BOARD_NAME + +#define STM32L433XX +#define BOARD_CYGNET + +#define LSE_VALUE ((uint32_t)32768) +#define BOARD_HAS_LOW_SPEED_CRYSTAL (1) +#define BOARD_HAS_HIGH_SPEED_CRYSTAL (0) + +// Increase drive strength of 32kHz external crystal, in line with calculations specified in ST AN2867 sections 3.3, 3.4, and STM32L4 datasheet DS12023 Table 58. LSE oscillator characteristics. +// The drive strength RCC_LSEDRIVE_LOW is marginal for the 32kHz crystal oscillator stability, and RCC_LSEDRIVE_MEDIUMLOW meets the calculated drive strength with a small margin for parasitic capacitance. +#define BOARD_LSE_DRIVE_LEVEL RCC_LSEDRIVE_MEDIUMLOW + +// Bootloader only +#ifdef UF2_BOOTLOADER_ENABLED + #define BOARD_VTOR_DEFER (1) // Leave VTOR relocation to bootloader +#endif + +#define BOARD_NO_VBUS_SENSE (1) +#define BOARD_NO_USB_OTG_ID_SENSE (1) + +#define DEFAULT_I2C_BUS_SCL (&pin_PB06) +#define DEFAULT_I2C_BUS_SDA (&pin_PB07) + +#define DEFAULT_SPI_BUS_SS (&pin_PB08) +#define DEFAULT_SPI_BUS_SCK (&pin_PA05) +#define DEFAULT_SPI_BUS_MOSI (&pin_PB05) +#define DEFAULT_SPI_BUS_MISO (&pin_PB06) + +#define DEFAULT_UART_BUS_RX (&pin_PA10) +#define DEFAULT_UART_BUS_TX (&pin_PA09) + +#define CYGNET_DISCHARGE_3V3 (&pin_PH01) +#define CYGNET_ENABLE_3V3 (&pin_PH00) diff --git a/ports/stm/boards/blues_cygnet/mpconfigboard.mk b/ports/stm/boards/blues_cygnet/mpconfigboard.mk new file mode 100644 index 0000000000000..48e8241c7a6b8 --- /dev/null +++ b/ports/stm/boards/blues_cygnet/mpconfigboard.mk @@ -0,0 +1,105 @@ +USB_VID = 0x30A4 +USB_PID = 0x03 +USB_PRODUCT = "Cygnet" +USB_MANUFACTURER = "Blues Inc." + +MCU_SERIES = L4 +MCU_VARIANT = STM32L433xx +MCU_PACKAGE = LQFP48 + +LD_COMMON = boards/common_default.ld +LD_DEFAULT = boards/STM32L433_default.ld +UF2_OFFSET = 0x8000000 +UF2_BOOTLOADER ?= 0 +CIRCUITPY_BUILD_EXTENSIONS = bin + +INTERNAL_FLASH_FILESYSTEM = 1 +LONGINT_IMPL = NONE +CIRCUITPY_FULL_BUILD = 0 + +CIRCUITPY_AESIO = 0 +CIRCUITPY_ALARM = 0 +CIRCUITPY_ANALOGIO = 1 +CIRCUITPY_ATEXIT = 0 +CIRCUITPY_AUDIOBUSIO = 0 +CIRCUITPY_AUDIOBUSIO_I2SOUT = 0 +CIRCUITPY_AUDIOBUSIO_PDMIN = 0 +CIRCUITPY_AUDIOMIXER = 0 +CIRCUITPY_AUDIOMP3 = 0 +CIRCUITPY_AUDIOPWMIO = 0 +CIRCUITPY_BITBANGIO = 1 +CIRCUITPY_BLEIO = 0 +CIRCUITPY_BLEIO_HCI = 0 +CIRCUITPY_BINASCII = 0 +CIRCUITPY_BITMAPFILTER = 0 +CIRCUITPY_BITMAPTOOLS = 0 +CIRCUITPY_BUILTINS_POW3 = 0 +CIRCUITPY_BUSDEVICE = 0 +CIRCUITPY_BUSIO = 1 +CIRCUITPY_CANIO = 0 +CIRCUITPY_COMPUTED_GOTO_SAVE_SPACE = 1 +CIRCUITPY_COUNTIO = 0 +CIRCUITPY_DIGITALIO = 1 +CIRCUITPY_DISPLAYIO = 0 +CIRCUITPY_ENABLE_MPY_NATIVE = 0 +CIRCUITPY_FRAMEBUFFERIO = 0 +CIRCUITPY_FREQUENCYIO = 0 +CIRCUITPY_FUTURE= 0 +CIRCUITPY_GETPASS = 0 +CIRCUITPY_GIFIO = 0 +CIRCUITPY_I2CTARGET = 0 +CIRCUITPY_JSON = 0 +CIRCUITPY_KEYPAD = 0 +CIRCUITPY_KEYPAD_DEMUX = 0 +CIRCUITPY_LTO = 1 +CIRCUITPY_MICROCONTROLLER = 1 +CIRCUITPY_MSGPACK = 0 +CIRCUITPY_NEOPIXEL_WRITE = 0 +CIRCUITPY_NVM = 0 +CIRCUITPY_ONEWIREIO = 0 +CIRCUITPY_OS = 1 +CIRCUITPY_PIXELBUF = 0 +CIRCUITPY_PIXELMAP = 0 +CIRCUITPY_PULSEIO = 1 +CIRCUITPY_PWMIO = 1 +CIRCUITPY_RANDOM = 0 +CIRCUITPY_RAINBOWIO = 0 +CIRCUITPY_RE = 0 +CIRCUITPY_REQUIRE_I2C_PULLUPS = 0 +CIRCUITPY_ROTARYIO_SOFTENCODER = 1 +CIRCUITPY_RGBMATRIX = 0 +CIRCUITPY_RTC = 0 +CIRCUITPY_SAFEMODE_PY = 0 +CIRCUITPY_SDCARDIO = 0 +CIRCUITPY_STATUS_BAR= 0 +CIRCUITPY_STORAGE = 1 +CIRCUITPY_SUPERVISOR = 1 +CIRCUITPY_SYNTHIO = 0 +CIRCUITPY_TERMINALIO = 0 +CIRCUITPY_TOUCHIO = 0 +CIRCUITPY_TOUCHIO_USE_NATIVE = 1 +CIRCUITPY_TRACEBACK = 0 +CIRCUITPY_ULAB = 0 +CIRCUITPY_USB_CDC = 1 +CIRCUITPY_USB_HID = 0 +CIRCUITPY_USB_IDENTIFICATION = 1 +CIRCUITPY_USB_MIDI = 0 +CIRCUITPY_USB_MIDI_ENABLED_DEFAULT= 0 +CIRCUITPY_USB_MSC = 1 +CIRCUITPY_USB_VENDOR = 0 +CIRCUITPY_WIFI_RADIO_SETTABLE_MAC_ADDRESS= 0 +CIRCUITPY_VECTORIO = 0 +CIRCUITPY_ZLIB = 0 + +MICROPY_PY_ASYNC_AWAIT = 0 + +RELEASE_NEEDS_CLEAN_BUILD = 0 + +SUPEROPT_GC = 0 +SUPEROPT_VM = 0 + +CIRCUITPY_LTO_PARTITION = one + +OPTIMIZATION_FLAGS = -Os + +CFLAGS_BOARD = -fweb -frename-registers diff --git a/ports/stm/boards/blues_cygnet/pins.c b/ports/stm/boards/blues_cygnet/pins.c new file mode 100644 index 0000000000000..f644160e4fd2a --- /dev/null +++ b/ports/stm/boards/blues_cygnet/pins.c @@ -0,0 +1,52 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2017 Scott Shawcroft for Adafruit Industries +// +// SPDX-License-Identifier: MIT + +// #include "py/objtuple.h" +#include "shared-bindings/board/__init__.h" +#include "board.h" + +// Core Feather Pins +static const mp_rom_map_elem_t board_module_globals_table[] = { + CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS + + { MP_ROM_QSTR(MP_QSTR_ENABLE_3V3), &power_pin }, + { MP_ROM_QSTR(MP_QSTR_DISCHARGE_3V3), &discharge_pin }, + + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PA07) }, + + { MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_PC13) }, + + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PB15) }, + + { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PB04) }, // ADC, PWM, DAC2 output also + + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) }, // PWM + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) }, // PWM + + { MP_ROM_QSTR(MP_QSTR_SS), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB05) }, + + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) }, // ADC, PWM + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) }, // PWM + + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; + +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/common-hal/microcontroller/Pin.c b/ports/stm/common-hal/microcontroller/Pin.c index 21c77736d6b8d..bdf5e5fb16cd6 100644 --- a/ports/stm/common-hal/microcontroller/Pin.c +++ b/ports/stm/common-hal/microcontroller/Pin.c @@ -21,6 +21,8 @@ GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE}; GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD}; #elif defined(UFQFPN48) GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC}; +#elif defined(LQFP48) +GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC}; #else #error Unknown package type #endif diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c index 5a0f0ed929451..a9c9b76849de3 100644 --- a/ports/stm/common-hal/microcontroller/__init__.c +++ b/ports/stm/common-hal/microcontroller/__init__.c @@ -31,12 +31,14 @@ void common_hal_mcu_delay_us(uint32_t delay) { SysTick->CTRL = 0UL; } -volatile uint32_t nesting_count = 0; +static volatile uint32_t nesting_count = 0; +// 32-bit increments void common_hal_mcu_disable_interrupts(void) { - __disable_irq(); - __DMB(); - nesting_count++; + if (++nesting_count == 1) { + __disable_irq(); + __DMB(); + } } void common_hal_mcu_enable_interrupts(void) { @@ -44,12 +46,10 @@ void common_hal_mcu_enable_interrupts(void) { // This is very very bad because it means there was mismatched disable/enables. reset_into_safe_mode(SAFE_MODE_INTERRUPT_ERROR); } - nesting_count--; - if (nesting_count > 0) { - return; + if (--nesting_count == 0) { + __DMB(); + __enable_irq(); } - __DMB(); - __enable_irq(); } static bool next_reset_to_bootloader = false; diff --git a/ports/stm/mpconfigport.mk b/ports/stm/mpconfigport.mk index 3874870a6da76..83759fc5d2405 100644 --- a/ports/stm/mpconfigport.mk +++ b/ports/stm/mpconfigport.mk @@ -81,11 +81,18 @@ ifeq ($(MCU_SERIES),L4) CIRCUITPY_NVM ?= 0 CIRCUITPY_ROTARYIO ?= 0 CIRCUITPY_RTC ?= 1 + UF2_FAMILY_ID ?= 0x00ff6919 +endif + +ifeq ($(MCU_VARIANT),STM32L4R5xx) # todo - this varies between devices in the series # This slide deck https://www.st.com/content/ccc/resource/training/technical/product_training/98/89/c8/6c/3e/e9/49/79/STM32L4_Peripheral_USB.pdf/files/STM32L4_Peripheral_USB.pdf/jcr:content/translations/en.STM32L4_Peripheral_USB.pdf # cites 16 endpoints, 8 endpoint pairs, while section 3.39 of the L4R5 datasheet states 6 endpoint pairs. USB_NUM_ENDPOINT_PAIRS = 6 - UF2_FAMILY_ID ?= 0x00ff6919 +endif + +ifeq ($(MCU_VARIANT),STM32L433xx) + USB_NUM_ENDPOINT_PAIRS = 4 endif CIRCUITPY_PARALLELDISPLAYBUS := 0 diff --git a/ports/stm/packages/LQFP48.c b/ports/stm/packages/LQFP48.c new file mode 100644 index 0000000000000..46b737adeb8e3 --- /dev/null +++ b/ports/stm/packages/LQFP48.c @@ -0,0 +1,63 @@ +#include "shared-bindings/microcontroller/__init__.h" +#include "common-hal/microcontroller/Pin.h" +#include "py/obj.h" + +static const mp_rom_map_elem_t mcu_pin_globals_table[] = { +// Pins 1-12 + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // { MP_ROM_QSTR(MP_QSTR_PH00), MP_ROM_PTR(&pin_PH00) }, PH00 OSC_IN + // { MP_ROM_QSTR(MP_QSTR_PH01), MP_ROM_PTR(&pin_PH01) }, PH01 OSC_OUT + // NRST -------------------------------------------*/ + // VSSA -------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + +// Pins 13-24 + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 25-36 + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 37-48 + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +}; +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h index e1a922cebc9d7..33b0f5e9edeb9 100644 --- a/ports/stm/peripherals/periph.h +++ b/ports/stm/peripherals/periph.h @@ -84,6 +84,13 @@ typedef struct { #include "stm32l4/stm32l4r5xx/periph.h" #endif +#ifdef STM32L433xx +#define HAS_DAC 1 +#define HAS_TRNG 1 +#define HAS_BASIC_TIM 1 +#include "stm32l4/stm32l433xx/periph.h" +#endif + #ifdef STM32F405xx #define HAS_DAC 1 #define HAS_TRNG 1 @@ -137,3 +144,7 @@ typedef struct { #define HAS_BASIC_TIM 1 #include "stm32h7/stm32h750xx/periph.h" #endif + +#if !defined(HAS_DAC) +#error Unknown MCU +#endif diff --git a/ports/stm/peripherals/pins.h b/ports/stm/peripherals/pins.h index 7720ce0a1e0ef..42ddefdc40624 100644 --- a/ports/stm/peripherals/pins.h +++ b/ports/stm/peripherals/pins.h @@ -70,6 +70,9 @@ extern const mp_obj_type_t mcu_pin_type; #ifdef STM32L4R5xx #include "stm32l4/stm32l4r5xx/pins.h" #endif +#ifdef STM32L433xx +#include "stm32l4/stm32l433xx/pins.h" +#endif #ifdef STM32F405xx #include "stm32f4/stm32f405xx/pins.h" #endif diff --git a/ports/stm/peripherals/stm32l4/clocks.c b/ports/stm/peripherals/stm32l4/clocks.c index a005c2bf7908f..4a7adc62de746 100644 --- a/ports/stm/peripherals/stm32l4/clocks.c +++ b/ports/stm/peripherals/stm32l4/clocks.c @@ -9,8 +9,10 @@ #include // L4 Series -#ifdef STM32L4R5xx +#if defined(STM32L4R5xx) #include "stm32l4/stm32l4r5xx/clocks.h" +#elif defined(STM32L433xx) +#include "stm32l4/stm32l433xx/clocks.h" #else #error Please add other MCUs here so that they are not silently ignored due to #define typos #endif @@ -44,49 +46,86 @@ void stm32_peripherals_clocks_init(void) { /** Configure the main internal regulator output voltage */ + #if defined(STM32L4R5xx) if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) { Error_Handler(); } - + #elif defined(STM32L433xx) + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { + Error_Handler(); + } + #endif /* Activate PLL with MSI , stabilizied via PLL by LSE */ + #if defined(STM32L4R5xx) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; RCC_OscInitStruct.PLL.PLLM = 6; RCC_OscInitStruct.PLL.PLLN = 30; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV5; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + #elif defined(STM32L433xx) + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSICalibrationValue = 0; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 40; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + #else + #error Unknown MCU + #endif + HAL_CHECK(HAL_RCC_OscConfig(&RCC_OscInitStruct)); + #ifdef STM32L4R5xx /* Enable MSI Auto-calibration through LSE */ HAL_RCCEx_EnableMSIPLLMode(); + #endif /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - // Avoid overshoot and start with HCLK 60 MHz RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + #if defined(STM32L4R5xx) HAL_CHECK(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3)); + #elif defined(STM32L433xx) + HAL_CHECK(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4)); + #else + #error Please expand the conditional compilation to set the default flash latency + #endif /* AHB prescaler divider at 1 as second step */ + #ifdef STM32L4R5xx RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; HAL_CHECK(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5)); + #endif /* Select MSI output as USB clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ADC; + #if defined(STM32L4R5xx) PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; + #elif defined(STM32L433xx) + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + #endif PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK; - HAL_CHECK(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct)); + HAL_CHECK(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct)); } diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/clocks.h b/ports/stm/peripherals/stm32l4/stm32l433xx/clocks.h new file mode 100644 index 0000000000000..a01cae704d6b6 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/clocks.h @@ -0,0 +1,49 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#pragma once + +#include "stm32l4xx_hal.h" + +// Chip: STM32L433 +// Line Type: Foundation Line +// Speed: 80MHz (MAX) + +// Defaults: +#ifndef CPY_CLK_VSCALE +#define CPY_CLK_VSCALE (PWR_REGULATOR_VOLTAGE_SCALE1) // up to 80MHz +#endif +#ifndef CPY_CLK_PLLM +#define CPY_CLK_PLLM (1) +#endif +#ifndef CPY_CLK_PLLN +#define CPY_CLK_PLLN (40) +#endif +#ifndef CPY_CLK_PLLP +#define CPY_CLK_PLLP (RCC_PLLP_DIV7) +#endif +#ifndef CPY_CLK_PLLQ +#define CPY_CLK_PLLQ (2) +#endif +#ifndef CPY_CLK_AHBDIV +#define CPY_CLK_AHBDIV (RCC_SYSCLK_DIV1) +#endif +#ifndef CPY_CLK_APB1DIV +#define CPY_CLK_APB1DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_APB2DIV +#define CPY_CLK_APB2DIV (RCC_HCLK_DIV1) +#endif +#ifndef CPY_CLK_FLASH_LATENCY +#define CPY_CLK_FLASH_LATENCY (FLASH_LATENCY_4) +#endif +#ifndef CPY_CLK_USB_USES_AUDIOPLL +#define CPY_CLK_USB_USES_AUDIOPLL (0) +#endif + +#ifndef BOARD_HAS_HIGH_SPEED_CRYSTAL +#define BOARD_HAS_HIGH_SPEED_CRYSTAL (1) +#endif diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/gpio.c b/ports/stm/peripherals/stm32l4/stm32l433xx/gpio.c new file mode 100644 index 0000000000000..eb8914b5585c1 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/gpio.c @@ -0,0 +1,26 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#include "peripherals/gpio.h" +#include "common-hal/microcontroller/Pin.h" + +void stm32_peripherals_gpio_init(void) { + // Enable all GPIO for now + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + + // Never reset pins + never_reset_pin_number(2, 14); // PC14 OSC32_IN + never_reset_pin_number(2, 15); // PC15 OSC32_OUT + never_reset_pin_number(0, 13); // PA13 SWDIO + never_reset_pin_number(0, 14); // PA14 SWCLK +} + +void stm32l4_peripherals_status_led(uint8_t led, uint8_t state) { + +} diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/periph.c b/ports/stm/peripherals/stm32l4/stm32l433xx/periph.c new file mode 100644 index 0000000000000..e98c192c68517 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/periph.c @@ -0,0 +1,91 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" + +I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN] = {I2C1, I2C2}; + +const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN] = { + PERIPH(1, 4, &pin_PA10), + PERIPH(2, 4, &pin_PB14), +}; + +const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN] = { + PERIPH(1, 4, &pin_PA09), + PERIPH(2, 4, &pin_PB13), +}; + +SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN] = {SPI1}; + +const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN] = { + PERIPH(1, 5, &pin_PB03), +}; +const mcu_periph_obj_t mcu_spi_mosi_list[SPI_MOSI_ARRAY_LEN] = { + PERIPH(1, 5, &pin_PA12), +}; +const mcu_periph_obj_t mcu_spi_miso_list[SPI_MISO_ARRAY_LEN] = { + PERIPH(1, 5, &pin_PA11), +}; +const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN] = { + PERIPH(1, 5, &pin_PA15), +}; + +USART_TypeDef *mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3}; +bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false}; + +const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN] = { + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(1, 7, &pin_PB06), + PERIPH(3, 7, &pin_PB10), +}; +const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN] = { + PERIPH(2, 7, &pin_PA03), + PERIPH(1, 7, &pin_PA10), + PERIPH(2, 7, &pin_PA15), + PERIPH(1, 7, &pin_PB07), + PERIPH(3, 7, &pin_PB11), +}; + +// Timers +TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN] = {TIM1, TIM2, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, TIM15, TIM16, NULL}; + +const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN] = { + TIM(2, 1, 1, &pin_PA00), + TIM(2, 1, 2, &pin_PA01), + TIM(2, 1, 3, &pin_PA02), + TIM(15, 15, 1, &pin_PA02), + TIM(2, 1, 4, &pin_PA03), + TIM(15, 15, 2, &pin_PA03), + TIM(2, 1, 1, &pin_PA05), + TIM(16, 15, 1, &pin_PA06), + TIM(1, 1, 1, &pin_PA08), + TIM(1, 1, 2, &pin_PA09), + TIM(1, 1, 3, &pin_PA10), + TIM(1, 1, 4, &pin_PA11), + TIM(2, 1, 1, &pin_PA15), + TIM(2, 1, 2, &pin_PB03), + TIM(16, 15, 1, &pin_PB08), + TIM(2, 1, 3, &pin_PB10), + TIM(2, 1, 4, &pin_PB11), + TIM(15, 15, 1, &pin_PB14), + TIM(15, 15, 2, &pin_PB15), +}; + +// CAN +CAN_TypeDef *mcu_can_banks[] = {CAN1}; + +const mcu_periph_obj_t mcu_can_tx_list[2] = { + PERIPH(1, 10, &pin_PA12), + PERIPH(1, 10, &pin_PB09), +}; +const mcu_periph_obj_t mcu_can_rx_list[2] = { + PERIPH(1, 10, &pin_PA11), + PERIPH(1, 10, &pin_PB08), +}; diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/periph.h b/ports/stm/peripherals/stm32l4/stm32l433xx/periph.h new file mode 100644 index 0000000000000..6bf0add01fef4 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/periph.h @@ -0,0 +1,46 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#pragma once + +// I2C +#define I2C_BANK_ARRAY_LEN 2 +#define I2C_SDA_ARRAY_LEN 2 +#define I2C_SCL_ARRAY_LEN 2 +extern I2C_TypeDef *mcu_i2c_banks[I2C_BANK_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_i2c_sda_list[I2C_SDA_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_i2c_scl_list[I2C_SCL_ARRAY_LEN]; + +// SPI +#define SPI_BANK_ARRAY_LEN 1 +#define SPI_SCK_ARRAY_LEN 1 +#define SPI_MOSI_ARRAY_LEN 1 +#define SPI_MISO_ARRAY_LEN 1 +#define SPI_NSS_ARRAY_LEN 1 +extern SPI_TypeDef *mcu_spi_banks[SPI_BANK_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_spi_sck_list[SPI_SCK_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_spi_mosi_list[SPI_MOSI_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_spi_miso_list[SPI_MISO_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_spi_nss_list[SPI_NSS_ARRAY_LEN]; + +// UART +#define UART_TX_ARRAY_LEN 4 +#define UART_RX_ARRAY_LEN 5 +extern USART_TypeDef *mcu_uart_banks[MAX_UART]; +extern bool mcu_uart_has_usart[MAX_UART]; +extern const mcu_periph_obj_t mcu_uart_tx_list[UART_TX_ARRAY_LEN]; +extern const mcu_periph_obj_t mcu_uart_rx_list[UART_RX_ARRAY_LEN]; + +// Timers +#define TIM_BANK_ARRAY_LEN 17 +#define TIM_PIN_ARRAY_LEN 19 +extern TIM_TypeDef *mcu_tim_banks[TIM_BANK_ARRAY_LEN]; +extern const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; + +// CAN +extern CAN_TypeDef *mcu_can_banks[1]; +extern const mcu_periph_obj_t mcu_can_tx_list[2]; +extern const mcu_periph_obj_t mcu_can_rx_list[2]; diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/pins.c b/ports/stm/peripherals/stm32l4/stm32l433xx/pins.c new file mode 100644 index 0000000000000..060f53031bb44 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/pins.c @@ -0,0 +1,50 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" + +#include STM32_HAL_H + +const mcu_pin_obj_t pin_PA00 = PIN(0, 0, ADC_INPUT(ADC_1, 5)); +const mcu_pin_obj_t pin_PA01 = PIN(0, 1, ADC_INPUT(ADC_1, 6)); +const mcu_pin_obj_t pin_PA02 = PIN(0, 2, ADC_INPUT(ADC_1, 7)); +const mcu_pin_obj_t pin_PA03 = PIN(0, 3, ADC_INPUT(ADC_1, 8)); +const mcu_pin_obj_t pin_PA04 = PIN(0, 4, ADC_INPUT(ADC_1, 9)); +const mcu_pin_obj_t pin_PA05 = PIN(0, 5, ADC_INPUT(ADC_1, 10)); +const mcu_pin_obj_t pin_PA06 = PIN(0, 6, ADC_INPUT(ADC_1, 11)); +const mcu_pin_obj_t pin_PA07 = PIN(0, 7, ADC_INPUT(ADC_1, 12)); +const mcu_pin_obj_t pin_PA08 = PIN(0, 8, NO_ADC); +const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC); +const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC); +const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC); +const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC); +const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); +const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); +const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); +const mcu_pin_obj_t pin_PB00 = PIN(1, 0, ADC_INPUT(ADC_1, 15)); +const mcu_pin_obj_t pin_PB01 = PIN(1, 1, ADC_INPUT(ADC_1, 16)); +const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); +const mcu_pin_obj_t pin_PB03 = PIN(1, 3, NO_ADC); +const mcu_pin_obj_t pin_PB04 = PIN(1, 4, NO_ADC); +const mcu_pin_obj_t pin_PB05 = PIN(1, 5, NO_ADC); +const mcu_pin_obj_t pin_PB06 = PIN(1, 6, NO_ADC); +const mcu_pin_obj_t pin_PB07 = PIN(1, 7, NO_ADC); +const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC); +const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC); +const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC); +const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); +const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC); +const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC); +const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC); +const mcu_pin_obj_t pin_PB15 = PIN(1, 15, NO_ADC); +const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); +const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); +const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); +const mcu_pin_obj_t pin_PH00 = PIN(5, 0, NO_ADC); +const mcu_pin_obj_t pin_PH01 = PIN(5, 1, NO_ADC); +const mcu_pin_obj_t pin_PH03 = PIN(5, 3, NO_ADC); diff --git a/ports/stm/peripherals/stm32l4/stm32l433xx/pins.h b/ports/stm/peripherals/stm32l4/stm32l433xx/pins.h new file mode 100644 index 0000000000000..93a175ddbad81 --- /dev/null +++ b/ports/stm/peripherals/stm32l4/stm32l433xx/pins.h @@ -0,0 +1,46 @@ +// This file is part of the CircuitPython project: https://circuitpython.org +// +// SPDX-FileCopyrightText: Copyright (c) 2021 Blues Wireless Contributors +// +// SPDX-License-Identifier: MIT + +#pragma once + +extern const mcu_pin_obj_t pin_PA00; +extern const mcu_pin_obj_t pin_PA01; +extern const mcu_pin_obj_t pin_PA02; +extern const mcu_pin_obj_t pin_PA03; +extern const mcu_pin_obj_t pin_PA04; +extern const mcu_pin_obj_t pin_PA05; +extern const mcu_pin_obj_t pin_PA06; +extern const mcu_pin_obj_t pin_PA07; +extern const mcu_pin_obj_t pin_PA08; +extern const mcu_pin_obj_t pin_PA09; +extern const mcu_pin_obj_t pin_PA10; +extern const mcu_pin_obj_t pin_PA11; +extern const mcu_pin_obj_t pin_PA12; +extern const mcu_pin_obj_t pin_PA13; +extern const mcu_pin_obj_t pin_PA14; +extern const mcu_pin_obj_t pin_PA15; +extern const mcu_pin_obj_t pin_PB00; +extern const mcu_pin_obj_t pin_PB01; +extern const mcu_pin_obj_t pin_PB02; +extern const mcu_pin_obj_t pin_PB03; +extern const mcu_pin_obj_t pin_PB04; +extern const mcu_pin_obj_t pin_PB05; +extern const mcu_pin_obj_t pin_PB06; +extern const mcu_pin_obj_t pin_PB07; +extern const mcu_pin_obj_t pin_PB08; +extern const mcu_pin_obj_t pin_PB09; +extern const mcu_pin_obj_t pin_PB10; +extern const mcu_pin_obj_t pin_PB11; +extern const mcu_pin_obj_t pin_PB12; +extern const mcu_pin_obj_t pin_PB13; +extern const mcu_pin_obj_t pin_PB14; +extern const mcu_pin_obj_t pin_PB15; +extern const mcu_pin_obj_t pin_PC13; +extern const mcu_pin_obj_t pin_PC14; +extern const mcu_pin_obj_t pin_PC15; +extern const mcu_pin_obj_t pin_PH00; +extern const mcu_pin_obj_t pin_PH01; +extern const mcu_pin_obj_t pin_PH03; diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 11fdc0a198dac..240dbba996085 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -75,12 +75,18 @@ static const flash_layout_t flash_layout[] = { #endif static uint8_t _flash_cache[0x20000] __attribute__((aligned(4))); -#elif defined(STM32L4) +#elif defined(STM32L4R5xx) static const flash_layout_t flash_layout[] = { { 0x08100000, 0x1000, 256 }, }; static uint8_t _flash_cache[0x1000] __attribute__((aligned(4))); +#elif defined(STM32L433xx) +static const flash_layout_t flash_layout[] = { + { 0x08000000, 0x0800, 128 }, +}; +static uint8_t _flash_cache[0x0800] __attribute__((aligned(4))); + #else #error Unsupported processor #endif @@ -185,8 +191,13 @@ void port_internal_flash_flush(void) { // set up for erase FLASH_EraseInitTypeDef EraseInitStruct = {}; #if CPY_STM32L4 + #if defined(STM32L4R5xx) EraseInitStruct.TypeErase = TYPEERASE_PAGES; - EraseInitStruct.Banks = FLASH_BANK_2; // filesystem stored in upper 1MB of flash in dual bank mode + EraseInitStruct.Banks = FLASH_BANK_2; // filesystem stored in upper 1MB of flash in dual bank mode + #elif defined(STM32L433xx) + EraseInitStruct.TypeErase = TYPEERASE_PAGES; + EraseInitStruct.Banks = FLASH_BANK_1; + #endif #else EraseInitStruct.TypeErase = TYPEERASE_SECTORS; EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index e9979e6a01058..473a495cd7c6e 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -93,6 +93,12 @@ #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08100000 #endif +#ifdef STM32L433xx +#define STM32_FLASH_SIZE 0x40000 // 256KiB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 // 48KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 +#endif + #define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #define STM32_FLASH_OFFSET 0x8000000 // All STM32 chips map to this flash location diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 61a7d54f08b74..7c782f61d0d9b 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -29,7 +29,7 @@ static void init_usb_vbus_sense(void) { // B-peripheral session valid override enable USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; - #else + #elif !defined(STM32L433xx) && !defined(STM32L4R5xx) USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; @@ -56,7 +56,7 @@ void init_usb_hardware(void) { GPIO_InitTypeDef GPIO_InitStruct = {0}; /**USB_OTG_FS GPIO Configuration - PA10 ------> USB_OTG_FS_ID + PA10 ------> USB_OTG_FS_ID (not present on STM32L433) PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ @@ -69,10 +69,15 @@ void init_usb_hardware(void) { GPIO_InitStruct.Pull = GPIO_NOPULL; #if CPY_STM32H7 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #elif CPY_STM32F4 || CPY_STM32F7 || CPY_STM32L4 + #elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5xx) GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + #elif defined(STM32L433xx) + GPIO_InitStruct.Alternate = GPIO_AF10_USB_FS; + #else + #error Unknown MCU #endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + never_reset_pin_number(0, 11); never_reset_pin_number(0, 12); claim_pin(0, 11); @@ -117,15 +122,21 @@ void init_usb_hardware(void) { #if CPY_STM32H7 HAL_PWREx_EnableUSBVoltageDetector(); __HAL_RCC_USB2_OTG_FS_CLK_ENABLE(); - #else + #elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5xx) /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + #else + __HAL_RCC_USB_CLK_ENABLE(); #endif - init_usb_vbus_sense(); } -void OTG_FS_IRQHandler(void) { +#if defined(STM32L433xx) +void USB_IRQHandler(void) +#else +void OTG_FS_IRQHandler(void) +#endif +{ usb_irq_handler(0); }