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hathachhathach
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refactor pin_mux to use mcux pin config tool
1 parent a3feba4 commit 4263111

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16 files changed

+2365
-450
lines changed

16 files changed

+2365
-450
lines changed

‎ports/mimxrt10xx/boards/teensy40/board.cmake‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,7 @@ set(MCU_VARIANT MIMXRT1062)
33
set(PYOCD_TARGET mimxrt1060)
44

55
function(update_board TARGET)
6-
target_sources(${TARGET} PRIVATE
7-
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
8-
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash_config.c
9-
)
6+
107
target_compile_definitions(${TARGET} PUBLIC
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CPU_MIMXRT1062DVL6A
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)

‎ports/mimxrt10xx/boards/teensy40/board.h‎

Lines changed: 3 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -34,33 +34,18 @@
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//--------------------------------------------------------------------+
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// LED
3636
//--------------------------------------------------------------------+
37-
38-
#define LED_PINMUX IOMUXC_GPIO_B0_03_GPIO2_IO03
39-
#define LED_PORT GPIO2
40-
#define LED_PIN 3
37+
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
38+
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
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#define LED_STATE_ON 0
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4341
//--------------------------------------------------------------------+
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// Neopixel
4543
//--------------------------------------------------------------------+
46-
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// Number of neopixels
48-
#define NEOPIXEL_NUMBER 0
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//--------------------------------------------------------------------+
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// Button
52-
//--------------------------------------------------------------------+
53-
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// Teensy 4.1 pin 23.
55-
#define BUTTON_PINMUX IOMUXC_GPIO_AD_B1_09_GPIO1_IO25
56-
#define BUTTON_PORT GPIO1
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#define BUTTON_PIN 25
58-
#define BUTTON_STATE_ACTIVE 0
44+
#define NEOPIXEL_NUMBER 0 // Number of neopixels
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6046
//--------------------------------------------------------------------+
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// USB UF2
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//--------------------------------------------------------------------+
63-
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#define USB_VID 0x239A
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#define USB_PID 0x0085
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#define USB_MANUFACTURER "PJRC"
@@ -74,9 +59,6 @@
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//--------------------------------------------------------------------+
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// UART
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//--------------------------------------------------------------------+
77-
7862
#define UART_DEV LPUART1
79-
#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_13_LPUART1_RX
80-
#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_12_LPUART1_TX
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8264
#endif /* BOARD_H_ */

ports/mimxrt10xx/boards/teensy40/clock_config.c renamed to ports/mimxrt10xx/boards/teensy40/board/clock_config.c

Lines changed: 94 additions & 78 deletions
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‎ports/mimxrt10xx/boards/teensy40/board/clock_config.h‎

Lines changed: 123 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,123 @@
1+
#ifndef _CLOCK_CONFIG_H_
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#define _CLOCK_CONFIG_H_
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4+
#include "fsl_common.h"
5+
6+
/*******************************************************************************
7+
* Definitions
8+
******************************************************************************/
9+
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
10+
11+
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
12+
/*******************************************************************************
13+
************************ BOARD_InitBootClocks function ************************
14+
******************************************************************************/
15+
16+
#if defined(__cplusplus)
17+
extern "C" {
18+
#endif /* __cplusplus*/
19+
20+
/*!
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* @brief This function executes default configuration of clocks.
22+
*
23+
*/
24+
void BOARD_InitBootClocks(void);
25+
26+
#if defined(__cplusplus)
27+
}
28+
#endif /* __cplusplus*/
29+
30+
/*******************************************************************************
31+
********************** Configuration BOARD_BootClockRUN ***********************
32+
******************************************************************************/
33+
/*******************************************************************************
34+
* Definitions for BOARD_BootClockRUN configuration
35+
******************************************************************************/
36+
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
37+
38+
/* Clock outputs (values are in Hz): */
39+
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */
40+
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */
41+
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
42+
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
43+
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
44+
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
45+
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
46+
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
47+
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */
48+
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */
49+
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */
50+
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
51+
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */
52+
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
53+
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
54+
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
55+
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */
56+
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
57+
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
58+
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
59+
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
60+
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
61+
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
62+
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
63+
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
64+
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */
65+
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
66+
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
67+
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
68+
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
69+
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
70+
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
71+
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
72+
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
73+
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
74+
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
75+
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
76+
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
77+
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
78+
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
79+
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
80+
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
81+
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
82+
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
83+
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
84+
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
85+
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
86+
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */
87+
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
88+
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
89+
90+
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
91+
*/
92+
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
93+
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
94+
*/
95+
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
96+
/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
97+
*/
98+
extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
99+
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
100+
*/
101+
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
102+
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
103+
*/
104+
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
105+
106+
/*******************************************************************************
107+
* API for BOARD_BootClockRUN configuration
108+
******************************************************************************/
109+
#if defined(__cplusplus)
110+
extern "C" {
111+
#endif /* __cplusplus*/
112+
113+
/*!
114+
* @brief This function executes configuration of clocks.
115+
*
116+
*/
117+
void BOARD_BootClockRUN(void);
118+
119+
#if defined(__cplusplus)
120+
}
121+
#endif /* __cplusplus*/
122+
123+
#endif /* _CLOCK_CONFIG_H_ */

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