diff --git a/.clang-format b/.clang-format new file mode 100644 index 000000000..d3298befc --- /dev/null +++ b/.clang-format @@ -0,0 +1,100 @@ +--- +Language: Cpp +BasedOnStyle: LLVM +AlignAfterOpenBracket: Align +AlignConsecutiveAssignments: + Enabled: true + AcrossEmptyLines: false + AcrossComments: false +AlignConsecutiveBitFields: + Enabled: true + AcrossEmptyLines: false + AcrossComments: false +AlignConsecutiveDeclarations: + Enabled: true + AcrossEmptyLines: false + AcrossComments: false +AlignConsecutiveMacros: + Enabled: true + AcrossEmptyLines: true + AcrossComments: false +AlignConsecutiveShortCaseStatements: + Enabled: true + AcrossEmptyLines: true + AcrossComments: true + AlignCaseColons: false +AlignEscapedNewlines: LeftWithLastLine +AlignOperands: true +AlignTrailingComments: + Kind: Always + OverEmptyLines: 2 +AllowAllArgumentsOnNextLine: false +AllowAllConstructorInitializersOnNextLine: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: Empty +AllowShortCaseExpressionOnASingleLine: true +AllowShortCaseLabelsOnASingleLine: false +AllowShortEnumsOnASingleLine: false +AllowShortFunctionsOnASingleLine: None +AllowShortIfStatementsOnASingleLine: Never +AlwaysBreakTemplateDeclarations: Yes +BinPackArguments: true +BreakBeforeBraces: Custom +BraceWrapping: + AfterCaseLabel: false + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterStruct: false + AfterUnion: false + AfterExternBlock: false + BeforeCatch: true + BeforeElse: false + BeforeLambdaBody: false + BeforeWhile: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BracedInitializerIndentWidth: 2 +BreakBeforeBinaryOperators: None +BreakConstructorInitializers: AfterColon +BreakConstructorInitializersBeforeComma: false +ContinuationIndentWidth: 2 +ColumnLimit: 120 +ConstructorInitializerAllOnOneLineOrOnePerLine: false +Cpp11BracedListStyle: true +IncludeBlocks: Preserve +IncludeCategories: + - Regex: '^<.*' + Priority: 1 + - Regex: '^".*' + Priority: 2 + - Regex: '.*' + Priority: 3 +IncludeIsMainRegex: '([-_](test|unittest))?$' +IndentPPDirectives: BeforeHash +InsertBraces: true +IndentCaseLabels: true +InsertNewlineAtEOF: true +MacroBlockBegin: '' +MacroBlockEnd: '' +MaxEmptyLinesToKeep: 2 +NamespaceIndentation: All +PenaltyBreakBeforeFirstCallParameter: 1000000 +PenaltyBreakOpenParenthesis: 1000000 +PPIndentWidth: 2 +QualifierAlignment: Custom +QualifierOrder: ['static', 'const', 'volatile', 'restrict', 'type'] +SpaceAfterTemplateKeyword: false +SpaceBeforeRangeBasedForLoopColon: false +SpaceInEmptyParentheses: false +SpacesInAngles: false +SpacesInConditionalStatement: false +SpacesInCStyleCastParentheses: false +SpacesInParentheses: false +SortIncludes: false +TabWidth: 2 +UseTab: Never +... diff --git a/README.md b/README.md index 7eaed9d55..fc5079bb7 100644 --- a/README.md +++ b/README.md @@ -38,9 +38,14 @@ Not all features are implemented for all MCUs, following is supported MCUs and i | STM32F4 | ✔ | ✔ | ✔ | ✔ | ✔ | | | STM32H5 | ✔ | ✔ | ✔ | ✔ | | | +## Supported MCUs and Boards + +Please refer to [supported boards](./supported_boards.md) for the complete list of supported MCUs and boards. + ## Build and Flash -Following is generic compiling information. Each port may require extra set-up and slight different process e.g esp32s2 require setup IDF. +Following is generic compiling information. Each port may require extra set-up and slight different process e.g esp32s2 +require ESP-IDF. ### Clone diff --git a/apps/blinky/src/blinky.c b/apps/blinky/src/blinky.c index db279d738..7e412542e 100644 --- a/apps/blinky/src/blinky.c +++ b/apps/blinky/src/blinky.c @@ -41,18 +41,22 @@ int main(void) { board_timer_start(1); while (1) { - // nothing to do + if ((_timer_count & 0xfful) == 0) { + uint32_t count = _timer_count >> 8; + // Toggle 2 times then pause 1 + if (count & 0x1ul || count & 0x4ul) { + board_led_write(0x000); + board_rgb_write(RGB_OFF); + } else { + board_led_write(0xff); + board_rgb_write(RGB_WRITING); + } + } } } void board_timer_handler(void) { _timer_count++; - if ((_timer_count & 0xfful) == 0) { - const uint32_t is_on = (_timer_count >> 8) & 0x1u; - - board_led_write(is_on ? 0xff : 0x000); - board_rgb_write(is_on ? RGB_WRITING : RGB_OFF); - } } //--------------------------------------------------------------------+ diff --git a/cmake/toolchain/common.cmake b/cmake/toolchain/common.cmake index 688715914..9e15bec9e 100644 --- a/cmake/toolchain/common.cmake +++ b/cmake/toolchain/common.cmake @@ -25,6 +25,7 @@ if (TOOLCHAIN STREQUAL "gcc") -ffunction-sections -fsingle-precision-constant -fno-strict-aliasing + -g ) list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS -Wl,--print-memory-usage diff --git a/ports/espressif/README.md b/ports/espressif/README.md index a296ee88c..2b250b4e6 100644 --- a/ports/espressif/README.md +++ b/ports/espressif/README.md @@ -1,36 +1,12 @@ -# TinyUF2 "Bootloader Application" for ESP32-S2 and ESP32-S3 +# TinyUF2 "Bootloader Application" for Espressif (S2/S3/P4) The project is composed of customizing the 2nd stage bootloader from IDF and UF2 factory application as 3rd stage bootloader. **Note**: IDF is actively developed and change very often, TinyUF2 is developed and tested with IDF v5.3.2. Should you have a problem please try to change your IDF version. -Following boards are supported: - -- [Adafruit Magtag 2.9" E-Ink WiFi Display](https://www.adafruit.com/product/4800) -- [Adafruit Metro ESP32-S2](https://www.adafruit.com/product/4775) -- [Deneyap Kart 1A v2](https://magaza.deneyapkart.org/tr/product/detail/deneyap-kart-1a-v2-type-c) -- [Deneyap Mini](https://magaza.deneyapkart.org/tr/product/detail/deneyap-mini) -- [Deneyap Mini v2](https://magaza.deneyapkart.org/tr/product/detail/deneyap-mini-v2-type-c) -- [ES3ink](https://github.com/dronecz/es3ink) -- [Espressif Kaluga 1](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit.html) -- [Espressif HMI 1](https://github.com/espressif/esp-dev-kits/tree/master/esp32-s2-hmi-devkit-1) -- [Espressif Saola 1R (WROVER) and 1M (WROOM)](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html) -- [Gravitech Cucumber RIS ESP32-S2 w/Sensors ](https://www.gravitech.us/curisdebowis.html) -- [Heltec Wireless Tracker](https://heltec.org/project/wireless-tracker) -- [LILYGO® TTGO T8 ESP32-S2 V1.1](http://www.lilygo.cn/prod_view.aspx?TypeId=50063&Id=1300&FId=t3:50063:3) -- [LILYGO® TTGO T8 ESP32-S2 V1.1 ST7789 ](http://www.lilygo.cn/prod_view.aspx?TypeId=50033&Id=1321&FId=t3:50033:3) -- [LILYGO® TTGO T8 ESP32-S2-WROOM](http://www.lilygo.cn/prod_view.aspx?TypeId=50063&Id=1320&FId=t3:50063:3) -- [LILYGO® TTGO T-Beam Supreme](https://www.lilygo.cc/products/softrf-t-beamsupreme) -- [LILYGO® TTGO T-TWR Plus](https://www.lilygo.cc/products/t-twr-plus) -- [LILYGO® T-Dongle S3](https://www.lilygo.cc/products/t-dongle-s3) -- [LOLIN Wemos® S2 Pico](https://www.wemos.cc/en/latest/s2/s2_pico.html) -- [Maker badge](https://github.com/dronecz/maker_badge) -- [MicroDev microS2](https://github.com/microDev1/microS2/wiki) -- [Morpheans MorphESP-240](https://github.com/ccadic/ESP32-S2-DevBoardTFT) or [MorphESP CrowdSupply](https://www.crowdsupply.com/morpheans/morphesp-240) -- [Olimex ESP32S2 DevKit Lipo vB1 (WROVER and WROOM)](https://www.olimex.com/Products/IoT/ESP32-S2/ESP32-S2-DevKit-Lipo/open-source-hardware) -- [Seeed XIAO ESP32S3](https://www.seeedstudio.com/XIAO-ESP32S3-p-5627.html) -- [Unexpected Maker FeatherS2](https://feathers2.io) +## Supported Boards +See the board list for this family in [supported_boards.md](../../supported_boards.md#espressif). ## Build & Flash diff --git a/ports/family_support.cmake b/ports/family_support.cmake index fecb1807b..939879c07 100644 --- a/ports/family_support.cmake +++ b/ports/family_support.cmake @@ -37,6 +37,19 @@ if (NOT DEFINED CMAKE_BUILD_TYPE OR CMAKE_BUILD_TYPE STREQUAL "") set(CMAKE_BUILD_TYPE MinSizeRel CACHE STRING "Build type" FORCE) endif () + +if (NOT DEFINED JLINKEXE) + if (CMAKE_HOST_WIN32) + set(JLINKEXE JLink.exe) + else () + set(JLINKEXE JLinkExe) + endif () +endif () + +if (NOT DEFINED JLINK_IF) + set(JLINK_IF swd) +endif () + #------------------------------------------------------------- # FAMILY and BOARD #------------------------------------------------------------- @@ -150,7 +163,7 @@ function(family_configure_common TARGET) target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER}) # Add segger rtt to example - if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") + if (LOGGER STREQUAL "RTT") target_sources(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) target_include_directories(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) # target_compile_definitions(${TARGET} PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) @@ -231,18 +244,6 @@ endfunction() # Add flash jlink target, optional parameter is the extension of the binary file function(family_flash_jlink TARGET) - if (NOT DEFINED JLINKEXE) - if(CMAKE_HOST_WIN32) - set(JLINKEXE JLink.exe) - else() - set(JLINKEXE JLinkExe) - endif() - endif () - - if (NOT DEFINED JLINK_IF) - set(JLINK_IF swd) - endif () - if (NOT DEFINED JLINK_OPTION) set(JLINK_OPTION "") endif () @@ -281,6 +282,23 @@ exit ) endfunction() +function(family_jlink_erase_external TARGET START_ADDR END_ADDR) + file(GENERATE + OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}-erase64k.jlink + CONTENT "halt +exec EnableEraseAllFlashBanks +r +erase ${START_ADDR} ${END_ADDR} +r +exit +" + ) + + add_custom_target(${TARGET}-erase-external-jlink + COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}-erase64k.jlink + ) +endfunction() + # Add flash stlink target function(family_flash_stlink TARGET) diff --git a/ports/make.mk b/ports/make.mk index d32ef01aa..a73a685e4 100644 --- a/ports/make.mk +++ b/ports/make.mk @@ -75,15 +75,14 @@ CFLAGS += \ -DUF2_VERSION_BASE='"$(GIT_VERSION)"'\ -DUF2_VERSION='"$(GIT_VERSION) - $(GIT_SUBMODULE_VERSIONS)"'\ -# Bootloader src, board folder and TinyUSB stack +# Bootloader src and TinyUSB stack SRC_C += \ src/ghostfat.c \ src/images.c \ src/main.c \ src/msc.c \ src/screen.c \ - src/usb_descriptors.c \ - $(subst $(TOP)/,,$(wildcard $(TOP)/$(BOARD_DIR)/*.c)) + src/usb_descriptors.c endif # BUILD_APPLICATION diff --git a/ports/maxim/README.md b/ports/maxim/README.md index 547a1e81f..acbb63843 100644 --- a/ports/maxim/README.md +++ b/ports/maxim/README.md @@ -1,6 +1,4 @@ -# TinyUF2 - MAX32690 Port - -This folder contains the port of TinyUF2 for Analog Devices' MAX32xxx/MAX78000 MCUs. +# TinyUF2 for Analog Maxim ## Navigation @@ -22,13 +20,15 @@ This folder contains the port of TinyUF2 for Analog Devices' MAX32xxx/MAX78000 M - [Re-Entering Bootloader Mode](#re-entering-bootloader-mode) - [Port Directory Structure](#port-directory-structure) +## Supported Boards + +See the board list for this family in [supported_boards.md](../../supported_boards.md#maxim). ## Requirements This guide focuses on building TinyUF2 for Analog Devices' MAX32 parts. It is written with Windows users in mind using the **MSDK**, but TinyUF2 is fully portable and can be built with a standard toolchain on Linux and macOS. - ### Requirements for Linux/macOS (Generic) You do **not** need the MSDK to build TinyUF2 on Linux or macOS. @@ -49,7 +49,6 @@ or python tools/get_deps.py --board apard32690 ``` - #### macOS Dependency Install ```bash brew install arm-none-eabi-gcc make cmake git diff --git a/ports/mimxrt10xx/CMakeLists.txt b/ports/mimxrt10xx/CMakeLists.txt index 45f08ffb6..62761374d 100644 --- a/ports/mimxrt10xx/CMakeLists.txt +++ b/ports/mimxrt10xx/CMakeLists.txt @@ -25,8 +25,12 @@ family_configure_tinyuf2(tinyuf2 OPT_MCU_MIMXRT1XXX) family_flash_sdp(tinyuf2) family_flash_jlink(tinyuf2 hex) +# erase first 64KB to ensure clean state for UF2 update +math(EXPR ERASE_END_ADDR "( ${FLASH_BASE} + 0x10000 )" OUTPUT_FORMAT HEXADECIMAL) +family_jlink_erase_external(tinyuf2 ${FLASH_BASE} ${ERASE_END_ADDR}) + # imxrt run entirely on SRAM and can update its self using uf2 -family_gen_uf2_from_bin(tinyuf2 ${UF2_FAMILY_ID} ${UF2_ADDR}) +family_gen_uf2_from_bin(tinyuf2 ${UF2_FAMILY_ID} ${FLASH_FCFB_ADDR}) family_flash_uf2(tinyuf2 ${UF2_FAMILY_ID}) # copy to ARTIFACT_PATH diff --git a/ports/mimxrt10xx/Makefile b/ports/mimxrt10xx/Makefile index 98e664e5a..e5ae7942f 100644 --- a/ports/mimxrt10xx/Makefile +++ b/ports/mimxrt10xx/Makefile @@ -23,19 +23,26 @@ SELF_UF2 = $(BUILD)/update-$(OUTNAME).uf2 include ../rules.mk #--------------------------------------------------------- -# Load to SRAM using sdphost -# Note: you may need to give the sdphost binary executable permission first. +# Load to SRAM using sdphost/blhost +# sdphost/blhost loads the image into the RAM locations specified in the .ld files. # -# SDP loads the image into the RAM locations specified in the .ld files. +# sdphost (rt10xx) # - "SDP Write Address" must equal _fcfb_origin # - "SDP Jump Address" must equal _ivt_origin # -# TinyUF2 will copy itself to the correct location in flash. -# "UF2 Write Address" shows where the image will reside in flash if you -# want to use a tool like pyocd to write the binary into flash through SWD -# Note: The .elf file cannot be written directly to flash since the target -# is RAM and the addresses need to be translated. +# blhost (rt117x) +# - "Load Address" must equal _fcfb_origin +# +# TinyUF2 will copy itself to the correct location in flash. "FLASH_FCFB_ADDR" shows where the image will reside in +# flash if you want to use a tool like pyocd to write the binary into flash through SWD +# Note: The .elf file cannot be written directly to flash since the target is RAM and the addresses need to be +# translated. #--------------------------------------------------------- + +# SDPHOST/BLHOST are variables if you need to change the path +SDPHOST ?= sdphost +BLHOST ?= blhost + SDP_MIMXRT1011_PID = 0x0145 SDP_MIMXRT1015_PID = 0x0130 SDP_MIMXRT1021_PID = 0x0130 @@ -46,33 +53,19 @@ SDP_MIMXRT1062_PID = 0x0135 SDP_MIMXRT1064_PID = 0x0135 SDP_MIMXRT1176_PID = 0x013d -UF2_MIMXRT1011_ADDR= 0x60000400 -UF2_MIMXRT1015_ADDR= 0x60000000 -UF2_MIMXRT1021_ADDR= 0x60000000 -UF2_MIMXRT1024_ADDR= 0x60000000 -UF2_MIMXRT1042_ADDR= 0x60000000 -UF2_MIMXRT1052_ADDR= 0x60000000 -UF2_MIMXRT1062_ADDR= 0x60000000 -UF2_MIMXRT1064_ADDR= 0x70000000 -UF2_MIMXRT1176_ADDR= 0x30000400 - SDP_PID = $(SDP_$(MCU)_PID) -UF2_ADDR = $(UF2_$(MCU)_ADDR) - -DBL_TAP_REG_ADDR = 0x400D410C -# extract _fcfb_origin from linker file +# extract _fcfb_origin and _flash_base from linker file FCFB_ORIGIN := $(shell sed -n 's/_fcfb_origin.*\(0x.*\);/\1/p' $(TOP)/$(PORT_DIR)/linker/$(MCU)_ram.ld) IVT_ORIGIN := $(shell printf "0x%X\n" $$(( ($(FCFB_ORIGIN) & ~0xFFF) + 0x1000 ))) -$(info FCFB_ORIGIN=$(FCFB_ORIGIN) IVT_ORIGIN=$(IVT_ORIGIN)) +FLASH_BASE := $(shell sed -n 's/_flash_base.*\(0x.*\);/\1/p' $(TOP)/$(PORT_DIR)/linker/$(MCU)_ram.ld) +FLASH_FCFB_ADDR := $(shell printf "0x%X\n" $$(( $(FLASH_BASE) + ($(FCFB_ORIGIN) & 0xFFF) ))) +$(info FCFB_ORIGIN=$(FCFB_ORIGIN) IVT_ORIGIN=$(IVT_ORIGIN) FLASH_FCFB_ADDR=$(FLASH_FCFB_ADDR)) -$(BUILD)/$(OUTNAME).hex: $(BUILD)/$(OUTNAME).elf +$(BUILD)/$(OUTNAME).hex: $(BUILD)/$(OUTNAME).bin @echo CREATE $@ - @$(OBJCOPY) -O ihex --change-addresses $$(( $(UF2_ADDR)-$(FCFB_ORIGIN) )) $^ $@ + @$(OBJCOPY) -Ibinary -Oihex --change-addresses ${FLASH_FCFB_ADDR} $^ $@ -# SDPHOST/BLHOST are variables if you need to change the path -SDPHOST = sdphost -BLHOST = blhost # RT117x uses blhost (MCU bootloader protocol) ifeq ($(MCU),MIMXRT1176) @@ -100,7 +93,7 @@ self-update: $(SELF_UF2) # self-update uf2 file $(SELF_UF2): $(BUILD)/$(OUTNAME).bin @echo CREATE $@ - $(UF2CONV_PY) -f $(UF2_FAMILY_ID) -b $(UF2_ADDR) -c -o $@ $< + $(UF2CONV_PY) -f $(UF2_FAMILY_ID) -b ${FLASH_FCFB_ADDR} -c -o $@ $< # flash by copying uf2 flash-uf2: $(SELF_UF2) diff --git a/ports/mimxrt10xx/README.md b/ports/mimxrt10xx/README.md index 23189d965..c483aeb6d 100644 --- a/ports/mimxrt10xx/README.md +++ b/ports/mimxrt10xx/README.md @@ -1,8 +1,12 @@ -# TinyUF2 for iMXRT +# TinyUF2 for NXP iMXRT TinyUF2 port of iMXRT runs entirely on SRAM which is not only superfast but also easy to perform self-update. After powering on, if TinyUF2 already exists on external flash, it will be loaded to internal SRAM and start executing from -there. +there i.e. flash-stored ram-executed + +## Supported Boards + +See the board list for this family in [supported_boards.md](../../supported_boards.md#mimxrt10xx). ## Build (CMake preferred) @@ -88,17 +92,6 @@ Double tap to enter bootloader mode, then simply drag & drop `update-tinyuf2_BOA update file can be generated by running the `self-update` target (Make or CMake) or simply download it from [release page](https://github.com/adafruit/tinyuf2/releases). -## Supported Boards - -- [Adafruit Metro M7 1011](https://www.adafruit.com/product/4950) -- [MIMX RT1010 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1010-evaluation-kit:MIMXRT1010-EVK) -- [MIMX RT1020 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1020-evaluation-kit:MIMXRT1020-EVK) -- [MIMX RT1060 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1060-evk-i.mx-rt1060-evaluation-kit:MIMXRT1060-EVK) -- [MIMX RT1170 Evaluation Kit](https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK) -- [Teensy 4.0](https://www.pjrc.com/store/teensy40.html) -- [Teensy 4.1](https://www.pjrc.com/store/teensy41.html) - - ## Linux hidraw access Linux requires setting permissions for accessing hidraw devices. This is done by adding udev rules. Follow these instructions to add permission. diff --git a/ports/mimxrt10xx/app.cmake b/ports/mimxrt10xx/app.cmake index c7ae0f024..51be94035 100644 --- a/ports/mimxrt10xx/app.cmake +++ b/ports/mimxrt10xx/app.cmake @@ -10,6 +10,9 @@ endfunction() function(family_configure_app TARGET) family_configure_common(${TARGET}) + target_compile_definitions(${TARGET} PUBLIC + BUILD_APPLICATION=1 + ) target_link_options(${TARGET} PUBLIC "LINKER:--script=${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_ram.ld" "LINKER:--script=${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/app.ld" diff --git a/ports/mimxrt10xx/apps/factory_test_metro_sd/CMakeLists.txt b/ports/mimxrt10xx/apps/factory_test_metro_sd/CMakeLists.txt index a67fcbcfc..d0ddd2a4f 100644 --- a/ports/mimxrt10xx/apps/factory_test_metro_sd/CMakeLists.txt +++ b/ports/mimxrt10xx/apps/factory_test_metro_sd/CMakeLists.txt @@ -29,42 +29,3 @@ add_sdmmc(factory_test_metro_sd) family_configure_app(factory_test_metro_sd) family_add_tinyusb(factory_test_metro_sd OPT_MCU_MIMXRT1XXX) - -#------------------------------------ -# -#------------------------------------ -#include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) -# -## gets PROJECT name for the example (e.g. -) -#family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) -# -#project(${PROJECT} C CXX ASM) -# -## Checks this example is valid for the family and initializes the project -#family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) -# -## Espressif has its own cmake build system -#if(FAMILY STREQUAL "espressif") -# return() -#endif() -# -#add_executable(${PROJECT}) -# -## Example source -#target_sources(${PROJECT} PUBLIC -# arduino.c -# main.c -# usb_descriptors.c -# ) -# -## Example include -#target_include_directories(${PROJECT} PUBLIC -# src -# ) -# -#include(middleware-sdmmc/CMakeLists.txt) -#add_sdmmc(${PROJECT}) -# -## Configure compilation flags and libraries for the example... see the corresponding function -## in hw/bsp/FAMILY/family.cmake for details. -#family_configure_device_example(${PROJECT} noos) diff --git a/ports/mimxrt10xx/board_flash.c b/ports/mimxrt10xx/board_flash.c index a538f7b69..62842fa7a 100644 --- a/ports/mimxrt10xx/board_flash.c +++ b/ports/mimxrt10xx/board_flash.c @@ -24,47 +24,74 @@ #include "board_api.h" #include "romapi_flash.h" -#include "fsl_flexspi_nor_boot.h" - -// compare and write tinyuf2 to flash every time it is running -#define COMPARE_AND_WRITE_TINYUF2 0 - -#define FLASH_CACHE_SIZE 4096 -#define SECTOR_SIZE (4 * 1024) -#define FLASH_CACHE_INVALID_ADDR 0xffffffff -#define FLASH_PAGE_SIZE 256 - -// on-board flash is connected to FLEXSPI2 on rt1064 -#if defined(MIMXRT1064_SERIES) - #define FLEXSPI_INSTANCE 1 - #define FLEXSPI_FLASH_BASE FlexSPI2_AMBA_BASE -#elif defined(MIMXRT1176_cm7_SERIES) - #define FLEXSPI_INSTANCE 1 - #define FLEXSPI_FLASH_BASE FlexSPI1_AMBA_BASE + +// FLEXSPI_INSTANCE is based on FLASH_BASE defined in fsl_flexspi_nor_boot.h +#if defined(MIMXRT1064_SERIES) || defined(MIMXRT1176_cm7_SERIES) + #define FLEXSPI_INSTANCE 1 #else - #define FLEXSPI_INSTANCE 0 - #define FLEXSPI_FLASH_BASE FlexSPI_AMBA_BASE + #define FLEXSPI_INSTANCE 0 #endif // Mask off lower 12 bits to get FCFB offset -#define FLASH_FCFB_ADDR (FLEXSPI_FLASH_BASE + (((uint32_t)_fcfb_origin) & 0xFFFl)) -#define FLASH_IVT_ADDR (FLEXSPI_FLASH_BASE + 0x1000) +#define FLASH_FCFB_ADDR (FLASH_BASE + (((uint32_t)_fcfb_origin) & 0xFFFl)) +#define FLASH_IVT_ADDR (FLASH_BASE + 0x1000) //--------------------------------------------------------------------+ -// +// IVT and BOOT Data //--------------------------------------------------------------------+ - -// Flash Configuration Structure -extern flexspi_nor_config_t const qspiflash_config; -static flexspi_nor_config_t flash_cfg; // local copy since ROM API may modify it +// The FCFB has different offsets, but the IVT is consistent within the family +#define BOARD_BOOT_START (((uint32_t)_ivt_origin) - 0x1000) + +// The ROM bootloader loader needs instructed to +// copy the text section, IVT structure and interrupt table. +#define BOARD_BOOT_LENGTH ((uint32_t)&_board_boot_length) + +__attribute__((section(".boot_hdr.ivt"))) const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +__attribute__((section(".boot_hdr.boot_data"))) const BOOT_DATA_T g_boot_data = { + BOARD_BOOT_START, /* boot start location */ + BOARD_BOOT_LENGTH, PLUGIN_FLAG, /* Plugin flag */ + 0xFFFFFFFF /* empty - extra data word */ +}; + +const uint8_t dcd_data[] = {0x00}; #if defined(MIMXRT1176_cm7_SERIES) #define USE_BLHOST -extern const flexspi_nor_config_t qspiflash_config_copy; -extern const BOOT_DATA_T g_boot_data_copy; -extern const ivt image_vector_table; + +// For blhost image-load, to create ivt at zero address we cooks boot data and left-out fcfb section. We need a copy to +// write to flash. +const BOOT_DATA_T g_boot_data_copy = { + BOARD_BOOT_START, /* boot start location */ + BOARD_BOOT_LENGTH, /* bootloader length */ + PLUGIN_FLAG, /* Plugin flag */ + 0xFFFFFFFF /* empty - extra data word */ +}; + +extern const flexspi_nor_config_t flash_nor_config_copy; #endif +//--------------------------------------------------------------------+ +// Flash with Caching +//--------------------------------------------------------------------+ +// Flash Configuration Structure +extern const flexspi_nor_config_t flash_nor_config; +static flexspi_nor_config_t flash_cfg; // local copy since ROM API may modify it + +#define FLASH_CACHE_SIZE 4096 +#define SECTOR_SIZE (4 * 1024) +#define FLASH_CACHE_INVALID_ADDR 0xffffffff +#define FLASH_PAGE_SIZE 256 + static uint32_t _flash_page_addr = FLASH_CACHE_INVALID_ADDR; static uint8_t _flash_cache[SECTOR_SIZE] __attribute__((aligned(4))); @@ -79,7 +106,7 @@ static void write_tinyuf2_to_flash(void) { #ifdef USE_BLHOST // blhost load-image with ivt at address 0, no FCFB in RAM, manual write it using copies // Write FCFB - board_flash_write(FLASH_FCFB_ADDR, &qspiflash_config_copy, sizeof(flexspi_nor_config_t)); + board_flash_write(FLASH_FCFB_ADDR, &flash_nor_config_copy, sizeof(flexspi_nor_config_t)); // Write IVT (image vector table + boot data) board_flash_write(FLASH_IVT_ADDR, &image_vector_table, sizeof(ivt)); @@ -91,10 +118,10 @@ static void write_tinyuf2_to_flash(void) { uint32_t flash_addr = FLASH_IVT_ADDR + ((uint32_t)_ivt_length); #else // sdphost write from fcfb to end of bootloader - const uint8_t *image_data = (const uint8_t *)&qspiflash_config; + const uint8_t *image_data = (const uint8_t *)&flash_nor_config; uint32_t flash_addr = FLASH_FCFB_ADDR; #endif - const uint32_t flash_end = FLEXSPI_FLASH_BASE + BOARD_BOOT_LENGTH; + const uint32_t flash_end = FLASH_BASE + BOARD_BOOT_LENGTH; while (flash_addr < flash_end) { board_flash_write(flash_addr, image_data, FLASH_PAGE_SIZE); @@ -105,14 +132,13 @@ static void write_tinyuf2_to_flash(void) { TUF2_LOG1("TinyUF2 copied to flash.\r\n"); } -void board_flash_init(void) -{ +void board_flash_init(void) { #if defined(MIMXRT1176_cm7_SERIES) // MIMXRT1176 requires ROM_API_Init to be called before using ROM API functions ROM_API_Init(); - flash_cfg = qspiflash_config_copy; + flash_cfg = flash_nor_config_copy; #else - flash_cfg = qspiflash_config; + flash_cfg = flash_nor_config; #endif ROM_FLEXSPI_NorFlash_Init(FLEXSPI_INSTANCE, &flash_cfg); @@ -135,12 +161,11 @@ void board_flash_init(void) uint32_t board_flash_size(void) { // TODO currently limit at 8MB since the CURRENT.UF2 can occupies all 32MB virtual disk - uint32_t const max_size = 8*1024*1024; + const uint32_t max_size = 8 * 1024 * 1024; return (BOARD_FLASH_SIZE < max_size) ? BOARD_FLASH_SIZE : max_size; } -void board_flash_read(uint32_t addr, void* buffer, uint32_t len) -{ +void board_flash_read(uint32_t addr, void *buffer, uint32_t len) { // Must write out anything in cache before trying to read. // board_flash_flush(); @@ -158,7 +183,7 @@ void board_flash_flush(void) { // Skip if data is the same if (memcmp(_flash_cache, (void *)_flash_page_addr, SECTOR_SIZE) != 0) { - const uint32_t sector_addr = (_flash_page_addr - FLEXSPI_FLASH_BASE); + const uint32_t sector_addr = (_flash_page_addr - FLASH_BASE); __disable_irq(); status = ROM_FLEXSPI_NorFlash_Erase(FLEXSPI_INSTANCE, &flash_cfg, sector_addr, SECTOR_SIZE); @@ -167,23 +192,20 @@ void board_flash_flush(void) { // Use absolute address for cache invalidation, not the offset SCB_InvalidateDCache_by_Addr((uint32_t *)_flash_page_addr, SECTOR_SIZE); - if ( status != kStatus_Success ) - { + if (status != kStatus_Success) { TUF2_LOG1("Erase failed: status = %ld!\r\n", status); return; } - for ( int i = 0; i < SECTOR_SIZE / FLASH_PAGE_SIZE; ++i ) - { - uint32_t const page_addr = sector_addr + i * FLASH_PAGE_SIZE; - void* page_data = _flash_cache + i * FLASH_PAGE_SIZE; + for (int i = 0; i < SECTOR_SIZE / FLASH_PAGE_SIZE; ++i) { + const uint32_t page_addr = sector_addr + i * FLASH_PAGE_SIZE; + void *page_data = _flash_cache + i * FLASH_PAGE_SIZE; __disable_irq(); status = ROM_FLEXSPI_NorFlash_ProgramPage(FLEXSPI_INSTANCE, &flash_cfg, page_addr, (uint32_t *)page_data); __enable_irq(); - if ( status != kStatus_Success ) - { + if (status != kStatus_Success) { TUF2_LOG1("Page program failed: status = %ld!\r\n", status); return; } @@ -206,7 +228,7 @@ bool board_flash_write(uint32_t addr, const void *src, uint32_t len) { _flash_page_addr = page_addr; // Copy the current contents of the entire page into the cache. - memcpy(_flash_cache, (void*) page_addr, SECTOR_SIZE); + memcpy(_flash_cache, (void *)page_addr, SECTOR_SIZE); } // Overwrite part or all of the page cache with the src data. @@ -215,8 +237,7 @@ bool board_flash_write(uint32_t addr, const void *src, uint32_t len) { return true; } -void board_flash_erase_app(void) -{ +void board_flash_erase_app(void) { TUF2_LOG1("Erase whole chip\r\n"); // Perform chip erase first @@ -228,9 +249,8 @@ void board_flash_erase_app(void) write_tinyuf2_to_flash(); } -bool board_flash_protect_bootloader(bool protect) -{ +bool board_flash_protect_bootloader(bool protect) { // TODO implement later - (void) protect; + (void)protect; return false; } diff --git a/ports/mimxrt10xx/boards.c b/ports/mimxrt10xx/boards.c index 1405ccf3b..030f942f4 100644 --- a/ports/mimxrt10xx/boards.c +++ b/ports/mimxrt10xx/boards.c @@ -33,87 +33,65 @@ #include "fsl_pwm.h" #include "fsl_xbara.h" -#include "clock_config.h" +#include "board/pin_mux.h" +#include "board/clock_config.h" #ifndef BUILD_NO_TINYUSB -#include "tusb.h" + #include "tusb.h" #endif static bool _dfu_mode = false; -// needed by fsl_flexspi_nor_boot -const uint8_t dcd_data[] = { 0x00 }; - -void board_init(void) -{ +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ +void board_init(void) { #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) SCB_EnableDCache(); + if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_EnableDCache(); + } #endif - // Init clock + BOARD_InitBootPins(); BOARD_BootClockRUN(); - // TODO System clock update could cause incorrect neopixel timing, make sure it right later - // SystemCoreClockUpdate(); - board_timer_stop(); - // Enable IOCON clock - CLOCK_EnableClock(kCLOCK_Iomuxc); - // Prevent clearing of SNVS General Purpose Register SNVS->LPCR |= SNVS_LPCR_GPR_Z_DIS_MASK; -#ifdef LED_PINMUX - IOMUXC_SetPinMux(LED_PINMUX, 0); - IOMUXC_SetPinConfig(LED_PINMUX, 0x10B0U); - - gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode }; - GPIO_PinInit(LED_PORT, LED_PIN, &led_config); -#endif - -#if NEOPIXEL_NUMBER - IOMUXC_SetPinMux(NEOPIXEL_PINMUX, 0); - IOMUXC_SetPinConfig(NEOPIXEL_PINMUX, 0x10B0U); - - gpio_pin_config_t neopixel_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode }; - GPIO_PinInit(NEOPIXEL_PORT, NEOPIXEL_PIN, &neopixel_config); -#endif - #if TUF2_LOG board_uart_init(BOARD_UART_BAUDRATE); #endif } -void board_teardown(void) -{ - // no GPIO deinit for GPIO: LED, Neopixel, Button +void board_teardown(void) { + // no GPIO deinit for GPIO: LED, Neopixel #if TUF2_LOG && defined(UART_DEV) LPUART_Deinit(UART_DEV); #endif } -void board_usb_init(void) -{ - USBPHY_Type* usb_phy; +void board_usb_init(void) { + USBPHY_Type *usb_phy; #ifdef USB_PWR_PINMUX // Enable USB power pin if defined by board (active high) IOMUXC_SetPinMux(USB_PWR_PINMUX, 0); IOMUXC_SetPinConfig(USB_PWR_PINMUX, 0x10B0U); - gpio_pin_config_t usb_pwr_config = { kGPIO_DigitalOutput, 1, kGPIO_NoIntmode }; + gpio_pin_config_t usb_pwr_config = {kGPIO_DigitalOutput, 1, kGPIO_NoIntmode}; GPIO_PinInit(USB_PWR_PORT, USB_PWR_PIN, &usb_pwr_config); #endif #if BOARD_TUD_RHPORT == 0 // Clock -#if defined(MIMXRT1176_cm7_SERIES) + #if defined(MIMXRT1176_cm7_SERIES) // RT1176 USB PHY PLL expects reference clock frequency (24MHz from OSC24M) // PLL multiplies by 20 to get 480MHz: 24MHz * 20 = 480MHz CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 24000000U); -#else + #else CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); -#endif + #endif CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); #ifdef USBPHY1 @@ -124,11 +102,11 @@ void board_usb_init(void) #elif BOARD_TUD_RHPORT == 1 // USB1 -#if defined(MIMXRT1176_cm7_SERIES) + #if defined(MIMXRT1176_cm7_SERIES) CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 24000000U); -#else + #else CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U); -#endif + #endif CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U); usb_phy = USBPHY2; #endif @@ -141,22 +119,22 @@ void board_usb_init(void) // TX Timing - use board-specific values if defined, otherwise defaults #ifndef BOARD_USB_PHY_D_CAL -#define BOARD_USB_PHY_D_CAL (0x0CU) + #define BOARD_USB_PHY_D_CAL (0x0CU) #endif #ifndef BOARD_USB_PHY_TXCAL45DP -#define BOARD_USB_PHY_TXCAL45DP (0x06U) + #define BOARD_USB_PHY_TXCAL45DP (0x06U) #endif #ifndef BOARD_USB_PHY_TXCAL45DM -#define BOARD_USB_PHY_TXCAL45DM (0x06U) + #define BOARD_USB_PHY_TXCAL45DM (0x06U) #endif uint32_t phytx = usb_phy->TX; phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK); - phytx |= USBPHY_TX_D_CAL(BOARD_USB_PHY_D_CAL) | USBPHY_TX_TXCAL45DP(BOARD_USB_PHY_TXCAL45DP) | USBPHY_TX_TXCAL45DM(BOARD_USB_PHY_TXCAL45DM); + phytx |= USBPHY_TX_D_CAL(BOARD_USB_PHY_D_CAL) | USBPHY_TX_TXCAL45DP(BOARD_USB_PHY_TXCAL45DP) | + USBPHY_TX_TXCAL45DM(BOARD_USB_PHY_TXCAL45DM); usb_phy->TX = phytx; } -void board_dfu_init(void) -{ +void board_dfu_init(void) { board_usb_init(); _dfu_mode = true; @@ -180,35 +158,32 @@ void board_dfu_init(void) PWM_Init(LED_PWM_BASE, LED_PWM_MODULE, &pwmConfig); - pwm_signal_param_t pwmSignal = - { - .pwmChannel = LED_PWM_CHANNEL, - .dutyCyclePercent = 0, - .level = LED_STATE_ON ? kPWM_HighTrue : kPWM_LowTrue, - .deadtimeValue = 0, - .faultState = kPWM_PwmFaultState0 - }; - PWM_SetupPwm(LED_PWM_BASE, LED_PWM_MODULE, &pwmSignal, 1, kPWM_SignedCenterAligned, 5000, CLOCK_GetFreq(kCLOCK_IpgClk)); + pwm_signal_param_t pwmSignal = {.pwmChannel = LED_PWM_CHANNEL, + .dutyCyclePercent = 0, + .level = LED_STATE_ON ? kPWM_HighTrue : kPWM_LowTrue, + .deadtimeValue = 0, + .faultState = kPWM_PwmFaultState0}; + PWM_SetupPwm(LED_PWM_BASE, LED_PWM_MODULE, &pwmSignal, 1, kPWM_SignedCenterAligned, 5000, + CLOCK_GetFreq(kCLOCK_IpgClk)); PWM_SetPwmLdok(LED_PWM_BASE, 1 << LED_PWM_MODULE, true); PWM_StartTimer(LED_PWM_BASE, 1 << LED_PWM_MODULE); #endif } -uint8_t board_usb_get_serial(uint8_t serial_id[16]) -{ - #if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL +uint8_t board_usb_get_serial(uint8_t serial_id[16]) { +#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk)); - #else +#else OCOTP_Init(OCOTP, 0u); - #endif +#endif // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info) // into 8 bit wide destination, avoiding punning. for (int i = 0; i < 4; ++i) { uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1); for (int j = 0; j < 4; j++) { - serial_id[i*4+j] = wr & 0xff; + serial_id[i * 4 + j] = wr & 0xff; wr >>= 8; } } @@ -217,19 +192,16 @@ uint8_t board_usb_get_serial(uint8_t serial_id[16]) return 16; } -void board_reset(void) -{ +void board_reset(void) { NVIC_SystemReset(); } -void board_dfu_complete(void) -{ +void board_dfu_complete(void) { NVIC_SystemReset(); } -bool board_app_valid(void) -{ - volatile uint32_t const * app_vector = (volatile uint32_t const*) BOARD_FLASH_APP_START; +bool board_app_valid(void) { + const volatile uint32_t *app_vector = (const volatile uint32_t *)BOARD_FLASH_APP_START; // 1st word is stack pointer (should be in SRAM region) @@ -241,22 +213,21 @@ bool board_app_valid(void) return true; } -void board_app_jump(void) -{ +void board_app_jump(void) { // Create the function call to the user application. // Static variables are needed since changed the stack pointer out from under the compiler // we need to ensure the values we are using are not stored on the previous stack static uint32_t stack_pointer; static uint32_t app_entry; - uint32_t const * app_vector = (uint32_t const*) BOARD_FLASH_APP_START; - stack_pointer = app_vector[0]; - app_entry = app_vector[1]; + const uint32_t *app_vector = (const uint32_t *)BOARD_FLASH_APP_START; + stack_pointer = app_vector[0]; + app_entry = app_vector[1]; // TODO protect bootloader region /* switch exception handlers to the application */ - SCB->VTOR = (uint32_t) BOARD_FLASH_APP_START; + SCB->VTOR = (uint32_t)BOARD_FLASH_APP_START; // Set stack pointer __set_MSP(stack_pointer); @@ -269,81 +240,70 @@ void board_app_jump(void) //--------------------------------------------------------------------+ // Timer //--------------------------------------------------------------------+ - -void board_timer_start(uint32_t ms) -{ +void board_timer_start(uint32_t ms) { // due to highspeed SystemCoreClock = 600 mhz, max interval of 24 bit systick is only 27 ms - const uint32_t tick = (SystemCoreClock/1000) * ms; - SysTick_Config( tick ); + const uint32_t tick = (SystemCoreClock / 1000) * ms; + SysTick_Config(tick); } -void board_timer_stop(void) -{ +void board_timer_stop(void) { SysTick->CTRL = 0; } -void SysTick_Handler(void) -{ +void SysTick_Handler(void) { board_timer_handler(); } //--------------------------------------------------------------------+ // LED / RGB //--------------------------------------------------------------------+ - -void board_led_write(uint32_t value) -{ -#ifdef LED_PINMUX +void board_led_write(uint32_t value) { #ifdef LED_PWM_PINMUX - if (_dfu_mode) - { + if (_dfu_mode) { uint8_t duty = (value * 100) / 0xff; PWM_UpdatePwmDutycycle(LED_PWM_BASE, LED_PWM_MODULE, LED_PWM_CHANNEL, kPWM_SignedCenterAligned, duty); PWM_SetPwmLdok(LED_PWM_BASE, 1 << LED_PWM_MODULE, true); - }else + } else #endif { value = (value >= 128) ? 1 : 0; - GPIO_PinWrite(LED_PORT, LED_PIN, value ? LED_STATE_ON : (1-LED_STATE_ON)); + GPIO_PinWrite(LED_PORT, LED_PIN, value ? LED_STATE_ON : (1 - LED_STATE_ON)); } -#endif } #if NEOPIXEL_NUMBER -#define MAGIC_800_INT 900000 // ~1.11 us -> 1.2 field -#define MAGIC_800_T0H 2800000 // ~0.36 us -> 0.44 field -#define MAGIC_800_T1H 1350000 // ~0.74 us -> 0.84 field + #define MAGIC_800_INT 900000 // ~1.11 us -> 1.2 field + #define MAGIC_800_T0H 2800000 // ~0.36 us -> 0.44 field + #define MAGIC_800_T1H 1350000 // ~0.74 us -> 0.84 field -static inline uint8_t apply_percentage(uint8_t brightness) -{ - return (uint8_t) ((brightness*NEOPIXEL_BRIGHTNESS) >> 8); +static inline uint8_t apply_percentage(uint8_t brightness) { + return (uint8_t)((brightness * NEOPIXEL_BRIGHTNESS) >> 8); } -void board_rgb_write(uint8_t const rgb[]) -{ +void board_rgb_write(const uint8_t rgb[]) { enum { PIN_MASK = (1u << NEOPIXEL_PIN) }; // neopixel color order is GRB - uint8_t const pixels[3] = { apply_percentage(rgb[1]), apply_percentage(rgb[0]), apply_percentage(rgb[2]) }; - uint32_t const numBytes = 3; + const uint8_t pixels[3] = {apply_percentage(rgb[1]), apply_percentage(rgb[0]), apply_percentage(rgb[2])}; + const uint32_t numBytes = 3; - uint8_t const *p = pixels, *end = p + numBytes; - uint8_t pix = *p++, mask = 0x80; - uint32_t start = 0; - uint32_t cyc = 0; + const uint8_t *p = pixels, *end = p + numBytes; + uint8_t pix = *p++, mask = 0x80; + uint32_t start = 0; + uint32_t cyc = 0; - //assumes 800_000Hz frequency - //Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us - //TODO: try to get dynamic weighting working again - uint32_t const sys_freq = SystemCoreClock; - uint32_t const interval = sys_freq/MAGIC_800_INT; - uint32_t const t0 = sys_freq/MAGIC_800_T0H; - uint32_t const t1 = sys_freq/MAGIC_800_T1H; + // assumes 800_000Hz frequency + // Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us + // TODO: try to get dynamic weighting working again + const uint32_t sys_freq = SystemCoreClock; + const uint32_t interval = sys_freq / MAGIC_800_INT; + const uint32_t t0 = sys_freq / MAGIC_800_T0H; + const uint32_t t1 = sys_freq / MAGIC_800_T1H; - volatile uint32_t* reg_set = &NEOPIXEL_PORT->DR_SET; - volatile uint32_t* reg_clr = &NEOPIXEL_PORT->DR_CLEAR; + volatile uint32_t *reg_set = &NEOPIXEL_PORT->DR_SET; + volatile uint32_t *reg_clr = &NEOPIXEL_PORT->DR_CLEAR; __disable_irq(); @@ -352,19 +312,23 @@ void board_rgb_write(uint8_t const rgb[]) DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; DWT->CYCCNT = 0; - while(1) { + while (1) { cyc = (pix & mask) ? t1 : t0; - while((DWT->CYCCNT - start) < interval); + while ((DWT->CYCCNT - start) < interval) + ; start = DWT->CYCCNT; *reg_set = PIN_MASK; - while((DWT->CYCCNT - start) < cyc); + while ((DWT->CYCCNT - start) < cyc) + ; *reg_clr = PIN_MASK; - if(!(mask >>= 1)) { - if(p >= end) break; + if (!(mask >>= 1)) { + if (p >= end) { + break; + } pix = *p++; mask = 0x80; } @@ -375,9 +339,8 @@ void board_rgb_write(uint8_t const rgb[]) #else -void board_rgb_write(uint8_t const rgb[]) -{ - (void) rgb; +void board_rgb_write(uint8_t const rgb[]) { + (void)rgb; } #endif @@ -385,66 +348,53 @@ void board_rgb_write(uint8_t const rgb[]) //--------------------------------------------------------------------+ // UART //--------------------------------------------------------------------+ - #ifdef UART_DEV -void board_uart_init(uint32_t baud_rate) -{ - // Enable UART when debug log is on - IOMUXC_SetPinMux(UART_RX_PINMUX, 0); - IOMUXC_SetPinMux(UART_TX_PINMUX, 0); - - IOMUXC_SetPinConfig(UART_RX_PINMUX, 0x10A0U); - IOMUXC_SetPinConfig(UART_TX_PINMUX, 0x10A0U); +void board_uart_init(uint32_t baud_rate) { + BOARD_InitDEBUG_UARTPins(); lpuart_config_t uart_config; LPUART_GetDefaultConfig(&uart_config); uart_config.baudRate_Bps = baud_rate; - uart_config.enableTx = true; - uart_config.enableRx = true; + uart_config.enableTx = true; + uart_config.enableRx = true; uint32_t freq; -#if defined(MIMXRT117x_SERIES) + #if defined(MIMXRT117x_SERIES) // MIMXRT1176 uses different clock API - get clock from root configuration freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1); -#else + #else if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ { freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - else - { + } else { freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); } -#endif + #endif LPUART_Init(UART_DEV, &uart_config, freq); } -int board_uart_write(void const * buf, int len) -{ - LPUART_WriteBlocking(UART_DEV, (uint8_t const*) buf, (size_t) len); +int board_uart_write(const void *buf, int len) { + LPUART_WriteBlocking(UART_DEV, (const uint8_t *)buf, (size_t)len); return len; } // optional API, not included in board_api.h -int board_uart_read(uint8_t* buf, int len) -{ +int board_uart_read(uint8_t *buf, int len) { int count = 0; - while( count < len ) - { - uint8_t const rx_count = LPUART_GetRxFifoCount(UART_DEV); - if (!rx_count) - { + while (count < len) { + const uint8_t rx_count = LPUART_GetRxFifoCount(UART_DEV); + if (!rx_count) { // clear all error flag if any uint32_t status_flags = LPUART_GetStatusFlags(UART_DEV); - status_flags &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | kLPUART_NoiseErrorFlag); + status_flags &= + (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | kLPUART_NoiseErrorFlag); LPUART_ClearStatusFlags(UART_DEV, status_flags); break; } - for(int i=0; i + + + MIMXRT1052xxxxB + MIMXRT1052DVL6B + IMXRT1050-EVKB + A + ksdk2_0 + + + + + + + false + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 0.0.0 + + + + + + + 13.0.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + kELCDIF_CurFrameDoneInterruptEnable + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + + + + diff --git a/ports/mimxrt10xx/boards/arch_mix_1052/board.cmake b/ports/mimxrt10xx/boards/arch_mix_1052/board.cmake new file mode 100644 index 000000000..8483c4781 --- /dev/null +++ b/ports/mimxrt10xx/boards/arch_mix_1052/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT MIMXRT1052) + +set(JLINK_DEVICE MIMXRT1052xxxxB) +set(PYOCD_TARGET mimxrt1052) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1052DVL6B + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/arch_mix_1052/board.h b/ports/mimxrt10xx/boards/arch_mix_1052/board.h index 5774307b1..c89ed5b34 100644 --- a/ports/mimxrt10xx/boards/arch_mix_1052/board.h +++ b/ports/mimxrt10xx/boards/arch_mix_1052/board.h @@ -34,28 +34,18 @@ //--------------------------------------------------------------------+ // LED //--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 -#define LED_PORT GPIO1 -#define LED_PIN 9 +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL #define LED_STATE_ON 0 //--------------------------------------------------------------------+ // Neopixel //--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 0 - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - +#define NEOPIXEL_NUMBER 0 // Number of neopixels //--------------------------------------------------------------------+ // USB UF2 //--------------------------------------------------------------------+ - #define USB_VID 0x2886 #define USB_PID 0x0010 #define USB_MANUFACTURER "Seeed Technology Co., Ltd." @@ -69,10 +59,6 @@ //--------------------------------------------------------------------+ // UART //--------------------------------------------------------------------+ - #define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_13_LPUART1_RXD -// On Rev A1 of the board this is on J31 closer to the edge. -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_12_LPUART1_TXD #endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/arch_mix_1052/board/clock_config.c b/ports/mimxrt10xx/boards/arch_mix_1052/board/clock_config.c new file mode 100644 index 000000000..a6b0cc203 --- /dev/null +++ b/ports/mimxrt10xx/boards/arch_mix_1052/board/clock_config.c @@ -0,0 +1,495 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: IMXRT1050-EVKB + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 40, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(40); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/ports/mimxrt10xx/boards/arch_mix_1052/board/clock_config.h b/ports/mimxrt10xx/boards/arch_mix_1052/board/clock_config.h new file mode 100644 index 000000000..c69d9aa88 --- /dev/null +++ b/ports/mimxrt10xx/boards/arch_mix_1052/board/clock_config.h @@ -0,0 +1,119 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/arch_mix_1052/board/pin_mux.c b/ports/mimxrt10xx/boards/arch_mix_1052/board/pin_mux.c new file mode 100644 index 000000000..cd1ee59f3 --- /dev/null +++ b/ports/mimxrt10xx/boards/arch_mix_1052/board/pin_mux.c @@ -0,0 +1,215 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: IMXRT1050-EVKB +pin_labels: +- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED} +- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper} + - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up_100K_Ohm} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + + /* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */ + GPIO_PinInit(GPIO1, 9U, &USER_LED_config); + + /* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on WAKEUP (pin L6) */ + GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U); + IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U); + IOMUXC_SetPinConfig(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0x01B0A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0x10B0U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0x10B0U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); +#endif +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitHyperFlashPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} + - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} + - {pin_num: L5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA3, pin_signal: GPIO_SD_B1_00} + - {pin_num: M5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA2, pin_signal: GPIO_SD_B1_01} + - {pin_num: M3, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA1, pin_signal: GPIO_SD_B1_02} + - {pin_num: M4, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA0, pin_signal: GPIO_SD_B1_03} + - {pin_num: P2, peripheral: FLEXSPI, signal: FLEXSPI_B_SCLK, pin_signal: GPIO_SD_B1_04} + - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} + - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} + - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitHyperFlashPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitHyperFlashPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); +#endif +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/arch_mix_1052/board/pin_mux.h b/ports/mimxrt10xx/boards/arch_mix_1052/board/pin_mux.h new file mode 100644 index 000000000..95ff77c38 --- /dev/null +++ b/ports/mimxrt10xx/boards/arch_mix_1052/board/pin_mux.h @@ -0,0 +1,171 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 9U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 9U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 9U) /*!< PORT pin mask */ + +/* WAKEUP (coord L6), SD_PWREN */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_B_SIGNAL FLEXSPI_B_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_B_SIGNAL FLEXSPI_B_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_02 (coord M3), FlexSPI_D1_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_B_SIGNAL FLEXSPI_B_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_03 (coord M4), FlexSPI_D0_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_B_SIGNAL FLEXSPI_B_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_04 (coord P2), FlexSPI_CLK_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_B_SIGNAL FLEXSPI_B_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitHyperFlashPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/arch_mix_1052/clock_config.c b/ports/mimxrt10xx/boards/arch_mix_1052/clock_config.c deleted file mode 100644 index a9246fc02..000000000 --- a/ports/mimxrt10xx/boards/arch_mix_1052/clock_config.c +++ /dev/null @@ -1,934 +0,0 @@ -/* - * Copyright 2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. - * - * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. - * - * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v10.0 -processor: MIMXRT1052xxxxB -package_id: MIMXRT1052DVL6B -mcu_data: ksdk2_0 -processor_version: 0.12.10 -board: IMXRT1050-EVKB - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "clock_config.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} -settings: -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} -- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} -- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} -- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL4.denom, value: '50'} -- {id: CCM_ANALOG.PLL4.div, value: '47'} -- {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} -- {id: CCM_ANALOG.PLL5.num, value: '0'} -- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} -- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} -- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} -- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} -sources: -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .postDivider = 8, /* Divider after PLL */ - .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 1); -#endif - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Video PLL. */ - uint32_t pllVideo; - /* Disable Video PLL output before initial Video PLL. */ - CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Bypass PLL first */ - CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); - CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); - CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); - pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); - CCM_ANALOG->PLL_VIDEO = pllVideo; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - /* Disable bypass for Video PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ -#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; -#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) - /* Backward compatibility for original bitfield name */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; -#else -#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." -#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} - -/******************************************************************************* - ******************* Configuration BOARD_BootClockRUN_528M ********************* - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN_528M -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 528 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 132 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} -settings: -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} -- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} -- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} -- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL4.denom, value: '50'} -- {id: CCM_ANALOG.PLL4.div, value: '47'} -- {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} -- {id: CCM_ANALOG.PLL5.num, value: '0'} -- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} -- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} -- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} -- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} -sources: -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN_528M configuration - ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_528M = - { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_528M = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_528M = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_528M = - { - .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .postDivider = 8, /* Divider after PLL */ - .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockRUN_528M configuration - ******************************************************************************/ -void BOARD_BootClockRUN_528M(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 1); -#endif - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN_528M); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN_528M); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN_528M); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Video PLL. */ - uint32_t pllVideo; - /* Disable Video PLL output before initial Video PLL. */ - CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Bypass PLL first */ - CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); - CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); - CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); - pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); - CCM_ANALOG->PLL_VIDEO = pllVideo; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - /* Disable bypass for Video PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 0); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ -#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; -#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) - /* Backward compatibility for original bitfield name */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; -#else -#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." -#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_528M_CORE_CLOCK; -} diff --git a/ports/mimxrt10xx/boards/arch_mix_1052/clock_config.h b/ports/mimxrt10xx/boards/arch_mix_1052/clock_config.h deleted file mode 100644 index 3e4009634..000000000 --- a/ports/mimxrt10xx/boards/arch_mix_1052/clock_config.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright 2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Video PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************* Configuration BOARD_BootClockRUN_528M ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN_528M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_528M_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_528M_AHB_CLK_ROOT 528000000UL -#define BOARD_BOOTCLOCKRUN_528M_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_528M_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_528M_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_528M_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_528M_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_528M_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_528M_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_528M_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_FLEXSPI_CLK_ROOT 160000000UL -#define BOARD_BOOTCLOCKRUN_528M_GPT1_IPG_CLK_HIGHFREQ 66000000UL -#define BOARD_BOOTCLOCKRUN_528M_GPT2_IPG_CLK_HIGHFREQ 66000000UL -#define BOARD_BOOTCLOCKRUN_528M_IPG_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_528M_LCDIF_CLK_ROOT 67500000UL -#define BOARD_BOOTCLOCKRUN_528M_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_528M_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_528M_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_528M_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_PERCLK_CLK_ROOT 66000000UL -#define BOARD_BOOTCLOCKRUN_528M_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_528M_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_528M_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_528M_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_SEMC_CLK_ROOT 66000000UL -#define BOARD_BOOTCLOCKRUN_528M_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_528M_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_528M_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_528M_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_528M_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN_528M configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_528M; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN_528M configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_528M; -/*! @brief Sys PLL for BOARD_BootClockRUN_528M configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_528M; -/*! @brief Video PLL set for BOARD_BootClockRUN_528M configuration. - */ -extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_528M; - -/******************************************************************************* - * API for BOARD_BootClockRUN_528M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN_528M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/arch_mix_1052/flash_config.c b/ports/mimxrt10xx/boards/arch_mix_1052/flash_config.c index d96d588e7..f5cb1c11f 100644 --- a/ports/mimxrt10xx/boards/arch_mix_1052/flash_config.c +++ b/ports/mimxrt10xx/boards/arch_mix_1052/flash_config.c @@ -9,37 +9,10 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for IS25WP064A with QSPI after changing resistors to send signal to // QSPI instead of hyper flash! __attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { +const flexspi_nor_config_t flash_nor_config = { .pageSize = 256u, .sectorSize = 4u * 1024u, .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/board.cmake b/ports/mimxrt10xx/boards/imxrt1010_evk/board.cmake new file mode 100644 index 000000000..ec823c0e3 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT MIMXRT1011) + +set(JLINK_DEVICE MIMXRT1011DAE5A) +set(PYOCD_TARGET mimxrt1010) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1011DAE5A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/board.h b/ports/mimxrt10xx/boards/imxrt1010_evk/board.h index 2923d72bd..9a53becb3 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/board.h +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board.h @@ -1,99 +1,81 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Ha Thach for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// Size of on-board external flash -#define BOARD_FLASH_SIZE (16*1024*1024) - -//--------------------------------------------------------------------+ -// LED -//--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_11_GPIOMUX_IO11 -#define LED_PORT GPIO1 -#define LED_PIN 11 -#define LED_STATE_ON 1 - -#if 0 -// PWM Test on Arduino header D8 -#define LED_PWM_PINMUX IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A -#define LED_PWM_BASE PWM1 -#define LED_PWM_MODULE kPWM_Module_0 -#define LED_PWM_CHANNEL kPWM_PwmA -#endif - -//--------------------------------------------------------------------+ -// Neopixel -//--------------------------------------------------------------------+ - -// Number of neopixels -#if 1 -#define NEOPIXEL_NUMBER 0 - -#else -// Neopixel Test on Arduino header A0 -#define NEOPIXEL_NUMBER 1 -#define NEOPIXEL_PINMUX IOMUXC_GPIO_AD_07_GPIOMUX_IO21 -#define NEOPIXEL_PORT GPIO1 -#define NEOPIXEL_PIN 21 -#endif - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// SW8 button -#define BUTTON_PINMUX IOMUXC_GPIO_SD_05_GPIO2_IO05 -#define BUTTON_PORT GPIO2 -#define BUTTON_PIN 5 -#define BUTTON_STATE_ACTIVE 0 - -//--------------------------------------------------------------------+ -// USB UF2 -//--------------------------------------------------------------------+ - -#define USB_VID 0x239A -#define USB_PID 0x0077 -#define USB_MANUFACTURER "NXP" -#define USB_PRODUCT "RT1010 EVK" - -#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT -#define UF2_BOARD_ID "MIMXRT1010-EVK-revA" -#define UF2_VOLUME_LABEL "RT1010BOOT" -#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1010-EVK#/" - -//--------------------------------------------------------------------+ -// UART -//--------------------------------------------------------------------+ - -#define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_09_LPUART1_RXD -#define UART_TX_PINMUX IOMUXC_GPIO_10_LPUART1_TXD - -#endif /* BOARD_H_ */ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Ha Thach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Size of on-board external flash +#define BOARD_FLASH_SIZE (16*1024*1024) + +//--------------------------------------------------------------------+ +// LED +//--------------------------------------------------------------------+ +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL +#define LED_STATE_ON 1 + +#if 0 +// PWM Test on Arduino header D8 +#define LED_PWM_PINMUX IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A +#define LED_PWM_BASE PWM1 +#define LED_PWM_MODULE kPWM_Module_0 +#define LED_PWM_CHANNEL kPWM_PwmA +#endif + +//--------------------------------------------------------------------+ +// Neopixel +//--------------------------------------------------------------------+ +#if 1 +#define NEOPIXEL_NUMBER 0 // Number of neopixels + +#else + // Neopixel Test on Arduino header A0 + #define NEOPIXEL_NUMBER 1 + #define NEOPIXEL_PINMUX IOMUXC_GPIO_AD_07_GPIOMUX_IO21 + #define NEOPIXEL_PORT GPIO1 + #define NEOPIXEL_PIN 21 +#endif + +//--------------------------------------------------------------------+ +// USB UF2 +//--------------------------------------------------------------------+ +#define USB_VID 0x239A +#define USB_PID 0x0077 +#define USB_MANUFACTURER "NXP" +#define USB_PRODUCT "RT1010 EVK" + +#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT +#define UF2_BOARD_ID "MIMXRT1010-EVK-revA" +#define UF2_VOLUME_LABEL "RT1010BOOT" +#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1010-EVK#/" + +//--------------------------------------------------------------------+ +// UART +//--------------------------------------------------------------------+ +#define UART_DEV LPUART1 + +#endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/makerdiary_rt1011/clock_config.c b/ports/mimxrt10xx/boards/imxrt1010_evk/board/clock_config.c similarity index 84% rename from ports/mimxrt10xx/boards/makerdiary_rt1011/clock_config.c rename to ports/mimxrt10xx/boards/imxrt1010_evk/board/clock_config.c index 178d62a84..76cb0a480 100644 --- a/ports/mimxrt10xx/boards/makerdiary_rt1011/clock_config.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board/clock_config.c @@ -1,10 +1,3 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* * How to setup clock using clock driver functions: * @@ -22,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v6.0 +product: Clocks v18.0 processor: MIMXRT1011xxxxx package_id: MIMXRT1011DAE5A mcu_data: ksdk2_0 -processor_version: 0.0.1 +processor_version: 25.09.10 board: MIMXRT1010-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -40,8 +33,6 @@ board: MIMXRT1010-EVK /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ @@ -82,21 +73,21 @@ called_from_default_init: true - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY_CLK.outFreq, value: 480 MHz} settings: - {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} - {id: CCM.AHB_PODF.scale, value: '1', locked: true} - {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} - {id: CCM.IPG_PODF.scale, value: '4'} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5'} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} - {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} - {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} - {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.div, value: '22'} - {id: CCM_ANALOG.PLL2.num, value: '0'} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} @@ -117,29 +108,33 @@ called_from_default_init: true - {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { - .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -161,22 +156,19 @@ void BOARD_BootClockRUN(void) CLOCK_SwitchOsc(kCLOCK_XtalOsc); /* Set Oscillator ready counter value. */ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */ + /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); /* Waiting for DCDC_STS_DC_OK bit is asserted */ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Disable IPG clock gate. */ CLOCK_DisableClock(kCLOCK_Adc1); CLOCK_DisableClock(kCLOCK_Xbar1); /* Set IPG_PODF. */ CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); /* Disable PERCLK clock gate. */ CLOCK_DisableClock(kCLOCK_Gpt1); CLOCK_DisableClock(kCLOCK_Gpt1S); @@ -186,9 +178,8 @@ void BOARD_BootClockRUN(void) /* Set PERCLK_PODF. */ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); @@ -212,9 +203,9 @@ void BOARD_BootClockRUN(void) /* Disable TRACE clock gate. */ CLOCK_DisableClock(kCLOCK_Trace); /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -263,22 +254,9 @@ void BOARD_BootClockRUN(void) CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); /* Set Flexio1 clock source. */ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Init Usb1 PLL. */ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); @@ -290,9 +268,28 @@ void BOARD_BootClockRUN(void) CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); /* Init Usb1 pfd3. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif + /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */ + /* Set Pll3 SW clock source to use the USB1 PLL output. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Set safe value of the AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 1); + /* Set periph clock2 clock source to use the PLL3_SW_CLK. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); /* Bypass Audio PLL. */ @@ -302,16 +299,14 @@ void BOARD_BootClockRUN(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); /* Set preperiph clock source. */ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ CLOCK_SetMux(kCLOCK_PeriphMux, 0); /* Set periph clock2 clock source. */ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Set clock out1 divider. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); /* Set clock out1 source. */ @@ -335,7 +330,7 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/board/clock_config.h b/ports/mimxrt10xx/boards/imxrt1010_evk/board/clock_config.h new file mode 100644 index 000000000..cc627cf6a --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board/clock_config.h @@ -0,0 +1,97 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL /* Clock consumers of ADC_ALT_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL /* Clock consumers of CORE_CLK_ROOT output : ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AIPSTZ1, AIPSTZ2, AOI, ARM, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, OCOTP, PWM1, RTWDOG, SAI1, SAI3, SNVS, SPDIF, SRC, TEMPMON, TRNG, USB, WDOG1, WDOG2, XBARA */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */ + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/board/pin_mux.c b/ports/mimxrt10xx/boards/imxrt1010_evk/board/pin_mux.c new file mode 100644 index 000000000..a3a921e0c --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board/pin_mux.c @@ -0,0 +1,107 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1011xxxxx +package_id: MIMXRT1011DAE5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1010-EVK +external_user_signals: {} +pin_labels: +- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: LED;USERLED;USER_LED} +power_domains: {NVCC_GPIO: '3.3'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '70', peripheral: GPIO2, signal: 'gpio_io, 05', pin_signal: GPIO_SD_05, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm} + - {pin_num: '1', peripheral: GPIO1, signal: 'gpiomux_io, 11', pin_signal: GPIO_11, identifier: USER_LED, direction: OUTPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of USER_LED on GPIO_11 (pin 1) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_11 (pin 1) */ + GPIO_PinInit(GPIO1, 11U, &USER_LED_config); + + /* GPIO configuration of USER_BUTTON on GPIO_SD_05 (pin 70) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_SD_05 (pin 70) */ + GPIO_PinInit(GPIO2, 5U, &USER_BUTTON_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0x70A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09} + - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/board/pin_mux.h b/ports/mimxrt10xx/boards/imxrt1010_evk/board/pin_mux.h new file mode 100644 index 000000000..48cbd3714 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/board/pin_mux.h @@ -0,0 +1,104 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x0820U /*!< Select GPIO1 or GPIO2: affected bits mask */ + +/* GPIO_SD_05 (number 70), USER_BUTTON/SW4 */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 5U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 5U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 5U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 5U) /*!< PORT pin mask */ + +/* GPIO_11 (number 1), GPIO_11 */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpiomux_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 11U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 11U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 11U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 11U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 11U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */ + +/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/clock_config.h b/ports/mimxrt10xx/boards/imxrt1010_evk/clock_config.h deleted file mode 100644 index 76f3df422..000000000 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/clock_config.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL - -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c index 369760bbf..ec8a16ef0 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c @@ -9,162 +9,114 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for AT25SF128A with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 4u, + .seqNum = 1u, }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/mimxrt1010_evk.mex b/ports/mimxrt10xx/boards/imxrt1010_evk/mimxrt1010_evk.mex new file mode 100644 index 000000000..6845e45f9 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1010_evk/mimxrt1010_evk.mex @@ -0,0 +1,419 @@ + + + + MIMXRT1011xxxxx + MIMXRT1011DAE5A + MIMXRT1010-EVK + A + ksdk2_0 + + + + + + + true + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 0.0.0 + + + + + + + 13.0.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/board.cmake b/ports/mimxrt10xx/boards/imxrt1015_evk/board.cmake new file mode 100644 index 000000000..7aabfec8c --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1015_evk/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT MIMXRT1015) + +set(JLINK_DEVICE MIMXRT1015DAF5A) +set(PYOCD_TARGET mimxrt1015) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1015DAF5A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/board.h b/ports/mimxrt10xx/boards/imxrt1015_evk/board.h index a3d58fc23..8eeff8bb9 100644 --- a/ports/mimxrt10xx/boards/imxrt1015_evk/board.h +++ b/ports/mimxrt10xx/boards/imxrt1015_evk/board.h @@ -1,100 +1,64 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Ha Thach for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// Size of on-board external flash -#define BOARD_FLASH_SIZE (16*1024*1024) - -//--------------------------------------------------------------------+ -// LED -//--------------------------------------------------------------------+ - -// GPIO_SD_B1_00 -#define LED_PINMUX IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 -#define LED_PORT GPIO3 -#define LED_PIN 20 -#define LED_STATE_ON 0 - -#if 0 -// PWM Test on Arduino header D8 -#define LED_PWM_PINMUX IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A -#define LED_PWM_BASE PWM1 -#define LED_PWM_MODULE kPWM_Module_0 -#define LED_PWM_CHANNEL kPWM_PwmA -#endif - -//--------------------------------------------------------------------+ -// Neopixel -//--------------------------------------------------------------------+ - -// Number of neopixels -#if 1 -#define NEOPIXEL_NUMBER 0 - -#else -// Neopixel Test on Arduino header A0 -#define NEOPIXEL_NUMBER 1 -#define NEOPIXEL_PINMUX IOMUXC_GPIO_AD_07_GPIOMUX_IO21 -#define NEOPIXEL_PORT GPIO1 -#define NEOPIXEL_PIN 21 -#endif - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// SW8 button -#define BUTTON_PINMUX IOMUXC_GPIO_EMC_09_GPIO2_IO09 -#define BUTTON_PORT GPIO2 -#define BUTTON_PIN 9 -#define BUTTON_STATE_ACTIVE 0 - -//--------------------------------------------------------------------+ -// USB UF2 -//--------------------------------------------------------------------+ - -#define USB_VID 0x239A -#define USB_PID 0x0137 -#define USB_MANUFACTURER "NXP" -#define USB_PRODUCT "RT1015 EVK" - -#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT -#define UF2_BOARD_ID "MIMXRT1015-EVK-revA" -#define UF2_VOLUME_LABEL "RT1015BOOT" -#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1015-EVK#/" - -//--------------------------------------------------------------------+ -// UART -//--------------------------------------------------------------------+ - -#define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_07_LPUART1_RX -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_06_LPUART1_TX - -#endif /* BOARD_H_ */ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Ha Thach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Size of on-board external flash +#define BOARD_FLASH_SIZE (16*1024*1024) + +//--------------------------------------------------------------------+ +// LED +//--------------------------------------------------------------------+ +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL +#define LED_STATE_ON 0 + +//--------------------------------------------------------------------+ +// Neopixel +//--------------------------------------------------------------------+ +#define NEOPIXEL_NUMBER 0 // Number of neopixels + +//--------------------------------------------------------------------+ +// USB UF2 +//--------------------------------------------------------------------+ +#define USB_VID 0x239A +#define USB_PID 0x0137 +#define USB_MANUFACTURER "NXP" +#define USB_PRODUCT "RT1015 EVK" + +#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT +#define UF2_BOARD_ID "MIMXRT1015-EVK-revA" +#define UF2_VOLUME_LABEL "RT1015BOOT" +#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1015-EVK#/" + +//--------------------------------------------------------------------+ +// UART +//--------------------------------------------------------------------+ +#define UART_DEV LPUART1 + +#endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/clock_config.c b/ports/mimxrt10xx/boards/imxrt1015_evk/board/clock_config.c similarity index 98% rename from ports/mimxrt10xx/boards/imxrt1015_evk/clock_config.c rename to ports/mimxrt10xx/boards/imxrt1015_evk/board/clock_config.c index c6f849e32..4689211d7 100644 --- a/ports/mimxrt10xx/boards/imxrt1015_evk/clock_config.c +++ b/ports/mimxrt10xx/boards/imxrt1015_evk/board/clock_config.c @@ -1,10 +1,3 @@ -/* - * Copyright 2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* * How to setup clock using clock driver functions: * @@ -22,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v10.0 +product: Clocks v18.0 processor: MIMXRT1015xxxxx package_id: MIMXRT1015DAF5A mcu_data: ksdk2_0 -processor_version: 0.12.10 +processor_version: 25.09.10 board: MIMXRT1015-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -84,6 +77,7 @@ called_from_default_init: true - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} settings: - {id: CCM.AHB_PODF.scale, value: '1', locked: true} - {id: CCM.ARM_PODF.scale, value: '1', locked: true} @@ -119,6 +113,8 @@ called_from_default_init: true - {id: CCM_ANALOG.PLL4.denom, value: '50'} - {id: CCM_ANALOG.PLL4.div, value: '47'} - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} sources: - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} @@ -306,8 +302,6 @@ void BOARD_BootClockRUN(void) CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); /* Init Usb1 pfd3. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/clock_config.h b/ports/mimxrt10xx/boards/imxrt1015_evk/board/clock_config.h similarity index 57% rename from ports/mimxrt10xx/boards/imxrt1015_evk/clock_config.h rename to ports/mimxrt10xx/boards/imxrt1015_evk/board/clock_config.h index 20985c2b5..cccbe487a 100644 --- a/ports/mimxrt10xx/boards/imxrt1015_evk/clock_config.h +++ b/ports/mimxrt10xx/boards/imxrt1015_evk/board/clock_config.h @@ -1,10 +1,3 @@ -/* - * Copyright 2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - #ifndef _CLOCK_CONFIG_H_ #define _CLOCK_CONFIG_H_ @@ -43,39 +36,39 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AOI, ARM, BEE, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, NVIC, OCOTP, PWM1, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TRNG, USB, WDOG1, WDOG2, XBARA, XBARB */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */ /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. */ diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/board/pin_mux.c b/ports/mimxrt10xx/boards/imxrt1015_evk/board/pin_mux.c new file mode 100644 index 000000000..f0facc74a --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1015_evk/board/pin_mux.c @@ -0,0 +1,136 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1015xxxxx +package_id: MIMXRT1015DAF5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1015-EVK +external_user_signals: {} +pin_labels: +- {pin_num: '21', pin_signal: GPIO_SD_B1_01, label: GPIO SD_B1_01, identifier: USER_LED} +power_domains: {NVCC_GPIO: '3.3'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '1', peripheral: GPIO2, signal: 'gpio_io, 09', pin_signal: GPIO_EMC_09, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm} + - {pin_num: '21', peripheral: GPIO3, signal: 'gpio_io, 21', pin_signal: GPIO_SD_B1_01, direction: OUTPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of USER_BUTTON on GPIO_EMC_09 (pin 1) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_EMC_09 (pin 1) */ + GPIO_PinInit(GPIO2, 9U, &USER_BUTTON_config); + + /* GPIO configuration of USER_LED on GPIO_SD_B1_01 (pin 21) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_SD_B1_01 (pin 21) */ + GPIO_PinInit(GPIO3, 21U, &USER_LED_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_GPIO3_IO21, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0x70B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '12', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: '11', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: '9', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10} + - {pin_num: '10', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09} + - {pin_num: '13', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06} + - {pin_num: '8', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, slew_rate: Slow} + - {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/board/pin_mux.h b/ports/mimxrt10xx/boards/imxrt1015_evk/board/pin_mux.h new file mode 100644 index 000000000..2f3bf2c4c --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1015_evk/board/pin_mux.h @@ -0,0 +1,141 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_EMC_09 (number 1), USER_BUTTON/SW4 */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 9U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 9U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 9U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 9U) /*!< PORT pin mask */ + +/* GPIO_SD_B1_01 (number 21), GPIO SD_B1_01 */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO3 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 21U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO3 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 21U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 21U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO3 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 21U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 21U) /*!< PORT pin mask */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_SD_B1_07 (number 12), FlexSPI_CLK_A/U13[6] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_08 (number 11), FlexSPI_D0_A/U13[5] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_10 (number 9), FlexSPI_D1_A/U13[2] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_09 (number 10), FlexSPI_D2_A/U13[3] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_06 (number 13), FlexSPI_D3_A/U13[7] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_11 (number 8), FlexSPI_SS0/U13[1] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1015_evk/flash_config.c index 369760bbf..ec8a16ef0 100644 --- a/ports/mimxrt10xx/boards/imxrt1015_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1015_evk/flash_config.c @@ -9,162 +9,114 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for AT25SF128A with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x02, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 4u, + .seqNum = 1u, }, + .deviceModeArg = 0x02, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1015_evk/mimxrt1015_evk.mex b/ports/mimxrt10xx/boards/imxrt1015_evk/mimxrt1015_evk.mex new file mode 100644 index 000000000..a39bb8107 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1015_evk/mimxrt1015_evk.mex @@ -0,0 +1,474 @@ + + + + MIMXRT1015xxxxx + MIMXRT1015DAF5A + MIMXRT1015-EVK + B + ksdk2_0 + + + + + + + true + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + N/A + + + + + + + 13.0.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + N/A + + + + diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/board.cmake b/ports/mimxrt10xx/boards/imxrt1020_evk/board.cmake new file mode 100644 index 000000000..c0c235be2 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT MIMXRT1021) + +set(JLINK_DEVICE MIMXRT1021DAG5A) +set(PYOCD_TARGET mimxrt1020) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1021DAG5A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/board.h b/ports/mimxrt10xx/boards/imxrt1020_evk/board.h index 2b66d5086..7babf39c6 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/board.h +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board.h @@ -1,82 +1,64 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Ha Thach for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// Size of on-board external flash -#define BOARD_FLASH_SIZE (8*1024*1024) - -//--------------------------------------------------------------------+ -// LED -//--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 -#define LED_PORT GPIO1 -#define LED_PIN 5 -#define LED_STATE_ON 0 - -//--------------------------------------------------------------------+ -// Neopixel -//--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 0 - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// SW8 button -#define BUTTON_PINMUX IOMUXC_SNVS_WAKEUP_GPIO5_IO00 -#define BUTTON_PORT GPIO5 -#define BUTTON_PIN 0 -#define BUTTON_STATE_ACTIVE 0 - -//--------------------------------------------------------------------+ -// USB UF2 -//--------------------------------------------------------------------+ - -#define USB_VID 0x239A -#define USB_PID 0x0081 -#define USB_MANUFACTURER "NXP" -#define USB_PRODUCT "RT1020 EVK" - -#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT -#define UF2_BOARD_ID "MIMXRT1020-EVK-revA" -#define UF2_VOLUME_LABEL "RT1020BOOT" -#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1020-EVK#/" - -//--------------------------------------------------------------------+ -// UART -//--------------------------------------------------------------------+ - -#define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_07_LPUART1_RX -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_06_LPUART1_TX - -#endif /* BOARD_H_ */ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Ha Thach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Size of on-board external flash +#define BOARD_FLASH_SIZE (8*1024*1024) + +//--------------------------------------------------------------------+ +// LED +//--------------------------------------------------------------------+ +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL +#define LED_STATE_ON 0 + +//--------------------------------------------------------------------+ +// Neopixel +//--------------------------------------------------------------------+ +#define NEOPIXEL_NUMBER 0 // Number of neopixels + +//--------------------------------------------------------------------+ +// USB UF2 +//--------------------------------------------------------------------+ +#define USB_VID 0x239A +#define USB_PID 0x0081 +#define USB_MANUFACTURER "NXP" +#define USB_PRODUCT "RT1020 EVK" + +#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT +#define UF2_BOARD_ID "MIMXRT1020-EVK-revA" +#define UF2_VOLUME_LABEL "RT1020BOOT" +#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1020-EVK#/" + +//--------------------------------------------------------------------+ +// UART +//--------------------------------------------------------------------+ +#define UART_DEV LPUART1 + +#endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/clock_config.c b/ports/mimxrt10xx/boards/imxrt1020_evk/board/clock_config.c similarity index 67% rename from ports/mimxrt10xx/boards/imxrt1020_evk/clock_config.c rename to ports/mimxrt10xx/boards/imxrt1020_evk/board/clock_config.c index 68cd97f6a..b63df4773 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/clock_config.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board/clock_config.c @@ -1,10 +1,3 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* * How to setup clock using clock driver functions: * @@ -22,10 +15,12 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v7.0 +product: Clocks v18.0 processor: MIMXRT1021xxxxx +package_id: MIMXRT1021DAG5A mcu_data: ksdk2_0 -processor_version: 0.10.4 +processor_version: 25.09.10 +board: MIMXRT1020-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" @@ -38,8 +33,6 @@ processor_version: 0.10.4 /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ @@ -57,38 +50,82 @@ void BOARD_InitBootClocks(void) name: BOARD_BootClockRUN called_from_default_init: true outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 24 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} +- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: ENET_500M_REF_CLK.outFreq, value: 24 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 4 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 24 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz} -- {id: MQS_MCLK.outFreq, value: 3 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI1_MCLK1.outFreq, value: 3 MHz} -- {id: SAI1_MCLK2.outFreq, value: 3 MHz} -- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI2_MCLK1.outFreq, value: 3 MHz} -- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz} -- {id: SAI3_MCLK1.outFreq, value: 3 MHz} -- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 8 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 4 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK} +- {id: CCM.IPG_PODF.scale, value: '4'} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true} +- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled} +- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* @@ -97,16 +134,21 @@ called_from_default_init: true const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 1, /* 30 bit numerator of fractional loop divider */ - .denominator = 60000, /* 30 bit denominator of fractional loop divider */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { - .enableClkOutput = true, /* Enable the PLL providing the ENET 125MHz reference clock */ + .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .enableClkOutput25M = true, /* Enable the PLL providing the ENET 25MHz reference clock */ - .loopDivider = 1, /* Set frequency of ethernet reference clock to 2.4 MHz */ + .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ + .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; /******************************************************************************* @@ -114,6 +156,8 @@ const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = ******************************************************************************/ void BOARD_BootClockRUN(void) { + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); /* Enable 1MHz clock output. */ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; /* Use free 1MHz clock output. */ @@ -131,6 +175,12 @@ void BOARD_BootClockRUN(void) /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Disable IPG clock gate. */ @@ -139,7 +189,7 @@ void BOARD_BootClockRUN(void) CLOCK_DisableClock(kCLOCK_Xbar1); CLOCK_DisableClock(kCLOCK_Xbar2); /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 0); + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); /* Set ARM_PODF. */ CLOCK_SetDiv(kCLOCK_ArmDiv, 0); /* Set PERIPH_CLK2_PODF. */ @@ -151,17 +201,17 @@ void BOARD_BootClockRUN(void) CLOCK_DisableClock(kCLOCK_Gpt2S); CLOCK_DisableClock(kCLOCK_Pit); /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 0); + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); /* Disable USDHC1 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc1); /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2); /* Set Usdhc1 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); /* Disable USDHC2 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc2); /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2); /* Set Usdhc2 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. @@ -171,7 +221,7 @@ void BOARD_BootClockRUN(void) /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 2); + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); /* Set Semc alt clock source. */ CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ @@ -184,9 +234,9 @@ void BOARD_BootClockRUN(void) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); + CLOCK_SetMux(kCLOCK_FlexspiMux, 2); #endif /* Disable LPSPI clock gate. */ CLOCK_DisableClock(kCLOCK_Lpspi1); @@ -194,7 +244,7 @@ void BOARD_BootClockRUN(void) CLOCK_DisableClock(kCLOCK_Lpspi3); CLOCK_DisableClock(kCLOCK_Lpspi4); /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 3); + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); /* Set Lpspi clock source. */ CLOCK_SetMux(kCLOCK_LpspiMux, 2); /* Disable TRACE clock gate. */ @@ -202,7 +252,7 @@ void BOARD_BootClockRUN(void) /* Set TRACE_PODF. */ CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -289,22 +339,24 @@ void BOARD_BootClockRUN(void) /* Init System pfd1. */ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); - /* Bypass System PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1); + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* DeInit Usb1 PLL. */ - CLOCK_DeinitUsb1Pll(); - /* Bypass Usb1 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1); - /* Enable Usb1 PLL output. */ - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK; + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); @@ -317,10 +369,8 @@ void BOARD_BootClockRUN(void) CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; /* Init Enet PLL. */ CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 2); + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ CLOCK_SetMux(kCLOCK_PeriphMux, 0); /* Set periph clock2 clock source. */ @@ -354,7 +404,14 @@ void BOARD_BootClockRUN(void) /* Set MQS configuration. */ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/board/clock_config.h b/ports/mimxrt10xx/boards/imxrt1020_evk/board/clock_config.h new file mode 100644 index 000000000..d7dc8b84e --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board/clock_config.h @@ -0,0 +1,108 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENET, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PWM1, PWM2, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TRNG, USB, USDHC1, USDHC2, WDOG1, WDOG2, XBARA, XBARB */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/board/pin_mux.c b/ports/mimxrt10xx/boards/imxrt1020_evk/board/pin_mux.c new file mode 100644 index 000000000..01ef27748 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board/pin_mux.c @@ -0,0 +1,136 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1021xxxxx +package_id: MIMXRT1021DAG5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1020-EVK +external_user_signals: {} +pin_labels: +- {pin_num: '52', pin_signal: WAKEUP, label: USER_BUTTON, identifier: USER_BUTTON} +- {pin_num: '106', pin_signal: GPIO_AD_B0_05, label: 'JTAG_nTRST/J16[3]/USER_LED/J17[5]', identifier: USER_LED} +power_domains: {NVCC_GPIO: '3.3'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '52', peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT} + - {pin_num: '106', peripheral: GPIO1, signal: 'gpio_io, 05', pin_signal: GPIO_AD_B0_05, direction: OUTPUT, pull_keeper_select: Keeper} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + + /* GPIO configuration of USER_LED on GPIO_AD_B0_05 (pin 106) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_05 (pin 106) */ + GPIO_PinInit(GPIO1, 5U, &USER_LED_config); + + /* GPIO configuration of USER_BUTTON on WAKEUP (pin 52) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on WAKEUP (pin 52) */ + GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0U); + IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0x50A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07} + - {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '24', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: '23', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: '21', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10} + - {pin_num: '22', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09} + - {pin_num: '25', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06} + - {pin_num: '19', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/board/pin_mux.h b/ports/mimxrt10xx/boards/imxrt1020_evk/board/pin_mux.h new file mode 100644 index 000000000..00ffe7316 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/board/pin_mux.h @@ -0,0 +1,141 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* WAKEUP (number 52), USER_BUTTON */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */ + +/* GPIO_AD_B0_05 (number 106), JTAG_nTRST/J16[3]/USER_LED/J17[5] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 5U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 5U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 5U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 5U) /*!< PORT pin mask */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_07 (number 101), UART1_RXD/J17[4] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/* GPIO_AD_B0_06 (number 105), UART1_TXD/J17[6] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_B1_07 (number 24), FlexSPI_CLK/U13[6] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_08 (number 23), FlexSPI_D0_A/U13[5] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_10 (number 21), FlexSPI_D1_A/U13[2] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_09 (number 22), FlexSPI_D2_A/U13[3] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_06 (number 25), FlexSPI_D3_A/U13[7] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_11 (number 19), FlexSPI_SS0/U13[1] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/clock_config.h b/ports/mimxrt10xx/boards/imxrt1020_evk/clock_config.h deleted file mode 100644 index 8f136bbcb..000000000 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/clock_config.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 2000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 0UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 3000000UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 1500000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 1500000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 3000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 1500000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 8000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 1500000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 6000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 4000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 12000000UL - -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c index 8083a6979..6e8d97a9a 100644 --- a/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c @@ -9,162 +9,114 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for IS25LP064A with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */ ), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 4u, + .seqNum = 1u, }, + .deviceModeArg = 0x40, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1020_evk/mimxrt1020_evk.mex b/ports/mimxrt10xx/boards/imxrt1020_evk/mimxrt1020_evk.mex new file mode 100644 index 000000000..6f2a30d5e --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1020_evk/mimxrt1020_evk.mex @@ -0,0 +1,459 @@ + + + + MIMXRT1021xxxxx + MIMXRT1021DAG5A + MIMXRT1020-EVK + A3 + ksdk2_0 + + + + + + + false + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 25.09.10 + c_array + + + + + + + + + + + + + 25.09.10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + + + + diff --git a/ports/mimxrt10xx/boards/imxrt1024_evk/board.cmake b/ports/mimxrt10xx/boards/imxrt1024_evk/board.cmake new file mode 100644 index 000000000..f19ee5d86 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1024_evk/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT MIMXRT1024) + +set(JLINK_DEVICE MIMXRT1024DAG5A) +set(PYOCD_TARGET mimxrt1024) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1024DAG5A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/imxrt1024_evk/board.h b/ports/mimxrt10xx/boards/imxrt1024_evk/board.h index 1cf320f15..8389cd8cb 100644 --- a/ports/mimxrt10xx/boards/imxrt1024_evk/board.h +++ b/ports/mimxrt10xx/boards/imxrt1024_evk/board.h @@ -1,82 +1,64 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Ha Thach for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// Size of on-board external flash -#define BOARD_FLASH_SIZE (4*1024*1024) - -//--------------------------------------------------------------------+ -// LED -//--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 -#define LED_PORT GPIO1 -#define LED_PIN 24 -#define LED_STATE_ON 1 - -//--------------------------------------------------------------------+ -// Neopixel -//--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 0 - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// SW8 button -#define BUTTON_PINMUX IOMUXC_SNVS_WAKEUP_GPIO5_IO00 -#define BUTTON_PORT GPIO5 -#define BUTTON_PIN 0 -#define BUTTON_STATE_ACTIVE 0 - -//--------------------------------------------------------------------+ -// USB UF2 -//--------------------------------------------------------------------+ - -#define USB_VID 0x239A -#define USB_PID 0x0081 -#define USB_MANUFACTURER "NXP" -#define USB_PRODUCT "RT1024 EVK" - -#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT -#define UF2_BOARD_ID "MIMXRT1024-EVK-revA" -#define UF2_VOLUME_LABEL "RT1024BOOT" -#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1024-EVK#/" - -//--------------------------------------------------------------------+ -// UART -//--------------------------------------------------------------------+ - -#define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_07_LPUART1_RX -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_06_LPUART1_TX - -#endif /* BOARD_H_ */ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Ha Thach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Size of on-board external flash +#define BOARD_FLASH_SIZE (4*1024*1024) + +//--------------------------------------------------------------------+ +// LED +//--------------------------------------------------------------------+ +#define LED_PORT BOARD_INITPINS_USER_LED_PORT +#define LED_PIN BOARD_INITPINS_USER_LED_PIN +#define LED_STATE_ON 1 + +//--------------------------------------------------------------------+ +// Neopixel +//--------------------------------------------------------------------+ +#define NEOPIXEL_NUMBER 0 // Number of neopixels + +//--------------------------------------------------------------------+ +// USB UF2 +//--------------------------------------------------------------------+ +#define USB_VID 0x239A +#define USB_PID 0x0081 +#define USB_MANUFACTURER "NXP" +#define USB_PRODUCT "RT1024 EVK" + +#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT +#define UF2_BOARD_ID "MIMXRT1024-EVK-revA" +#define UF2_VOLUME_LABEL "RT1024BOOT" +#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1024-EVK#/" + +//--------------------------------------------------------------------+ +// UART +//--------------------------------------------------------------------+ +#define UART_DEV LPUART1 + +#endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1024_evk/clock_config.c b/ports/mimxrt10xx/boards/imxrt1024_evk/board/clock_config.c similarity index 82% rename from ports/mimxrt10xx/boards/imxrt1024_evk/clock_config.c rename to ports/mimxrt10xx/boards/imxrt1024_evk/board/clock_config.c index 337624657..46c4b1e42 100644 --- a/ports/mimxrt10xx/boards/imxrt1024_evk/clock_config.c +++ b/ports/mimxrt10xx/boards/imxrt1024_evk/board/clock_config.c @@ -1,10 +1,3 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* * How to setup clock using clock driver functions: * @@ -22,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v5.0 +product: Clocks v18.0 processor: MIMXRT1024xxxxx package_id: MIMXRT1024DAG5A mcu_data: ksdk2_0 -processor_version: 0.0.0 +processor_version: 25.09.10 board: MIMXRT1024-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -40,8 +33,6 @@ board: MIMXRT1024-EVK /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ @@ -86,8 +77,9 @@ called_from_default_init: true - {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} - {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz} settings: @@ -100,7 +92,8 @@ called_from_default_init: true - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF} - {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} - {id: CCM.USDHC1_PODF.scale, value: '3', locked: true} - {id: CCM.USDHC2_PODF.scale, value: '3', locked: true} - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} @@ -128,32 +121,36 @@ called_from_default_init: true - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} - {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled} - {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { - .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ - .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ - .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ + .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -178,7 +175,7 @@ void BOARD_BootClockRUN(void) /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */ + /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); /* Waiting for DCDC_STS_DC_OK bit is asserted */ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) @@ -218,9 +215,8 @@ void BOARD_BootClockRUN(void) /* Set Usdhc2 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); @@ -232,9 +228,8 @@ void BOARD_BootClockRUN(void) CLOCK_SetMux(kCLOCK_SemcMux, 0); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); @@ -255,9 +250,9 @@ void BOARD_BootClockRUN(void) /* Disable TRACE clock gate. */ CLOCK_DisableClock(kCLOCK_Trace); /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -331,10 +326,12 @@ void BOARD_BootClockRUN(void) /* Set Pll3 sw clock source. */ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ @@ -347,9 +344,8 @@ void BOARD_BootClockRUN(void) CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Init Usb1 PLL. */ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); @@ -361,8 +357,6 @@ void BOARD_BootClockRUN(void) CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); /* Init Usb1 pfd3. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); @@ -408,9 +402,16 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/boards/imxrt1024_evk/board/clock_config.h b/ports/mimxrt10xx/boards/imxrt1024_evk/board/clock_config.h new file mode 100644 index 000000000..d7dc8b84e --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1024_evk/board/clock_config.h @@ -0,0 +1,108 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENET, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PWM1, PWM2, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TRNG, USB, USDHC1, USDHC2, WDOG1, WDOG2, XBARA, XBARB */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1024_evk/board/pin_mux.c b/ports/mimxrt10xx/boards/imxrt1024_evk/board/pin_mux.c new file mode 100644 index 000000000..e47b05c5c --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1024_evk/board/pin_mux.c @@ -0,0 +1,162 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1024xxxxx +package_id: MIMXRT1024DAG5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1024-EVK +pin_labels: +- {pin_num: '52', pin_signal: WAKEUP, label: USER_BUTTON, identifier: USER_BUTTON} +- {pin_num: '82', pin_signal: GPIO_AD_B1_08, label: 'UART_TX/USER_LED/J17[4]', identifier: USER_LED} +power_domains: {NVCC_GPIO: '3.3'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); + +/* GPIO_AD_B1_00~GPIO_AD_B1_05 can only be configured as flexspi function. Note that it can't be modified here */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03,1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK,1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00,1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02,1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01,1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B,1U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '52', peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT} + - {pin_num: '82', peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08, direction: OUTPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); /* iomuxc_snvs clock (iomuxc_snvs_clk_enable): 0x03U */ + + /* GPIO configuration of USER_LED on GPIO_AD_B1_08 (pin 82) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B1_08 (pin 82) */ + GPIO_PinInit(GPIO1, 24U, &USER_LED_config); + + /* GPIO configuration of USER_BUTTON on WAKEUP (pin 52) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on WAKEUP (pin 52) */ + GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, /* GPIO_AD_B1_08 is configured as GPIO1_IO24 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_SNVS_WAKEUP_GPIO5_IO00, /* WAKEUP is configured as GPIO5_IO00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07} + - {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_06_LPUART1_TX, /* GPIO_AD_B0_06 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_07_LPUART1_RX, /* GPIO_AD_B0_07 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '24', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: '23', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: '21', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10} + - {pin_num: '22', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09} + - {pin_num: '25', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06} + - {pin_num: '19', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, /* GPIO_SD_B1_06 is configured as FLEXSPI_A_DATA03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, /* GPIO_SD_B1_07 is configured as FLEXSPI_A_SCLK */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, /* GPIO_SD_B1_08 is configured as FLEXSPI_A_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, /* GPIO_SD_B1_09 is configured as FLEXSPI_A_DATA02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, /* GPIO_SD_B1_10 is configured as FLEXSPI_A_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, /* GPIO_SD_B1_11 is configured as FLEXSPI_A_SS0_B */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1024_evk/board/pin_mux.h b/ports/mimxrt10xx/boards/imxrt1024_evk/board/pin_mux.h new file mode 100644 index 000000000..4f5ee61a3 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1024_evk/board/pin_mux.h @@ -0,0 +1,123 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/* Define the flexspi macro. Note that it can't be modified here */ +#define IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03 0x401F80FCU, 0x1U, 0x401F8374U, 0x1U, 0x401F8270U +#define IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK 0x401F8100U, 0x1U, 0x401F8378U, 0x1U, 0x401F8274U +#define IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00 0x401F8104U, 0x1U, 0x401F8368U, 0x1U, 0x401F8278U +#define IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02 0x401F8108U, 0x1U, 0x401F8370U, 0x1U, 0x401F827CU +#define IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01 0x401F810CU, 0x1U, 0x401F836CU, 0x1U, 0x401F8280U +#define IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B 0x401F8110U, 0x1U, 0, 0, 0x401F8284U + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* WAKEUP (number 52), USER_BUTTON */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO device name: GPIO5 */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT device name: GPIO5 */ +#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< GPIO5 pin index: 0 */ + +/* GPIO_AD_B1_08 (number 82), UART_TX/USER_LED/J17[4] */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO device name: GPIO1 */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT device name: GPIO1 */ +#define BOARD_INITPINS_USER_LED_PIN 24U /*!< GPIO1 pin index: 24 */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_07 (number 101), UART1_RXD/J17[8] */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */ + +/* GPIO_AD_B0_06 (number 105), UART1_TXD/J17[12] */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_B1_07 (number 24), SAI3_TX_SYNC */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< FLEXSPI signal: FLEXSPI_A_SCLK */ + +/* GPIO_SD_B1_08 (number 23), SAI3_TXD */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< FLEXSPI signal: FLEXSPI_A_DATA0 */ + +/* GPIO_SD_B1_10 (number 21), SD_PWREN */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< FLEXSPI signal: FLEXSPI_A_DATA1 */ + +/* GPIO_SD_B1_09 (number 22), AUD_INT */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< FLEXSPI signal: FLEXSPI_A_DATA2 */ + +/* GPIO_SD_B1_06 (number 25), SAI3_TX_BCLK */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< FLEXSPI signal: FLEXSPI_A_DATA3 */ + +/* GPIO_SD_B1_11 (number 19), SAI3_RXD */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< FLEXSPI signal: FLEXSPI_A_SS0_B */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1024_evk/clock_config.h b/ports/mimxrt10xx/boards/imxrt1024_evk/clock_config.h deleted file mode 100644 index 538151b6a..000000000 --- a/ports/mimxrt10xx/boards/imxrt1024_evk/clock_config.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL - -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1024_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1024_evk/flash_config.c index 09f2aaf8d..b029d7b4a 100644 --- a/ports/mimxrt10xx/boards/imxrt1024_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1024_evk/flash_config.c @@ -9,172 +9,122 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for on-chip W25Q32JV with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = + { + .seqId = 4u, .seqNum = 1u, }, - .deviceModeArg = 0x0200, - .configCmdEnable = 1u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .configCmdSeqs[0] = { - .seqId = 2u, - .seqNum = 1u, - }, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_60MHz, - .sflashA1Size = BOARD_FLASH_SIZE, - .lookupTable = + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, - DUMMY_SDR, FLEXSPI_1PAD, 8), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 2u, + .seqNum = 1u, }, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = BOARD_FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, DUMMY_SDR, FLEXSPI_1PAD, 8), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1024_evk/mimxrt1024_evk.mex b/ports/mimxrt10xx/boards/imxrt1024_evk/mimxrt1024_evk.mex new file mode 100644 index 000000000..54c770110 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1024_evk/mimxrt1024_evk.mex @@ -0,0 +1,363 @@ + + + + MIMXRT1024xxxxx + MIMXRT1024DAG5A + MIMXRT1024-EVK + B1 + ksdk2_0 + + + + + + + false + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 13.0.2 + c_array + + + + + + + + + + + + + 13.0.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + N/A + + + + + + + diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/board.cmake b/ports/mimxrt10xx/boards/imxrt1040_evk/board.cmake new file mode 100644 index 000000000..f363640c2 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1040_evk/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT MIMXRT1042) + +set(JLINK_DEVICE MIMXRT1042xxx5B) +set(PYOCD_TARGET mimxrt1042) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1042XJM5B + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/board.h b/ports/mimxrt10xx/boards/imxrt1040_evk/board.h index c7610b7f7..18ecf9675 100644 --- a/ports/mimxrt10xx/boards/imxrt1040_evk/board.h +++ b/ports/mimxrt10xx/boards/imxrt1040_evk/board.h @@ -34,18 +34,14 @@ //--------------------------------------------------------------------+ // LED //--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 -#define LED_PORT GPIO1 -#define LED_PIN 8 +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL #define LED_STATE_ON 0 //--------------------------------------------------------------------+ // Neopixel //--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 0 +#define NEOPIXEL_NUMBER 0 // Number of neopixels //--------------------------------------------------------------------+ // Button @@ -55,7 +51,6 @@ //--------------------------------------------------------------------+ // USB UF2 //--------------------------------------------------------------------+ - #define USB_VID 0x239A #define USB_PID 0x0135 #define USB_MANUFACTURER "NXP" @@ -69,9 +64,6 @@ //--------------------------------------------------------------------+ // UART //--------------------------------------------------------------------+ - #define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_13_LPUART1_RX -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_12_LPUART1_TX #endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/teensy40/clock_config.c b/ports/mimxrt10xx/boards/imxrt1040_evk/board/clock_config.c similarity index 77% rename from ports/mimxrt10xx/boards/teensy40/clock_config.c rename to ports/mimxrt10xx/boards/imxrt1040_evk/board/clock_config.c index 38f0b8f99..f3d8c7901 100644 --- a/ports/mimxrt10xx/boards/teensy40/clock_config.c +++ b/ports/mimxrt10xx/boards/imxrt1040_evk/board/clock_config.c @@ -1,5 +1,5 @@ /* - * Copyright 2018-2019 NXP + * Copyright 2025 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,12 +22,12 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v5.0 -processor: MIMXRT1062xxxxA -package_id: MIMXRT1062DVL6A +product: Clocks v18.0 +processor: MIMXRT1042xxxxB +package_id: MIMXRT1042XJM5B mcu_data: ksdk2_0 -processor_version: 0.0.0 -board: MIMXRT1060-EVK +processor_version: 25.09.10 +board: MIMXRT1040-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" @@ -40,8 +40,6 @@ board: MIMXRT1060-EVK /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ @@ -64,10 +62,6 @@ called_from_default_init: true - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} -- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} -- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} @@ -77,13 +71,12 @@ called_from_default_init: true - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} - {id: MQS_MCLK.outFreq, value: 1080/17 MHz} - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} @@ -96,7 +89,7 @@ called_from_default_init: true - {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} @@ -109,8 +102,11 @@ called_from_default_init: true - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8', locked: true} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM.USDHC1_PODF.scale, value: '2', locked: true} +- {id: CCM.USDHC2_PODF.scale, value: '2', locked: true} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} @@ -128,35 +124,47 @@ called_from_default_init: true - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL4.denom, value: '50'} -- {id: CCM_ANALOG.PLL4.div, value: '47'} - {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} - {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -222,9 +230,8 @@ void BOARD_BootClockRUN(void) /* Set Usdhc2 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); @@ -236,9 +243,8 @@ void BOARD_BootClockRUN(void) CLOCK_SetMux(kCLOCK_SemcMux, 0); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); @@ -253,17 +259,10 @@ void BOARD_BootClockRUN(void) CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); /* Set Flexspi2 clock source. */ CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); /* Disable LPSPI clock gate. */ CLOCK_DisableClock(kCLOCK_Lpspi1); CLOCK_DisableClock(kCLOCK_Lpspi2); CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); /* Set LPSPI_PODF. */ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); /* Set Lpspi clock source. */ @@ -271,9 +270,9 @@ void BOARD_BootClockRUN(void) /* Disable TRACE clock gate. */ CLOCK_DisableClock(kCLOCK_Trace); /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -367,10 +366,12 @@ void BOARD_BootClockRUN(void) /* Init ARM PLL. */ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ @@ -383,9 +384,8 @@ void BOARD_BootClockRUN(void) CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Init Usb1 PLL. */ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); @@ -409,36 +409,35 @@ void BOARD_BootClockRUN(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); /* DeInit Enet PLL. */ CLOCK_DeinitEnetPll(); /* Bypass Enet PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); /* Enable Enet output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Set Enet2 output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); - /* Enable Enet2 output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; /* Enable Enet25M output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; /* Set preperiph clock source. */ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ @@ -448,8 +447,7 @@ void BOARD_BootClockRUN(void) /* Set per clock source. */ CLOCK_SetMux(kCLOCK_PerclkMux, 0); /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = - (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); /* Set clock out1 divider. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); /* Set clock out1 source. */ @@ -475,15 +473,10 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET1 Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); - /* Set ENET2 Tx clock source. */ -#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); -#else - IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); -#endif + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/board/clock_config.h b/ports/mimxrt10xx/boards/imxrt1040_evk/board/clock_config.h new file mode 100644 index 000000000..77f56c399 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1040_evk/board/clock_config.h @@ -0,0 +1,121 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, USB, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3 */ +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/board/pin_mux.c b/ports/mimxrt10xx/boards/imxrt1040_evk/board/pin_mux.c new file mode 100644 index 000000000..a9bc5e3b2 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1040_evk/board/pin_mux.c @@ -0,0 +1,137 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1042xxxxB +package_id: MIMXRT1042XJM5B +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1040-EVK +pin_labels: +- {pin_num: G11, pin_signal: GPIO_AD_B0_08, label: 'JTAG_MOD/BT_PCM_RXD/U10[18]/USER_LED', identifier: USER_LED} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: G11, peripheral: GPIO1, signal: 'gpio_io, 08', pin_signal: GPIO_AD_B0_08, direction: OUTPUT, gpio_init_state: 'true'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of USER_LED on GPIO_AD_B0_08 (pin G11) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_08 (pin G11) */ + GPIO_PinInit(GPIO1, 8U, &USER_LED_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_GPIO1_IO08, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) + ); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: J12, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: J11, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: M4, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05} + - {pin_num: M5, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} + - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: K6, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} + - {pin_num: N5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} + - {pin_num: N6, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/board/pin_mux.h b/ports/mimxrt10xx/boards/imxrt1040_evk/board/pin_mux.h new file mode 100644 index 000000000..f7636ed0c --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1040_evk/board/pin_mux.h @@ -0,0 +1,138 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x0100U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */ + +/* GPIO_AD_B0_08 (coord G11), JTAG_MOD/BT_PCM_RXD/U10[18]/USER_LED */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 8U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 1U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 8U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 8U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 8U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 8U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_12 (coord J12), UART1_TXD/J13[2] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + +/* GPIO_AD_B0_13 (coord J11), UART1_RXD/J11[2] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_B1_05 (coord M4), FlexSPI_DQS */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */ + +/* GPIO_SD_B1_06 (coord M5), FlexSPI_SS0/U24[1] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK/U24[6] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_08 (coord N4), FlexSPI_D0_A/U24[5] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_09 (coord K6), FlexSPI_D1_A/U24[2] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_10 (coord N5), FlexSPI_D2_A/U24[3] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_11 (coord N6), FlexSPI_D3_A/U24[7] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/clock_config.c b/ports/mimxrt10xx/boards/imxrt1040_evk/clock_config.c deleted file mode 100644 index 027ec7eab..000000000 --- a/ports/mimxrt10xx/boards/imxrt1040_evk/clock_config.c +++ /dev/null @@ -1,912 +0,0 @@ -/* - * Copyright 2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. - * - * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. - * - * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v10.0 -processor: MIMXRT1042xxxxB -package_id: MIMXRT1042XJM5B -mcu_data: ksdk2_0 -processor_version: 0.12.13 -board: MIMXRT1040-EVK - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "clock_config.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 528 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 132 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} -settings: -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} -- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM.SEMC_PODF.scale, value: '8', locked: true} -- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} -- {id: CCM.USDHC1_PODF.scale, value: '2', locked: true} -- {id: CCM.USDHC2_PODF.scale, value: '2', locked: true} -- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} -- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} -- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} -- {id: CCM_ANALOG.PLL5.num, value: '0'} -- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} -- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} -- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} -- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} -sources: -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .postDivider = 8, /* Divider after PLL */ - .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 3); -#endif - /* Disable Flexspi2 clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi2); - /* Set FLEXSPI2_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); - /* Set Flexspi2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Video PLL. */ - uint32_t pllVideo; - /* Disable Video PLL output before initial Video PLL. */ - CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Bypass PLL first */ - CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); - CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); - CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); - pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); - CCM_ANALOG->PLL_VIDEO = pllVideo; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - /* Disable bypass for Video PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 0); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} - -/******************************************************************************* - ******************* Configuration BOARD_BootClockRUN_600M ********************* - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN_600M -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} -settings: -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} -- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.SEMC_PODF.scale, value: '8', locked: true} -- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} -- {id: CCM.USDHC1_PODF.scale, value: '2', locked: true} -- {id: CCM.USDHC2_PODF.scale, value: '2', locked: true} -- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} -- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} -- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} -- {id: CCM_ANALOG.PLL5.num, value: '0'} -- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} -- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} -- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} -- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} -sources: -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN_600M configuration - ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_600M = - { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_600M = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_600M = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_600M = - { - .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .postDivider = 8, /* Divider after PLL */ - .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockRUN_600M configuration - ******************************************************************************/ -void BOARD_BootClockRUN_600M(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 3); -#endif - /* Disable Flexspi2 clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi2); - /* Set FLEXSPI2_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); - /* Set Flexspi2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can3); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - CLOCK_DisableClock(kCLOCK_Can3S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN_600M); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN_600M); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN_600M); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Video PLL. */ - uint32_t pllVideo; - /* Disable Video PLL output before initial Video PLL. */ - CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Bypass PLL first */ - CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); - CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); - CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); - pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); - CCM_ANALOG->PLL_VIDEO = pllVideo; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - /* Disable bypass for Video PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_600M_CORE_CLOCK; -} diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/clock_config.h b/ports/mimxrt10xx/boards/imxrt1040_evk/clock_config.h deleted file mode 100644 index 129818ba1..000000000 --- a/ports/mimxrt10xx/boards/imxrt1040_evk/clock_config.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright 2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 528000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 66000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 66000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 66000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 66000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Video PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************* Configuration BOARD_BootClockRUN_600M ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN_600M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_600M_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_600M_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_600M_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_600M_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_600M_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_600M_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_600M_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_600M_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_600M_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_600M_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_600M_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_600M_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_600M_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_600M_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_600M_FLEXSPI2_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_600M_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_600M_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_600M_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_600M_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_600M_LCDIF_CLK_ROOT 67500000UL -#define BOARD_BOOTCLOCKRUN_600M_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_600M_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_600M_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_600M_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_600M_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_600M_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_600M_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_600M_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_600M_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_600M_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_600M_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_600M_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_600M_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_600M_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_600M_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_600M_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_600M_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_600M_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_600M_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_600M_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_600M_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_600M_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_600M_USBPHY_CLK 0UL -#define BOARD_BOOTCLOCKRUN_600M_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_600M_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN_600M configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_600M; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN_600M configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_600M; -/*! @brief Sys PLL for BOARD_BootClockRUN_600M configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_600M; -/*! @brief Video PLL set for BOARD_BootClockRUN_600M configuration. - */ -extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_600M; - -/******************************************************************************* - * API for BOARD_BootClockRUN_600M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN_600M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1040_evk/flash_config.c index 55175051d..8775ae4df 100644 --- a/ports/mimxrt10xx/boards/imxrt1040_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1040_evk/flash_config.c @@ -9,162 +9,114 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for IS25WP064A with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 4u, + .seqNum = 1u, }, + .deviceModeArg = 0x40, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1040_evk/imxrt1040_evk.mex b/ports/mimxrt10xx/boards/imxrt1040_evk/imxrt1040_evk.mex new file mode 100644 index 000000000..86230f011 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1040_evk/imxrt1040_evk.mex @@ -0,0 +1,522 @@ + + + + MIMXRT1042xxxxB + MIMXRT1042XJM5B + MIMXRT1040-EVK + A + ksdk2_0 + + + + + + + true + false + + /* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + true + + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 25.09.10 + c_array + + + + + + + + + + + + + 25.09.10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + kELCDIF_CurFrameDoneInterruptEnable + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + N/A + + + + diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/board.cmake b/ports/mimxrt10xx/boards/imxrt1050_evkb/board.cmake new file mode 100644 index 000000000..7be9fcc1c --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT MIMXRT1052) + +set(JLINK_DEVICE MIMXRT1052xxxxB) +set(PYOCD_TARGET mimxrt1052) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1052DVL6B + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/board.h b/ports/mimxrt10xx/boards/imxrt1050_evkb/board.h index 562a81518..cdcf11c81 100644 --- a/ports/mimxrt10xx/boards/imxrt1050_evkb/board.h +++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/board.h @@ -1,78 +1,64 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Ha Thach for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// Size of on-board external flash -#define BOARD_FLASH_SIZE (8*1024*1024) - -//--------------------------------------------------------------------+ -// LED -//--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 -#define LED_PORT GPIO1 -#define LED_PIN 9 -#define LED_STATE_ON 0 - -//--------------------------------------------------------------------+ -// Neopixel -//--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 0 - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - - -//--------------------------------------------------------------------+ -// USB UF2 -//--------------------------------------------------------------------+ - -#define USB_VID 0x239A -#define USB_PID 0x0133 -#define USB_MANUFACTURER "NXP" -#define USB_PRODUCT "RT1050 EVK" - -#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT -#define UF2_BOARD_ID "MIMXRT1050-EVKB-revA" -#define UF2_VOLUME_LABEL "RT1050BOOT" -#define UF2_INDEX_URL "https://www.nxp.com/part/IMXRT1050-EVKB#/" - -//--------------------------------------------------------------------+ -// UART -//--------------------------------------------------------------------+ - -#define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_13_LPUART1_RXD -// On Rev A1 of the board this is on J31 closer to the edge. -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_12_LPUART1_TXD - -#endif /* BOARD_H_ */ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Ha Thach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Size of on-board external flash +#define BOARD_FLASH_SIZE (8*1024*1024) + +//--------------------------------------------------------------------+ +// LED +//--------------------------------------------------------------------+ +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL +#define LED_STATE_ON 0 + +//--------------------------------------------------------------------+ +// Neopixel +//--------------------------------------------------------------------+ +#define NEOPIXEL_NUMBER 0 // Number of neopixels + +//--------------------------------------------------------------------+ +// USB UF2 +//--------------------------------------------------------------------+ +#define USB_VID 0x239A +#define USB_PID 0x0133 +#define USB_MANUFACTURER "NXP" +#define USB_PRODUCT "RT1050 EVK" + +#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT +#define UF2_BOARD_ID "MIMXRT1050-EVKB-revA" +#define UF2_VOLUME_LABEL "RT1050BOOT" +#define UF2_INDEX_URL "https://www.nxp.com/part/IMXRT1050-EVKB#/" + +//--------------------------------------------------------------------+ +// UART +//--------------------------------------------------------------------+ +#define UART_DEV LPUART1 + +#endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/board/clock_config.c b/ports/mimxrt10xx/boards/imxrt1050_evkb/board/clock_config.c new file mode 100644 index 000000000..a6b0cc203 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/board/clock_config.c @@ -0,0 +1,495 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: IMXRT1050-EVKB + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 40, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(40); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/board/clock_config.h b/ports/mimxrt10xx/boards/imxrt1050_evkb/board/clock_config.h new file mode 100644 index 000000000..c69d9aa88 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/board/clock_config.h @@ -0,0 +1,119 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, EWM, FLEXIO1, FLEXIO2, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/board/pin_mux.c b/ports/mimxrt10xx/boards/imxrt1050_evkb/board/pin_mux.c new file mode 100644 index 000000000..399397759 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/board/pin_mux.c @@ -0,0 +1,608 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: IMXRT1050-EVKB +pin_labels: +- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED} +- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper} + - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up_100K_Ohm} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + + /* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */ + GPIO_PinInit(GPIO1, 9U, &USER_LED_config); + + /* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on WAKEUP (pin L6) */ + GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U); + IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U); + IOMUXC_SetPinConfig(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0x01B0A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0x10B0U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0x10B0U); +#else + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); +#endif +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSDRAMPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09} + - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10} + - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11} + - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12} + - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13} + - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14} + - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15} + - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16} + - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17} + - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18} + - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23} + - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19} + - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20} + - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21} + - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22} + - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24} + - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27} + - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26} + - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00} + - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01} + - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02} + - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03} + - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04} + - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05} + - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06} + - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07} + - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30} + - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31} + - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32} + - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33} + - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34} + - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35} + - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36} + - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37} + - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08} + - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38} + - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25} + - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28} + - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSDRAMPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitSDRAMPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DA00, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DA01, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DA02, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DA03, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DA04, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DA05, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DA06, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DA07, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U); +#endif + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U); +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DA08, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DA09, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DA10, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DA11, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DA12, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DA13, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DA14, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DA15, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U); +#endif + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U); +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX0, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U); +#endif +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitCSIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08} + - {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09} + - {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10} + - {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11} + - {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12} + - {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13} + - {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15} + - {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14} + - {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04} + - {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05} + - {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06} + - {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07} + - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitCSIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitCSIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLCDPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLCDPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitLCDPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitCANPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14} + - {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitCANPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitCANPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitENETPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40} + - {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41} + - {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10} + - {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04} + - {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05} + - {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06} + - {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11} + - {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07} + - {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08} + - {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitENETPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitENETPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSDHCPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05} + - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04} + - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03} + - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02} + - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00} + - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSDHCPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitUSDHCPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitHyperFlashPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} + - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} + - {pin_num: L5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA3, pin_signal: GPIO_SD_B1_00} + - {pin_num: M5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA2, pin_signal: GPIO_SD_B1_01} + - {pin_num: M3, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA1, pin_signal: GPIO_SD_B1_02} + - {pin_num: M4, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA0, pin_signal: GPIO_SD_B1_03} + - {pin_num: P2, peripheral: FLEXSPI, signal: FLEXSPI_B_SCLK, pin_signal: GPIO_SD_B1_04} + - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} + - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} + - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitHyperFlashPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitHyperFlashPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); +#endif +#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3, 0U); +#else + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); +#endif +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/board/pin_mux.h b/ports/mimxrt10xx/boards/imxrt1050_evkb/board/pin_mux.h new file mode 100644 index 000000000..ff2621509 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/board/pin_mux.h @@ -0,0 +1,762 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 9U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 9U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 9U) /*!< PORT pin mask */ + +/* WAKEUP (coord L6), SD_PWREN */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_EMC_09 (coord C2), SEMC_A0 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_EMC_10 (coord G1), SEMC_A1 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_EMC_11 (coord G3), SEMC_A2 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_EMC_12 (coord H1), SEMC_A3 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_EMC_13 (coord A6), SEMC_A4 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */ + +/* GPIO_EMC_14 (coord B6), SEMC_A5 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */ + +/* GPIO_EMC_15 (coord B1), SEMC_A6 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */ + +/* GPIO_EMC_16 (coord A5), SEMC_A7 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */ + +/* GPIO_EMC_17 (coord A4), SEMC_A8 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */ + +/* GPIO_EMC_18 (coord B2), SEMC_A9 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */ + +/* GPIO_EMC_23 (coord G2), SEMC_A10 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */ + +/* GPIO_EMC_19 (coord B4), SEMC_A11 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */ + +/* GPIO_EMC_20 (coord A3), SEMC_A12 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */ + +/* GPIO_EMC_21 (coord C1), SEMC_BA0 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_EMC_22 (coord F1), SEMC_BA1 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_EMC_24 (coord D3), SEMC_CAS */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */ + +/* GPIO_EMC_27 (coord A2), SEMC_CKE */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */ + +/* GPIO_EMC_26 (coord B3), SEMC_CLK */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */ + +/* GPIO_EMC_00 (coord E3), SEMC_D0 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_EMC_01 (coord F3), SEMC_D1 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_EMC_02 (coord F4), SEMC_D2 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_EMC_03 (coord G4), SEMC_D3 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_EMC_04 (coord F2), SEMC_D4 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */ + +/* GPIO_EMC_05 (coord G5), SEMC_D5 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */ + +/* GPIO_EMC_06 (coord H5), SEMC_D6 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */ + +/* GPIO_EMC_07 (coord H4), SEMC_D7 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */ + +/* GPIO_EMC_30 (coord C6), SEMC_D8 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */ + +/* GPIO_EMC_31 (coord C5), SEMC_D9 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */ + +/* GPIO_EMC_32 (coord D5), SEMC_D10 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */ + +/* GPIO_EMC_33 (coord C4), SEMC_D11 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */ + +/* GPIO_EMC_34 (coord D4), SEMC_D12 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */ + +/* GPIO_EMC_35 (coord E5), SEMC_D13 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */ + +/* GPIO_EMC_36 (coord C3), SEMC_D14 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */ + +/* GPIO_EMC_37 (coord E4), SEMC_D15 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */ + +/* GPIO_EMC_08 (coord H3), SEMC_DM0 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_EMC_38 (coord D6), SEMC_DM1 */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */ +#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_EMC_25 (coord D2), SEMC_RAS */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */ + +/* GPIO_EMC_28 (coord D1), SEMC_WE */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */ + +/* GPIO_EMC_41 (coord C7), ENET_MDIO */ +/* Routed pin properties */ +#define BOARD_INITSDRAMPINS_ENET_MDIO_PERIPHERAL SEMC /*!< Peripheral name */ +#define BOARD_INITSDRAMPINS_ENET_MDIO_SIGNAL CSX /*!< Signal name */ +#define BOARD_INITSDRAMPINS_ENET_MDIO_CHANNEL 0U /*!< Signal channel */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSDRAMPins(void); + +/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_D9_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_D9_SIGNAL csi_data /*!< Signal name */ +#define BOARD_INITCSIPINS_CSI_D9_CHANNEL 9U /*!< Signal channel */ + +/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_D8_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_D8_SIGNAL csi_data /*!< Signal name */ +#define BOARD_INITCSIPINS_CSI_D8_CHANNEL 8U /*!< Signal channel */ + +/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_D7_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_D7_SIGNAL csi_data /*!< Signal name */ +#define BOARD_INITCSIPINS_CSI_D7_CHANNEL 7U /*!< Signal channel */ + +/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_D6_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_D6_SIGNAL csi_data /*!< Signal name */ +#define BOARD_INITCSIPINS_CSI_D6_CHANNEL 6U /*!< Signal channel */ + +/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_D5_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_D5_SIGNAL csi_data /*!< Signal name */ +#define BOARD_INITCSIPINS_CSI_D5_CHANNEL 5U /*!< Signal channel */ + +/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_D4_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_D4_SIGNAL csi_data /*!< Signal name */ +#define BOARD_INITCSIPINS_CSI_D4_CHANNEL 4U /*!< Signal channel */ + +/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_D2_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_D2_SIGNAL csi_data /*!< Signal name */ +#define BOARD_INITCSIPINS_CSI_D2_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_D3_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_D3_SIGNAL csi_data /*!< Signal name */ +#define BOARD_INITCSIPINS_CSI_D3_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_PIXCLK_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_PIXCLK_SIGNAL csi_pixclk /*!< Signal name */ + +/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_MCLK_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_MCLK_SIGNAL csi_mclk /*!< Signal name */ + +/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_VSYNC_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_VSYNC_SIGNAL csi_vsync /*!< Signal name */ + +/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_HSYNC_PERIPHERAL CSI /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_HSYNC_SIGNAL csi_hsync /*!< Signal name */ + +/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_I2C_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_I2C_SCL_SIGNAL SCL /*!< Signal name */ + +/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_I2C_SDA_PERIPHERAL LPI2C1 /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_I2C_SDA_SIGNAL SDA /*!< Signal name */ + +/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */ +/* Routed pin properties */ +#define BOARD_INITCSIPINS_CSI_PWDN_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITCSIPINS_CSI_PWDN_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITCSIPINS_CSI_PWDN_CHANNEL 4U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITCSIPINS_CSI_PWDN_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN 4U /*!< GPIO pin number */ +#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN_MASK (1U << 4U) /*!< GPIO pin mask */ +#define BOARD_INITCSIPINS_CSI_PWDN_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITCSIPINS_CSI_PWDN_PIN 4U /*!< PORT pin number */ +#define BOARD_INITCSIPINS_CSI_PWDN_PIN_MASK (1U << 4U) /*!< PORT pin mask */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitCSIPins(void); + +/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D2_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_B0_00 (coord D7), LCDIF_CLK */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */ + +/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D3_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D4_CHANNEL 4U /*!< Signal channel */ + +/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D5_CHANNEL 5U /*!< Signal channel */ + +/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D6_CHANNEL 6U /*!< Signal channel */ + +/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D7_CHANNEL 7U /*!< Signal channel */ + +/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D8_CHANNEL 8U /*!< Signal channel */ + +/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D9_CHANNEL 9U /*!< Signal channel */ + +/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D10_CHANNEL 10U /*!< Signal channel */ + +/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D11_CHANNEL 11U /*!< Signal channel */ + +/* GPIO_B1_00 (coord A11), LCDIF_D12 */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D12_CHANNEL 12U /*!< Signal channel */ + +/* GPIO_B1_01 (coord B11), LCDIF_D13 */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D13_CHANNEL 13U /*!< Signal channel */ + +/* GPIO_B1_02 (coord C11), LCDIF_D14 */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D14_CHANNEL 14U /*!< Signal channel */ + +/* GPIO_B1_03 (coord D11), LCDIF_D15 */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D15_CHANNEL 15U /*!< Signal channel */ + +/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */ + +/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */ + +/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */ + +/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_CHANNEL 31U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN 31U /*!< GPIO pin number */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN_MASK (1U << 31U) /*!< GPIO pin mask */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN 31U /*!< PORT pin number */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN_MASK (1U << 31U) /*!< PORT pin mask */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLCDPins(void); + +/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */ +/* Routed pin properties */ +#define BOARD_INITCANPINS_CAN2_TX_PERIPHERAL CAN2 /*!< Peripheral name */ +#define BOARD_INITCANPINS_CAN2_TX_SIGNAL TX /*!< Signal name */ + +/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */ +/* Routed pin properties */ +#define BOARD_INITCANPINS_CAN2_RX_PERIPHERAL CAN2 /*!< Peripheral name */ +#define BOARD_INITCANPINS_CAN2_RX_SIGNAL RX /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitCANPins(void); + +/* GPIO_EMC_40 (coord A7), ENET_MDC */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_MDC_SIGNAL enet_mdc /*!< Signal name */ + +/* GPIO_EMC_41 (coord C7), ENET_MDIO */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL enet_mdio /*!< Signal name */ + +/* GPIO_B1_10 (coord B13), ENET_TX_CLK */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL enet_ref_clk /*!< Signal name */ + +/* GPIO_B1_04 (coord E12), ENET_RXD0 */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL enet_rx_data /*!< Signal name */ +#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_B1_05 (coord D12), ENET_RXD1 */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL enet_rx_data /*!< Signal name */ +#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_B1_06 (coord C12), ENET_CRS_DV */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL enet_rx_en /*!< Signal name */ + +/* GPIO_B1_11 (coord C13), ENET_RXER */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_RXER_SIGNAL enet_rx_er /*!< Signal name */ + +/* GPIO_B1_07 (coord B12), ENET_TXD0 */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL enet_tx_data /*!< Signal name */ +#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_B1_08 (coord A12), ENET_TXD1 */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL enet_tx_data /*!< Signal name */ +#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_B1_09 (coord A13), ENET_TXEN */ +/* Routed pin properties */ +#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL ENET /*!< Peripheral name */ +#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL enet_tx_en /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitENETPins(void); + +/* GPIO_SD_B0_05 (coord J2), SD1_D3 */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL usdhc_data /*!< Signal name */ +#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_SD_B0_04 (coord H2), SD1_D2 */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL usdhc_data /*!< Signal name */ +#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL usdhc_data /*!< Signal name */ +#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL usdhc_data /*!< Signal name */ +#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< Signal name */ + +/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL usdhc_clk /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSDHCPins(void); + +/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_B_SIGNAL FLEXSPI_B_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_B_SIGNAL FLEXSPI_B_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_02 (coord M3), FlexSPI_D1_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_B_SIGNAL FLEXSPI_B_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_03 (coord M4), FlexSPI_D0_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_B_SIGNAL FLEXSPI_B_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_04 (coord P2), FlexSPI_CLK_B */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_B_SIGNAL FLEXSPI_B_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */ +/* Routed pin properties */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITHYPERFLASHPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitHyperFlashPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/clock_config.c b/ports/mimxrt10xx/boards/imxrt1050_evkb/clock_config.c deleted file mode 100644 index a9246fc02..000000000 --- a/ports/mimxrt10xx/boards/imxrt1050_evkb/clock_config.c +++ /dev/null @@ -1,934 +0,0 @@ -/* - * Copyright 2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. - * - * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. - * - * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v10.0 -processor: MIMXRT1052xxxxB -package_id: MIMXRT1052DVL6B -mcu_data: ksdk2_0 -processor_version: 0.12.10 -board: IMXRT1050-EVKB - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "clock_config.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} -settings: -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} -- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} -- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} -- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL4.denom, value: '50'} -- {id: CCM_ANALOG.PLL4.div, value: '47'} -- {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} -- {id: CCM_ANALOG.PLL5.num, value: '0'} -- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} -- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} -- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} -- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} -sources: -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = - { - .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .postDivider = 8, /* Divider after PLL */ - .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 1); -#endif - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Video PLL. */ - uint32_t pllVideo; - /* Disable Video PLL output before initial Video PLL. */ - CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Bypass PLL first */ - CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); - CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); - CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); - pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); - CCM_ANALOG->PLL_VIDEO = pllVideo; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - /* Disable bypass for Video PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ -#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; -#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) - /* Backward compatibility for original bitfield name */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; -#else -#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." -#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} - -/******************************************************************************* - ******************* Configuration BOARD_BootClockRUN_528M ********************* - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN_528M -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 528 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 132 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} -settings: -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} -- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} -- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} -- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} -- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL4.denom, value: '50'} -- {id: CCM_ANALOG.PLL4.div, value: '47'} -- {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} -- {id: CCM_ANALOG.PLL5.num, value: '0'} -- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} -- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} -- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} -- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} -sources: -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN_528M configuration - ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_528M = - { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_528M = - { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_528M = - { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_528M = - { - .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .postDivider = 8, /* Divider after PLL */ - .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ - }; -/******************************************************************************* - * Code for BOARD_BootClockRUN_528M configuration - ******************************************************************************/ -void BOARD_BootClockRUN_528M(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 1); -#endif - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN_528M); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN_528M); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN_528M); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Video PLL. */ - uint32_t pllVideo; - /* Disable Video PLL output before initial Video PLL. */ - CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Bypass PLL first */ - CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); - CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); - CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); - pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); - pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); - CCM_ANALOG->PLL_VIDEO = pllVideo; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - /* Disable bypass for Video PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 0); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ -#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; -#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) - /* Backward compatibility for original bitfield name */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; -#else -#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." -#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_528M_CORE_CLOCK; -} diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/clock_config.h b/ports/mimxrt10xx/boards/imxrt1050_evkb/clock_config.h deleted file mode 100644 index 3e4009634..000000000 --- a/ports/mimxrt10xx/boards/imxrt1050_evkb/clock_config.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright 2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Video PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************* Configuration BOARD_BootClockRUN_528M ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN_528M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_528M_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_528M_AHB_CLK_ROOT 528000000UL -#define BOARD_BOOTCLOCKRUN_528M_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_528M_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_528M_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_528M_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_528M_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_528M_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_528M_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_528M_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_FLEXSPI_CLK_ROOT 160000000UL -#define BOARD_BOOTCLOCKRUN_528M_GPT1_IPG_CLK_HIGHFREQ 66000000UL -#define BOARD_BOOTCLOCKRUN_528M_GPT2_IPG_CLK_HIGHFREQ 66000000UL -#define BOARD_BOOTCLOCKRUN_528M_IPG_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_528M_LCDIF_CLK_ROOT 67500000UL -#define BOARD_BOOTCLOCKRUN_528M_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_528M_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_528M_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_528M_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_PERCLK_CLK_ROOT 66000000UL -#define BOARD_BOOTCLOCKRUN_528M_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_528M_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_528M_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_528M_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_528M_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_SEMC_CLK_ROOT 66000000UL -#define BOARD_BOOTCLOCKRUN_528M_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_528M_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_528M_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_528M_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_528M_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_528M_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_528M_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN_528M configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_528M; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN_528M configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_528M; -/*! @brief Sys PLL for BOARD_BootClockRUN_528M configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_528M; -/*! @brief Video PLL set for BOARD_BootClockRUN_528M configuration. - */ -extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_528M; - -/******************************************************************************* - * API for BOARD_BootClockRUN_528M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN_528M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/flash_config.c b/ports/mimxrt10xx/boards/imxrt1050_evkb/flash_config.c index d96d588e7..c11d67c88 100644 --- a/ports/mimxrt10xx/boards/imxrt1050_evkb/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/flash_config.c @@ -9,163 +9,150 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - +#if 1 // Config for IS25WP064A with QSPI after changing resistors to send signal to // QSPI instead of hyper flash! -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = + { + .seqId = 4u, .seqNum = 1u, }, - .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .deviceModeArg = 0x40, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, + }, +}; + +#else +// hyperflash +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), }, }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, }; +#endif diff --git a/ports/mimxrt10xx/boards/imxrt1050_evkb/mimxrt1050_evkb.mex b/ports/mimxrt10xx/boards/imxrt1050_evkb/mimxrt1050_evkb.mex new file mode 100644 index 000000000..51befc57f --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1050_evkb/mimxrt1050_evkb.mex @@ -0,0 +1,1030 @@ + + + + MIMXRT1052xxxxB + MIMXRT1052DVL6B + IMXRT1050-EVKB + A + ksdk2_0 + + + + + + + false + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 0.0.0 + + + + + + + 13.0.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + kELCDIF_CurFrameDoneInterruptEnable + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + + + + diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/board.cmake b/ports/mimxrt10xx/boards/imxrt1060_evk/board.cmake new file mode 100644 index 000000000..e552acb54 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT MIMXRT1062) + +set(JLINK_DEVICE MIMXRT1062xxx6A) +set(PYOCD_TARGET mimxrt1060) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1062DVL6A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/board.h b/ports/mimxrt10xx/boards/imxrt1060_evk/board.h index 85fae6184..7cac4ac89 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/board.h +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/board.h @@ -1,82 +1,73 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Ha Thach for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// Size of on-board external flash -#define BOARD_FLASH_SIZE (8*1024*1024) - -//--------------------------------------------------------------------+ -// LED -//--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 -#define LED_PORT GPIO1 -#define LED_PIN 9 -#define LED_STATE_ON 0 - -//--------------------------------------------------------------------+ -// Neopixel -//--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 0 - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// SW8 button -#define BUTTON_PINMUX IOMUXC_SNVS_WAKEUP_GPIO5_IO00 -#define BUTTON_PORT GPIO5 -#define BUTTON_PIN 0 -#define BUTTON_STATE_ACTIVE 0 - -//--------------------------------------------------------------------+ -// USB UF2 -//--------------------------------------------------------------------+ - -#define USB_VID 0x239A -#define USB_PID 0x0083 -#define USB_MANUFACTURER "NXP" -#define USB_PRODUCT "RT1060 EVK" - -#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT -#define UF2_BOARD_ID "MIMXRT1060-EVK-revA" -#define UF2_VOLUME_LABEL "RT1060BOOT" -#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1060-EVK#/" - -//--------------------------------------------------------------------+ -// UART -//--------------------------------------------------------------------+ - -#define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_13_LPUART1_RX -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_12_LPUART1_TX - -#endif /* BOARD_H_ */ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Ha Thach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Size of on-board external flash +#define BOARD_FLASH_SIZE (8*1024*1024) + +//--------------------------------------------------------------------+ +// LED +//--------------------------------------------------------------------+ +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL +#define LED_STATE_ON 0 + +//--------------------------------------------------------------------+ +// Neopixel +//--------------------------------------------------------------------+ +#define NEOPIXEL_NUMBER 0 // Number of neopixels + +//--------------------------------------------------------------------+ +// Button +//--------------------------------------------------------------------+ +// SW8 button +#define BUTTON_PINMUX IOMUXC_SNVS_WAKEUP_GPIO5_IO00 +#define BUTTON_PORT GPIO5 +#define BUTTON_PIN 0 +#define BUTTON_STATE_ACTIVE 0 + +//--------------------------------------------------------------------+ +// USB UF2 +//--------------------------------------------------------------------+ +#define USB_VID 0x239A +#define USB_PID 0x0083 +#define USB_MANUFACTURER "NXP" +#define USB_PRODUCT "RT1060 EVK" + +#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT +#define UF2_BOARD_ID "MIMXRT1060-EVK-revA" +#define UF2_VOLUME_LABEL "RT1060BOOT" +#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1060-EVK#/" + +//--------------------------------------------------------------------+ +// UART +//--------------------------------------------------------------------+ +#define UART_DEV LPUART1 + +#endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/clock_config.c b/ports/mimxrt10xx/boards/imxrt1060_evk/board/clock_config.c similarity index 74% rename from ports/mimxrt10xx/boards/imxrt1060_evk/clock_config.c rename to ports/mimxrt10xx/boards/imxrt1060_evk/board/clock_config.c index 38f0b8f99..31329ed60 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/clock_config.c +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/board/clock_config.c @@ -1,10 +1,3 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* * How to setup clock using clock driver functions: * @@ -22,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v5.0 +product: Clocks v18.0 processor: MIMXRT1062xxxxA package_id: MIMXRT1062DVL6A mcu_data: ksdk2_0 -processor_version: 0.0.0 +processor_version: 25.09.10 board: MIMXRT1060-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -40,8 +33,6 @@ board: MIMXRT1060-EVK /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ @@ -65,9 +56,7 @@ called_from_default_init: true - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} -- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} @@ -77,13 +66,13 @@ called_from_default_init: true - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} - {id: MQS_MCLK.outFreq, value: 1080/17 MHz} - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} @@ -96,8 +85,10 @@ called_from_default_init: true - {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} settings: @@ -107,10 +98,13 @@ called_from_default_init: true - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} @@ -131,32 +125,57 @@ called_from_default_init: true - {id: CCM_ANALOG.PLL4.denom, value: '50'} - {id: CCM_ANALOG.PLL4.div, value: '47'} - {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} - {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -222,9 +241,8 @@ void BOARD_BootClockRUN(void) /* Set Usdhc2 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); @@ -236,9 +254,8 @@ void BOARD_BootClockRUN(void) CLOCK_SetMux(kCLOCK_SemcMux, 0); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); @@ -271,9 +288,9 @@ void BOARD_BootClockRUN(void) /* Disable TRACE clock gate. */ CLOCK_DisableClock(kCLOCK_Trace); /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -367,10 +384,12 @@ void BOARD_BootClockRUN(void) /* Init ARM PLL. */ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ @@ -383,9 +402,8 @@ void BOARD_BootClockRUN(void) CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Init Usb1 PLL. */ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); @@ -397,8 +415,6 @@ void BOARD_BootClockRUN(void) CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); /* Init Usb1 pfd3. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); @@ -409,36 +425,41 @@ void BOARD_BootClockRUN(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); /* DeInit Enet PLL. */ CLOCK_DeinitEnetPll(); /* Bypass Enet PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); /* Enable Enet output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; /* Set Enet2 output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); /* Enable Enet2 output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; /* Enable Enet25M output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); /* Set preperiph clock source. */ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ @@ -448,8 +469,7 @@ void BOARD_BootClockRUN(void) /* Set per clock source. */ CLOCK_SetMux(kCLOCK_PerclkMux, 0); /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = - (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); /* Set clock out1 divider. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); /* Set clock out1 source. */ @@ -475,15 +495,11 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET1 Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); - /* Set ENET2 Tx clock source. */ -#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); -#else - IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); -#endif + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/board/clock_config.h b/ports/mimxrt10xx/boards/imxrt1060_evk/board/clock_config.h new file mode 100644 index 000000000..2fa713c0d --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/board/clock_config.h @@ -0,0 +1,123 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/board/pin_mux.c b/ports/mimxrt10xx/boards/imxrt1060_evk/board/pin_mux.c new file mode 100644 index 000000000..48cde3c2c --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/board/pin_mux.c @@ -0,0 +1,144 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1060-EVK +pin_labels: +- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED} +- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper} + - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + + /* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */ + GPIO_PinInit(GPIO1, 9U, &USER_LED_config); + + /* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on WAKEUP (pin L6) */ + GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} + - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} + - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} + - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} + - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/board/pin_mux.h b/ports/mimxrt10xx/boards/imxrt1060_evk/board/pin_mux.h new file mode 100644 index 000000000..916ea3853 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/board/pin_mux.h @@ -0,0 +1,145 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x0200U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */ + +/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 9U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 9U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 9U) /*!< PORT pin mask */ + +/* WAKEUP (coord L6), SD_PWREN */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/clock_config.h b/ports/mimxrt10xx/boards/imxrt1060_evk/clock_config.h deleted file mode 100644 index 082202484..000000000 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/clock_config.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c index aa7b2fdd6..da3a9e5fe 100644 --- a/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c @@ -9,162 +9,114 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for IS25WP064A with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 4u, + .seqNum = 1u, }, + .deviceModeArg = 0x40, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1060_evk/mimxrt1060_evk.mex b/ports/mimxrt10xx/boards/imxrt1060_evk/mimxrt1060_evk.mex new file mode 100644 index 000000000..89396c5d5 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1060_evk/mimxrt1060_evk.mex @@ -0,0 +1,616 @@ + + + + MIMXRT1062xxxxA + MIMXRT1062DVL6A + MIMXRT1060-EVK + A2 + ksdk2_0 + + + + + + + false + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 0.0.0 + + + + + + + 13.0.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + kELCDIF_CurFrameDoneInterruptEnable + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + diff --git a/ports/mimxrt10xx/boards/imxrt1064_evk/board.cmake b/ports/mimxrt10xx/boards/imxrt1064_evk/board.cmake new file mode 100644 index 000000000..d9a6da8a2 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1064_evk/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT MIMXRT1064) + +set(JLINK_DEVICE MIMXRT1064xxx6A) +set(PYOCD_TARGET mimxrt1064) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1064DVL6A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/imxrt1064_evk/board.h b/ports/mimxrt10xx/boards/imxrt1064_evk/board.h index 84ff8e7df..09a1d4dda 100644 --- a/ports/mimxrt10xx/boards/imxrt1064_evk/board.h +++ b/ports/mimxrt10xx/boards/imxrt1064_evk/board.h @@ -1,83 +1,64 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Ha Thach for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// Size of on-chip 4MB flash -#define BOARD_FLASH_SIZE (4*1024*1024) - -//--------------------------------------------------------------------+ -// LED -//--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 -#define LED_PORT GPIO1 -#define LED_PIN 9 -#define LED_STATE_ON 0 - -//--------------------------------------------------------------------+ -// Neopixel -//--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 0 - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// SW8 button -#define BUTTON_PINMUX IOMUXC_SNVS_WAKEUP_GPIO5_IO00 -#define BUTTON_PORT GPIO5 -#define BUTTON_PIN 0 -#define BUTTON_STATE_ACTIVE 0 - -//--------------------------------------------------------------------+ -// USB UF2 -//--------------------------------------------------------------------+ - -#define USB_VID 0x239A -#define USB_PID 0x0083 -#define USB_MANUFACTURER "NXP" -#define USB_PRODUCT "RT1064 EVK" - -#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT -#define UF2_BOARD_ID "MIMXRT1064-EVK-revA" -#define UF2_VOLUME_LABEL "RT1064BOOT" -#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1064-EVK#/" - -//--------------------------------------------------------------------+ -// UART -//--------------------------------------------------------------------+ - -#define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_13_LPUART1_RX -// On J46 farthest from the edge. -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_12_LPUART1_TX - -#endif /* BOARD_H_ */ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Ha Thach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Size of on-chip 4MB flash +#define BOARD_FLASH_SIZE (4*1024*1024) + +//--------------------------------------------------------------------+ +// LED +//--------------------------------------------------------------------+ +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL +#define LED_STATE_ON 0 + +//--------------------------------------------------------------------+ +// Neopixel +//--------------------------------------------------------------------+ +#define NEOPIXEL_NUMBER 0 // Number of neopixels + +//--------------------------------------------------------------------+ +// USB UF2 +//--------------------------------------------------------------------+ +#define USB_VID 0x239A +#define USB_PID 0x0083 +#define USB_MANUFACTURER "NXP" +#define USB_PRODUCT "RT1064 EVK" + +#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT +#define UF2_BOARD_ID "MIMXRT1064-EVK-revA" +#define UF2_VOLUME_LABEL "RT1064BOOT" +#define UF2_INDEX_URL "https://www.nxp.com/part/MIMXRT1064-EVK#/" + +//--------------------------------------------------------------------+ +// UART +//--------------------------------------------------------------------+ +#define UART_DEV LPUART1 + +#endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1064_evk/clock_config.c b/ports/mimxrt10xx/boards/imxrt1064_evk/board/clock_config.c similarity index 75% rename from ports/mimxrt10xx/boards/imxrt1064_evk/clock_config.c rename to ports/mimxrt10xx/boards/imxrt1064_evk/board/clock_config.c index 9a22cd4b8..7d9f498be 100644 --- a/ports/mimxrt10xx/boards/imxrt1064_evk/clock_config.c +++ b/ports/mimxrt10xx/boards/imxrt1064_evk/board/clock_config.c @@ -1,10 +1,3 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* * How to setup clock using clock driver functions: * @@ -22,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v5.0 +product: Clocks v18.0 processor: MIMXRT1064xxxxA package_id: MIMXRT1064DVL6A mcu_data: ksdk2_0 -processor_version: 0.0.0 +processor_version: 25.09.10 board: MIMXRT1064-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -40,8 +33,6 @@ board: MIMXRT1064-EVK /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ @@ -65,9 +56,7 @@ called_from_default_init: true - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} -- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} @@ -83,7 +72,7 @@ called_from_default_init: true - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} - {id: MQS_MCLK.outFreq, value: 1080/17 MHz} - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} @@ -96,8 +85,10 @@ called_from_default_init: true - {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} settings: @@ -107,10 +98,13 @@ called_from_default_init: true - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} @@ -126,37 +120,64 @@ called_from_default_init: true - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD1_DIV.scale, value: '16', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_MUL.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} - {id: CCM_ANALOG.PLL4.denom, value: '50'} - {id: CCM_ANALOG.PLL4.div, value: '47'} - {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} - {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -222,9 +243,8 @@ void BOARD_BootClockRUN(void) /* Set Usdhc2 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); @@ -242,8 +262,7 @@ void BOARD_BootClockRUN(void) /* Set Flexspi clock source. */ CLOCK_SetMux(kCLOCK_FlexspiMux, 3); /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left - * unchanged. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi2 clock gate. */ @@ -271,9 +290,9 @@ void BOARD_BootClockRUN(void) /* Disable TRACE clock gate. */ CLOCK_DisableClock(kCLOCK_Trace); /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -367,10 +386,12 @@ void BOARD_BootClockRUN(void) /* Init ARM PLL. */ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ @@ -383,8 +404,7 @@ void BOARD_BootClockRUN(void) CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); #endif /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left - * unchanged. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Init Usb1 PLL. */ @@ -397,8 +417,6 @@ void BOARD_BootClockRUN(void) CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); /* Init Usb1 pfd3. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); @@ -409,36 +427,41 @@ void BOARD_BootClockRUN(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); /* DeInit Enet PLL. */ CLOCK_DeinitEnetPll(); /* Bypass Enet PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); /* Enable Enet output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; /* Set Enet2 output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); /* Enable Enet2 output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; /* Enable Enet25M output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); /* Set preperiph clock source. */ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ @@ -448,8 +471,7 @@ void BOARD_BootClockRUN(void) /* Set per clock source. */ CLOCK_SetMux(kCLOCK_PerclkMux, 0); /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = - (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); /* Set clock out1 divider. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); /* Set clock out1 source. */ @@ -475,15 +497,11 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET1 Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); - /* Set ENET2 Tx clock source. */ -#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); -#else - IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); -#endif + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/boards/imxrt1064_evk/board/clock_config.h b/ports/mimxrt10xx/boards/imxrt1064_evk/board/clock_config.h new file mode 100644 index 000000000..2fa713c0d --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1064_evk/board/clock_config.h @@ -0,0 +1,123 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1064_evk/board/pin_mux.c b/ports/mimxrt10xx/boards/imxrt1064_evk/board/pin_mux.c new file mode 100644 index 000000000..0dfb42bb3 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1064_evk/board/pin_mux.c @@ -0,0 +1,236 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1064xxxxA +package_id: MIMXRT1064DVL6A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1064-EVK +pin_labels: +- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED} +- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper} + - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + + /* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */ + GPIO_PinInit(GPIO1, 9U, &USER_LED_config); + + /* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on WAKEUP (pin L6) */ + GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLCDPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + - {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow} + - {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLCDPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitLCDPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) + ); + IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 & + (~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} + - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} + - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} + - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} + - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1064_evk/board/pin_mux.h b/ports/mimxrt10xx/boards/imxrt1064_evk/board/pin_mux.h new file mode 100644 index 000000000..c89901bd7 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1064_evk/board/pin_mux.h @@ -0,0 +1,284 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x0200U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */ + +/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 9U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 9U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 9U) /*!< PORT pin mask */ + +/* WAKEUP (coord L6), SD_PWREN */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x04U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */ +#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x80000000U /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */ + +/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D2_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_B0_00 (coord D7), LCDIF_CLK */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */ + +/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D3_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D4_CHANNEL 4U /*!< Signal channel */ + +/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D5_CHANNEL 5U /*!< Signal channel */ + +/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D6_CHANNEL 6U /*!< Signal channel */ + +/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D7_CHANNEL 7U /*!< Signal channel */ + +/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D8_CHANNEL 8U /*!< Signal channel */ + +/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D9_CHANNEL 9U /*!< Signal channel */ + +/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D10_CHANNEL 10U /*!< Signal channel */ + +/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D11_CHANNEL 11U /*!< Signal channel */ + +/* GPIO_B1_00 (coord A11), LCDIF_D12 */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D12_CHANNEL 12U /*!< Signal channel */ + +/* GPIO_B1_01 (coord B11), LCDIF_D13 */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D13_CHANNEL 13U /*!< Signal channel */ + +/* GPIO_B1_02 (coord C11), LCDIF_D14 */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D14_CHANNEL 14U /*!< Signal channel */ + +/* GPIO_B1_03 (coord D11), LCDIF_D15 */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */ +#define BOARD_INITLCDPINS_LCDIF_D15_CHANNEL 15U /*!< Signal channel */ + +/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */ + +/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */ + +/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */ +#define BOARD_INITLCDPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */ + +/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */ +/* Routed pin properties */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_CHANNEL 31U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN 31U /*!< GPIO pin number */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN_MASK (1U << 31U) /*!< GPIO pin mask */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN 31U /*!< PORT pin number */ +#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN_MASK (1U << 31U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLCDPins(void); + +/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1064_evk/clock_config.h b/ports/mimxrt10xx/boards/imxrt1064_evk/clock_config.h deleted file mode 100644 index 13bc925a1..000000000 --- a/ports/mimxrt10xx/boards/imxrt1064_evk/clock_config.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1064_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1064_evk/flash_config.c index bc7175887..c0d45a867 100644 --- a/ports/mimxrt10xx/boards/imxrt1064_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1064_evk/flash_config.c @@ -9,172 +9,122 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for on-chip W25Q32JV with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = + { + .seqId = 4u, .seqNum = 1u, }, - .deviceModeArg = 0x0200, - .configCmdEnable = 1u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .configCmdSeqs[0] = { - .seqId = 2u, - .seqNum = 1u, - }, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = BOARD_FLASH_SIZE, - .lookupTable = + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, - DUMMY_SDR, FLEXSPI_1PAD, 8), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 2u, + .seqNum = 1u, }, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = BOARD_FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* the command to send */, DUMMY_SDR, FLEXSPI_1PAD, 8), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/imxrt1064_evk/mimxrt1064_evk.mex b/ports/mimxrt10xx/boards/imxrt1064_evk/mimxrt1064_evk.mex new file mode 100644 index 000000000..6fc741a33 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1064_evk/mimxrt1064_evk.mex @@ -0,0 +1,794 @@ + + + + MIMXRT1064xxxxA + MIMXRT1064DVL6A + MIMXRT1064-EVK + 1 + ksdk2_0 + + + + + + + true + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 0.0.0 + + + + + + + 13.0.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + kCSI_HsyncActiveHigh + kCSI_VsyncActiveLow + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + kELCDIF_CurFrameDoneInterruptEnable + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + diff --git a/ports/mimxrt10xx/boards/imxrt1170_evk/board.cmake b/ports/mimxrt10xx/boards/imxrt1170_evk/board.cmake index e445f9542..49ea81f31 100644 --- a/ports/mimxrt10xx/boards/imxrt1170_evk/board.cmake +++ b/ports/mimxrt10xx/boards/imxrt1170_evk/board.cmake @@ -5,10 +5,6 @@ set(PYOCD_TARGET mimxrt1170_cm7) set(NXPLINK_DEVICE MIMXRT1176xxxxx:MIMXRT1170-EVK) function(update_board TARGET) - target_sources(${TARGET} PRIVATE - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash_config.c - ) target_compile_definitions(${TARGET} PUBLIC CPU_MIMXRT1176DVMAA_cm7 MIMXRT117x_SERIES diff --git a/ports/mimxrt10xx/boards/imxrt1170_evk/board.h b/ports/mimxrt10xx/boards/imxrt1170_evk/board.h index 72e33ad9a..01ed5cb68 100644 --- a/ports/mimxrt10xx/boards/imxrt1170_evk/board.h +++ b/ports/mimxrt10xx/boards/imxrt1170_evk/board.h @@ -31,33 +31,18 @@ //--------------------------------------------------------------------+ // LED //--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_AD_04_GPIO9_IO03 -#define LED_PORT GPIO9 -#define LED_PIN 3 +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL #define LED_STATE_ON 1 //--------------------------------------------------------------------+ // Neopixel //--------------------------------------------------------------------+ - -// Number of neopixels #define NEOPIXEL_NUMBER 0 -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// SW7 button on WAKEUP pin -#define BUTTON_PINMUX IOMUXC_WAKEUP_DIG_GPIO13_IO00 -#define BUTTON_PORT GPIO13 -#define BUTTON_PIN 0 -#define BUTTON_STATE_ACTIVE 0 - //--------------------------------------------------------------------+ // USB UF2 //--------------------------------------------------------------------+ - #define USB_VID 0x239A #define USB_PID 0x0099 #define USB_MANUFACTURER "NXP" @@ -71,7 +56,6 @@ //--------------------------------------------------------------------+ // USB PHY //--------------------------------------------------------------------+ - #define BOARD_USB_PHY_D_CAL (0x07U) #define BOARD_USB_PHY_TXCAL45DP (0x06U) #define BOARD_USB_PHY_TXCAL45DM (0x06U) @@ -79,9 +63,6 @@ //--------------------------------------------------------------------+ // UART //--------------------------------------------------------------------+ - #define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_25_LPUART1_RXD -#define UART_TX_PINMUX IOMUXC_GPIO_AD_24_LPUART1_TXD #endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1170_evk/clock_config.c b/ports/mimxrt10xx/boards/imxrt1170_evk/board/clock_config.c similarity index 99% rename from ports/mimxrt10xx/boards/imxrt1170_evk/clock_config.c rename to ports/mimxrt10xx/boards/imxrt1170_evk/board/clock_config.c index 864100763..ba940e174 100644 --- a/ports/mimxrt10xx/boards/imxrt1170_evk/clock_config.c +++ b/ports/mimxrt10xx/boards/imxrt1170_evk/board/clock_config.c @@ -16,7 +16,7 @@ * */ -#include "clock_config.h" +#include "board/clock_config.h" #include "fsl_iomuxc.h" #include "fsl_dcdc.h" #include "fsl_pmu.h" diff --git a/ports/mimxrt10xx/boards/imxrt1170_evk/clock_config.h b/ports/mimxrt10xx/boards/imxrt1170_evk/board/clock_config.h similarity index 100% rename from ports/mimxrt10xx/boards/imxrt1170_evk/clock_config.h rename to ports/mimxrt10xx/boards/imxrt1170_evk/board/clock_config.h diff --git a/ports/mimxrt10xx/boards/imxrt1170_evk/board/pin_mux.c b/ports/mimxrt10xx/boards/imxrt1170_evk/board/pin_mux.c new file mode 100644 index 000000000..ced23addf --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1170_evk/board/pin_mux.c @@ -0,0 +1,143 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1176xxxxx +package_id: MIMXRT1176DVMAA +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1170-EVKB +external_user_signals: {} +pin_labels: +- {pin_num: M13, pin_signal: GPIO_AD_04, label: 'SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]', identifier: SIM1_PD;LED;USER_LED} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: M13, peripheral: GPIO9, signal: 'gpio_io, 03', pin_signal: GPIO_AD_04, identifier: USER_LED, direction: OUTPUT, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper} + - {pin_num: T8, peripheral: GPIO13, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ + + /* GPIO configuration of USER_LED on GPIO_AD_04 (pin M13) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_AD_04 (pin M13) */ + GPIO_PinInit(GPIO9, 3U, &USER_LED_config); + + /* GPIO configuration of USER_BUTTON on WAKEUP_DIG (pin T8) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on WAKEUP_DIG (pin T8) */ + GPIO_PinInit(GPIO13, 0U, &USER_BUTTON_config); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 is configured as GPIO9_IO03 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG is configured as GPIO13_IO00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */ + 0x0EU); /* Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain SNVS Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, pull_keeper_select: Keeper, slew_rate: Slow} + - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, pull_keeper_select: Keeper, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */ + 0x03U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */ + 0x03U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: high drive strength + Pull / Keep Select Field: Pull Disable + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1170_evk/board/pin_mux.h b/ports/mimxrt10xx/boards/imxrt1170_evk/board/pin_mux.h new file mode 100644 index 000000000..0e0368ef6 --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1170_evk/board/pin_mux.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_AD_04 (coord M13), SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO9 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 3U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO9 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */ + +/* WAKEUP (coord T8), USER_BUTTON/SW7 */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO13 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO13 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M7F */ + +/* GPIO_AD_24 (coord L13), LPUART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */ + +/* GPIO_AD_25 (coord M15), LPUART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M7F */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/imxrt1170_evk/flash_config.c b/ports/mimxrt10xx/boards/imxrt1170_evk/flash_config.c index 28593ea5e..af04b8c34 100644 --- a/ports/mimxrt10xx/boards/imxrt1170_evk/flash_config.c +++ b/ports/mimxrt10xx/boards/imxrt1170_evk/flash_config.c @@ -8,34 +8,8 @@ #include "flexspi_nor_flash.h" #include "fsl_flexspi_nor_boot.h" #include "boards.h" - - -/************************************* - * IVT Data - *************************************/ -__attribute__((section(".boot_hdr.ivt"))) const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -/************************************* - * Boot Data - *************************************/ -__attribute__((section(".boot_hdr.boot_data"))) const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, // Dest memory that BootROM will copy to - BOARD_BOOT_LENGTH, /* bootloader length */ - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for IS25WP128 (16MB QSPI NOR Flash) on MIMXRT1170-EVK -#define QSPI_FLASH_CONFIG_INIT \ +#define FLASH_NOR_CONFIG_INIT \ { \ .pageSize = 256u, \ .sectorSize = 4u * 1024u, \ @@ -176,16 +150,8 @@ __attribute__((section(".boot_hdr.boot_data"))) const BOOT_DATA_T g_boot_data = }, \ } +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = FLASH_NOR_CONFIG_INIT; -__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t qspiflash_config = QSPI_FLASH_CONFIG_INIT; - - -// For SDP image-load, to create ivt at zero address we cooks boot data and left-out fcfb section. We need a copy to +// For blhost image-load, to create ivt at zero address we cooks boot data and left-out fcfb section. We need a copy to // write to flash. -const BOOT_DATA_T g_boot_data_copy = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, /* bootloader length */ - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; -const flexspi_nor_config_t qspiflash_config_copy = QSPI_FLASH_CONFIG_INIT; +const flexspi_nor_config_t flash_nor_config_copy = FLASH_NOR_CONFIG_INIT; diff --git a/ports/mimxrt10xx/boards/imxrt1170_evk/mimxrt1170_evkb.mex b/ports/mimxrt10xx/boards/imxrt1170_evk/mimxrt1170_evkb.mex new file mode 100644 index 000000000..2099126db --- /dev/null +++ b/ports/mimxrt10xx/boards/imxrt1170_evk/mimxrt1170_evkb.mex @@ -0,0 +1,662 @@ + + + + MIMXRT1176xxxxx + MIMXRT1176DVMAA + MIMXRT1170-EVKB + ksdk2_0 + + + + + Configuration imported from evkbmimxrt1170_dev_cdc_vcom_lite_bm_cm7 + + + true + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + cm7 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + cm7 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 13.0.2 + c_array + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + 2.5.1 + + + + + + 13.0.2 + + + + + + + + + 0 + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + N/A + + + + diff --git a/ports/mimxrt10xx/boards/makerdiary_rt1011/board.cmake b/ports/mimxrt10xx/boards/makerdiary_rt1011/board.cmake new file mode 100644 index 000000000..ec823c0e3 --- /dev/null +++ b/ports/mimxrt10xx/boards/makerdiary_rt1011/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT MIMXRT1011) + +set(JLINK_DEVICE MIMXRT1011DAE5A) +set(PYOCD_TARGET mimxrt1010) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1011DAE5A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/makerdiary_rt1011/board.h b/ports/mimxrt10xx/boards/makerdiary_rt1011/board.h index 2f16a350d..8745cdf78 100644 --- a/ports/mimxrt10xx/boards/makerdiary_rt1011/board.h +++ b/ports/mimxrt10xx/boards/makerdiary_rt1011/board.h @@ -34,50 +34,18 @@ //--------------------------------------------------------------------+ // LED //--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_SD_04_GPIO2_IO04 -#define LED_PORT GPIO2 -#define LED_PIN 4 +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL #define LED_STATE_ON 1 -#if 0 -// PWM Test on Arduino header D8 -#define LED_PWM_PINMUX IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A -#define LED_PWM_BASE PWM1 -#define LED_PWM_MODULE kPWM_Module_0 -#define LED_PWM_CHANNEL kPWM_PwmA -#endif - //--------------------------------------------------------------------+ // Neopixel //--------------------------------------------------------------------+ - -// Number of neopixels -#if 1 -#define NEOPIXEL_NUMBER 0 - -#else -// Neopixel Test on Arduino header A0 -#define NEOPIXEL_NUMBER 1 -#define NEOPIXEL_PINMUX IOMUXC_GPIO_AD_07_GPIOMUX_IO21 -#define NEOPIXEL_PORT GPIO1 -#define NEOPIXEL_PIN 21 -#endif - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// SW8 button -#define BUTTON_PINMUX IOMUXC_GPIO_SD_11_GPIO2_IO11 -#define BUTTON_PORT GPIO2 -#define BUTTON_PIN 11 -#define BUTTON_STATE_ACTIVE 0 +#define NEOPIXEL_NUMBER 0 // Number of neopixels //--------------------------------------------------------------------+ // USB UF2 //--------------------------------------------------------------------+ - #define USB_VID 0x2886 #define USB_PID 0xf00f #define USB_MANUFACTURER "Makerdiary" @@ -91,9 +59,6 @@ //--------------------------------------------------------------------+ // UART //--------------------------------------------------------------------+ - #define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_09_LPUART1_RXD -#define UART_TX_PINMUX IOMUXC_GPIO_10_LPUART1_TXD #endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/clock_config.c b/ports/mimxrt10xx/boards/makerdiary_rt1011/board/clock_config.c similarity index 84% rename from ports/mimxrt10xx/boards/metro_m7_1011/clock_config.c rename to ports/mimxrt10xx/boards/makerdiary_rt1011/board/clock_config.c index 178d62a84..76cb0a480 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/clock_config.c +++ b/ports/mimxrt10xx/boards/makerdiary_rt1011/board/clock_config.c @@ -1,10 +1,3 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* * How to setup clock using clock driver functions: * @@ -22,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v6.0 +product: Clocks v18.0 processor: MIMXRT1011xxxxx package_id: MIMXRT1011DAE5A mcu_data: ksdk2_0 -processor_version: 0.0.1 +processor_version: 25.09.10 board: MIMXRT1010-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -40,8 +33,6 @@ board: MIMXRT1010-EVK /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ @@ -82,21 +73,21 @@ called_from_default_init: true - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY_CLK.outFreq, value: 480 MHz} settings: - {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} - {id: CCM.AHB_PODF.scale, value: '1', locked: true} - {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} - {id: CCM.IPG_PODF.scale, value: '4'} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5'} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} - {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} - {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} - {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.div, value: '22'} - {id: CCM_ANALOG.PLL2.num, value: '0'} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} @@ -117,29 +108,33 @@ called_from_default_init: true - {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { - .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -161,22 +156,19 @@ void BOARD_BootClockRUN(void) CLOCK_SwitchOsc(kCLOCK_XtalOsc); /* Set Oscillator ready counter value. */ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */ + /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); /* Waiting for DCDC_STS_DC_OK bit is asserted */ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Disable IPG clock gate. */ CLOCK_DisableClock(kCLOCK_Adc1); CLOCK_DisableClock(kCLOCK_Xbar1); /* Set IPG_PODF. */ CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); /* Disable PERCLK clock gate. */ CLOCK_DisableClock(kCLOCK_Gpt1); CLOCK_DisableClock(kCLOCK_Gpt1S); @@ -186,9 +178,8 @@ void BOARD_BootClockRUN(void) /* Set PERCLK_PODF. */ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); @@ -212,9 +203,9 @@ void BOARD_BootClockRUN(void) /* Disable TRACE clock gate. */ CLOCK_DisableClock(kCLOCK_Trace); /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -263,22 +254,9 @@ void BOARD_BootClockRUN(void) CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); /* Set Flexio1 clock source. */ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Init Usb1 PLL. */ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); @@ -290,9 +268,28 @@ void BOARD_BootClockRUN(void) CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); /* Init Usb1 pfd3. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif + /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */ + /* Set Pll3 SW clock source to use the USB1 PLL output. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Set safe value of the AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 1); + /* Set periph clock2 clock source to use the PLL3_SW_CLK. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); /* Bypass Audio PLL. */ @@ -302,16 +299,14 @@ void BOARD_BootClockRUN(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); /* Set preperiph clock source. */ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ CLOCK_SetMux(kCLOCK_PeriphMux, 0); /* Set periph clock2 clock source. */ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Set clock out1 divider. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); /* Set clock out1 source. */ @@ -335,7 +330,7 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/boards/makerdiary_rt1011/board/clock_config.h b/ports/mimxrt10xx/boards/makerdiary_rt1011/board/clock_config.h new file mode 100644 index 000000000..cc627cf6a --- /dev/null +++ b/ports/mimxrt10xx/boards/makerdiary_rt1011/board/clock_config.h @@ -0,0 +1,97 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL /* Clock consumers of ADC_ALT_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL /* Clock consumers of CORE_CLK_ROOT output : ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AIPSTZ1, AIPSTZ2, AOI, ARM, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, OCOTP, PWM1, RTWDOG, SAI1, SAI3, SNVS, SPDIF, SRC, TEMPMON, TRNG, USB, WDOG1, WDOG2, XBARA */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */ + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/makerdiary_rt1011/board/pin_mux.c b/ports/mimxrt10xx/boards/makerdiary_rt1011/board/pin_mux.c new file mode 100644 index 000000000..7bcd85f8a --- /dev/null +++ b/ports/mimxrt10xx/boards/makerdiary_rt1011/board/pin_mux.c @@ -0,0 +1,113 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1011xxxxx +package_id: MIMXRT1011DAE5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1010-EVK +external_user_signals: {} +pin_labels: +- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: USER_LED} +- {pin_num: '72', pin_signal: GPIO_SD_04, label: 'GPIO_SD_04/BOOT_MODE[0]', identifier: USER_LED} +power_domains: {NVCC_GPIO: '3.3'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '72', peripheral: GPIO2, signal: 'gpio_io, 04', pin_signal: GPIO_SD_04} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_04_GPIO2_IO04, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09} + - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '65', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_10} + - {pin_num: '66', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_09} + - {pin_num: '68', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_07} + - {pin_num: '67', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_08} + - {pin_num: '64', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_11} + - {pin_num: '69', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_06} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3, 0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/makerdiary_rt1011/board/pin_mux.h b/ports/mimxrt10xx/boards/makerdiary_rt1011/board/pin_mux.h new file mode 100644 index 000000000..9f5275f25 --- /dev/null +++ b/ports/mimxrt10xx/boards/makerdiary_rt1011/board/pin_mux.h @@ -0,0 +1,123 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_SD_04 (number 72), GPIO_SD_04/BOOT_MODE[0] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 4U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 4U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 4U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 4U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 4U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */ + +/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_10 (number 65), FlexSPI_CLK_A/U13[6] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_09 (number 66), FlexSPI_D0_A/U13[5] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_07 (number 68), FlexSPI_D1_A/U13[2] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_08 (number 67), FlexSPI_D2_A/U13[3] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_11 (number 64), FlexSPI_D3_A/U13[7] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_06 (number 69), FlexSPI_SS0/U13[1] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/makerdiary_rt1011/clock_config.h b/ports/mimxrt10xx/boards/makerdiary_rt1011/clock_config.h deleted file mode 100644 index 76f3df422..000000000 --- a/ports/mimxrt10xx/boards/makerdiary_rt1011/clock_config.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL - -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/makerdiary_rt1011/flash_config.c b/ports/mimxrt10xx/boards/makerdiary_rt1011/flash_config.c index 2a5ace6c5..7ee525bf0 100644 --- a/ports/mimxrt10xx/boards/makerdiary_rt1011/flash_config.c +++ b/ports/mimxrt10xx/boards/makerdiary_rt1011/flash_config.c @@ -9,162 +9,114 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for W25Q128VPQ with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x200, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 4u, + .seqNum = 1u, }, + .deviceModeArg = 0x200, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/makerdiary_rt1011/makerdiary_rt1011.mex b/ports/mimxrt10xx/boards/makerdiary_rt1011/makerdiary_rt1011.mex new file mode 100644 index 000000000..723101922 --- /dev/null +++ b/ports/mimxrt10xx/boards/makerdiary_rt1011/makerdiary_rt1011.mex @@ -0,0 +1,543 @@ + + + + MIMXRT1011xxxxx + MIMXRT1011DAE5A + MIMXRT1010-EVK + A + ksdk2_0 + + + + + + + true + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 0.0.0 + + + + + + + + true + + + + + 2.5.0 + + + + + true + + + + + 2.0.1 + + + + + true + + + + + 2.0.3 + + + + + true + + + + + true + + + + + + 25.09.10 + + + + + + + + + 0 + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/board.cmake b/ports/mimxrt10xx/boards/metro_m7_1011/board.cmake index 975ddb0c7..4836ebdb4 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/board.cmake +++ b/ports/mimxrt10xx/boards/metro_m7_1011/board.cmake @@ -5,11 +5,8 @@ set(PYOCD_TARGET mimxrt1010) set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010) function(update_board TARGET) - target_sources(${TARGET} PRIVATE - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash_config.c - ) + target_compile_definitions(${TARGET} PUBLIC CPU_MIMXRT1011DAE5A ) -endfunction() +endfunction() diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/board.h b/ports/mimxrt10xx/boards/metro_m7_1011/board.h index 106437432..3285fd84e 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/board.h +++ b/ports/mimxrt10xx/boards/metro_m7_1011/board.h @@ -1,92 +1,89 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Ha Thach for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// Size of on-board external flash -#define BOARD_FLASH_SIZE (8*1024*1024) - -//--------------------------------------------------------------------+ -// LED -//--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_03_GPIOMUX_IO03 -#define LED_PORT GPIO1 -#define LED_PIN 3 -#define LED_STATE_ON 1 - -#define LED_PWM_PINMUX IOMUXC_GPIO_03_FLEXPWM1_PWM1_B -#define LED_PWM_BASE PWM1 -#define LED_PWM_MODULE kPWM_Module_1 -#define LED_PWM_CHANNEL kPWM_PwmB - -//--------------------------------------------------------------------+ -// Neopixel -//--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 1 -#define NEOPIXEL_PINMUX IOMUXC_GPIO_00_GPIOMUX_IO00 -#define NEOPIXEL_PORT GPIO1 -#define NEOPIXEL_PIN 0 - -//--------------------------------------------------------------------+ -// USB UF2 -//--------------------------------------------------------------------+ - -#define USB_VID 0x239A -#define USB_PID 0x00E1 -#define USB_MANUFACTURER "Adafruit" -#define USB_PRODUCT "Metro M7 iMX RT1011" - -#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT -#define UF2_BOARD_ID "MIMXRT1011-Metro-revA" -#define UF2_VOLUME_LABEL "METROM7BOOT" -#define UF2_INDEX_URL "https://www.adafruit.com/product/4950" - -//--------------------------------------------------------------------+ -// UART -//--------------------------------------------------------------------+ - -#define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_09_LPUART1_RXD -#define UART_TX_PINMUX IOMUXC_GPIO_10_LPUART1_TXD - -//--------------------------------------------------------------------+ -// ESP32 Co-Processors -//--------------------------------------------------------------------+ -#define ESP32_GPIO0_PINMUX IOMUXC_GPIO_SD_05_GPIO2_IO05 -#define ESP32_GPIO0_PORT GPIO2 -#define ESP32_GPIO0_PIN 5 - -#define ESP32_RESET_PINMUX IOMUXC_GPIO_AD_07_GPIOMUX_IO21 -#define ESP32_RESET_PORT GPIO1 -#define ESP32_RESET_PIN 21 - - -#endif /* BOARD_H_ */ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Ha Thach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Size of on-board external flash +#define BOARD_FLASH_SIZE (8*1024*1024) + +//--------------------------------------------------------------------+ +// LED +//--------------------------------------------------------------------+ +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL +#define LED_STATE_ON 1 + +#define LED_PWM_PINMUX IOMUXC_GPIO_03_FLEXPWM1_PWM1_B +#define LED_PWM_BASE PWM1 +#define LED_PWM_MODULE kPWM_Module_1 +#define LED_PWM_CHANNEL kPWM_PwmB + +//--------------------------------------------------------------------+ +// Neopixel +//--------------------------------------------------------------------+ + +// Number of neopixels +#define NEOPIXEL_NUMBER 1 +#define NEOPIXEL_PINMUX IOMUXC_GPIO_00_GPIOMUX_IO00 +#define NEOPIXEL_PORT BOARD_INITPINS_NEOPIXEL_PORT +#define NEOPIXEL_PIN BOARD_INITPINS_NEOPIXEL_PIN + +//--------------------------------------------------------------------+ +// USB UF2 +//--------------------------------------------------------------------+ +#define USB_VID 0x239A +#define USB_PID 0x00E1 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Metro M7 iMX RT1011" + +#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT +#define UF2_BOARD_ID "MIMXRT1011-Metro-revA" +#define UF2_VOLUME_LABEL "METROM7BOOT" +#define UF2_INDEX_URL "https://www.adafruit.com/product/4950" + +//--------------------------------------------------------------------+ +// UART +//--------------------------------------------------------------------+ + +#define UART_DEV LPUART1 +#define UART_RX_PINMUX IOMUXC_GPIO_09_LPUART1_RXD +#define UART_TX_PINMUX IOMUXC_GPIO_10_LPUART1_TXD + +//--------------------------------------------------------------------+ +// ESP32 Co-Processors +//--------------------------------------------------------------------+ +#define ESP32_GPIO0_PINMUX IOMUXC_GPIO_SD_05_GPIO2_IO05 +#define ESP32_GPIO0_PORT GPIO2 +#define ESP32_GPIO0_PIN 5 + +#define ESP32_RESET_PINMUX IOMUXC_GPIO_AD_07_GPIOMUX_IO21 +#define ESP32_RESET_PORT GPIO1 +#define ESP32_RESET_PIN 21 + + +#endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/imxrt1010_evk/clock_config.c b/ports/mimxrt10xx/boards/metro_m7_1011/board/clock_config.c similarity index 84% rename from ports/mimxrt10xx/boards/imxrt1010_evk/clock_config.c rename to ports/mimxrt10xx/boards/metro_m7_1011/board/clock_config.c index 178d62a84..76cb0a480 100644 --- a/ports/mimxrt10xx/boards/imxrt1010_evk/clock_config.c +++ b/ports/mimxrt10xx/boards/metro_m7_1011/board/clock_config.c @@ -1,10 +1,3 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* * How to setup clock using clock driver functions: * @@ -22,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v6.0 +product: Clocks v18.0 processor: MIMXRT1011xxxxx package_id: MIMXRT1011DAE5A mcu_data: ksdk2_0 -processor_version: 0.0.1 +processor_version: 25.09.10 board: MIMXRT1010-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -40,8 +33,6 @@ board: MIMXRT1010-EVK /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ @@ -82,21 +73,21 @@ called_from_default_init: true - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY_CLK.outFreq, value: 480 MHz} settings: - {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} - {id: CCM.AHB_PODF.scale, value: '1', locked: true} - {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} - {id: CCM.IPG_PODF.scale, value: '4'} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5'} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} - {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} - {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} - {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.div, value: '22'} - {id: CCM_ANALOG.PLL2.num, value: '0'} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} @@ -117,29 +108,33 @@ called_from_default_init: true - {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { - .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -161,22 +156,19 @@ void BOARD_BootClockRUN(void) CLOCK_SwitchOsc(kCLOCK_XtalOsc); /* Set Oscillator ready counter value. */ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */ + /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); /* Waiting for DCDC_STS_DC_OK bit is asserted */ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Disable IPG clock gate. */ CLOCK_DisableClock(kCLOCK_Adc1); CLOCK_DisableClock(kCLOCK_Xbar1); /* Set IPG_PODF. */ CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); /* Disable PERCLK clock gate. */ CLOCK_DisableClock(kCLOCK_Gpt1); CLOCK_DisableClock(kCLOCK_Gpt1S); @@ -186,9 +178,8 @@ void BOARD_BootClockRUN(void) /* Set PERCLK_PODF. */ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); @@ -212,9 +203,9 @@ void BOARD_BootClockRUN(void) /* Disable TRACE clock gate. */ CLOCK_DisableClock(kCLOCK_Trace); /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -263,22 +254,9 @@ void BOARD_BootClockRUN(void) CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); /* Set Flexio1 clock source. */ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Init Usb1 PLL. */ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); @@ -290,9 +268,28 @@ void BOARD_BootClockRUN(void) CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); /* Init Usb1 pfd3. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif + /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */ + /* Set Pll3 SW clock source to use the USB1 PLL output. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Set safe value of the AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 1); + /* Set periph clock2 clock source to use the PLL3_SW_CLK. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); /* Bypass Audio PLL. */ @@ -302,16 +299,14 @@ void BOARD_BootClockRUN(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); /* Set preperiph clock source. */ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ CLOCK_SetMux(kCLOCK_PeriphMux, 0); /* Set periph clock2 clock source. */ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Set clock out1 divider. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); /* Set clock out1 source. */ @@ -335,7 +330,7 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/board/clock_config.h b/ports/mimxrt10xx/boards/metro_m7_1011/board/clock_config.h new file mode 100644 index 000000000..cc627cf6a --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011/board/clock_config.h @@ -0,0 +1,97 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL /* Clock consumers of ADC_ALT_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL /* Clock consumers of CORE_CLK_ROOT output : ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AIPSTZ1, AIPSTZ2, AOI, ARM, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, OCOTP, PWM1, RTWDOG, SAI1, SAI3, SNVS, SPDIF, SRC, TEMPMON, TRNG, USB, WDOG1, WDOG2, XBARA */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */ + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/board/pin_mux.c b/ports/mimxrt10xx/boards/metro_m7_1011/board/pin_mux.c new file mode 100644 index 000000000..09ba40973 --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011/board/pin_mux.c @@ -0,0 +1,258 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1011xxxxx +package_id: MIMXRT1011DAE5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1010-EVK +external_user_signals: {} +pin_labels: +- {pin_num: '10', pin_signal: GPIO_03, label: 'SAI1_RXD0/U10[16]', identifier: USER_LED} +- {pin_num: '13', pin_signal: GPIO_00, label: 'AUD_INT/U10[15]', identifier: NEOPIXEL} +power_domains: {NVCC_GPIO: '3.3'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '57', peripheral: LPSPI1, signal: SDI, pin_signal: GPIO_AD_03} + - {pin_num: '56', peripheral: LPSPI1, signal: SDO, pin_signal: GPIO_AD_04} + - {pin_num: '52', peripheral: LPSPI1, signal: SCK, pin_signal: GPIO_AD_06} + - {pin_num: '60', peripheral: ARM, signal: 'TRACE, 0', pin_signal: GPIO_AD_00} + - {pin_num: '79', peripheral: ARM, signal: 'TRACE, 1', pin_signal: GPIO_13} + - {pin_num: '80', peripheral: ARM, signal: 'TRACE, 2', pin_signal: GPIO_12} + - {pin_num: '1', peripheral: ARM, signal: 'TRACE, 3', pin_signal: GPIO_11} + - {pin_num: '58', peripheral: ARM, signal: arm_trace_clk, pin_signal: GPIO_AD_02} + - {pin_num: '70', peripheral: GPIO2, signal: 'gpio_io, 05', pin_signal: GPIO_SD_05} + - {pin_num: '11', peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_02} + - {pin_num: '10', peripheral: GPIO1, signal: 'gpiomux_io, 03', pin_signal: GPIO_03, direction: OUTPUT} + - {pin_num: '13', peripheral: GPIO1, signal: 'gpiomux_io, 00', pin_signal: GPIO_00, direction: OUTPUT, slew_rate: Fast} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of NEOPIXEL on GPIO_00 (pin 13) */ + gpio_pin_config_t NEOPIXEL_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_00 (pin 13) */ + GPIO_PinInit(GPIO1, 0U, &NEOPIXEL_config); + + /* GPIO configuration of USER_LED on GPIO_03 (pin 10) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_03 (pin 10) */ + GPIO_PinInit(GPIO1, 3U, &USER_LED_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_00_GPIOMUX_IO00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_02_LPI2C1_SCL, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_03_GPIOMUX_IO03, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_03_LPSPI1_SDI, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_04_LPSPI1_SDO, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_06_LPSPI1_SCK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_00_GPIOMUX_IO00, 0x10A1U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09} + - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '65', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_10} + - {pin_num: '66', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_09} + - {pin_num: '68', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_07} + - {pin_num: '67', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_08} + - {pin_num: '64', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_11} + - {pin_num: '69', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_06} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '1', peripheral: GPIO1, signal: 'gpiomux_io, 11', pin_signal: GPIO_11, direction: OUTPUT, gpio_init_state: 'true', slew_rate: Slow, software_input_on: Disable, + open_drain: Disable, drive_strength: R0_4, pull_keeper_select: Keeper, pull_keeper_enable: Enable, pull_up_down_config: Pull_Down_100K_Ohm, hysteresis_enable: Disable} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitLEDPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of GPIO_11 on GPIO_11 (pin 1) */ + gpio_pin_config_t GPIO_11_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_11 (pin 1) */ + GPIO_PinInit(GPIO1, 11U, &GPIO_11_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITLEDPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_11_GPIOMUX_IO11, 0x10A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '70', peripheral: GPIO2, signal: 'gpio_io, 05', pin_signal: GPIO_SD_05, direction: INPUT, gpio_interrupt: kGPIO_NoIntmode, slew_rate: Slow, software_input_on: Disable, + open_drain: Disable, drive_strength: R0_4, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Enable} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitBUTTONPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of USER_BUTTON on GPIO_SD_05 (pin 70) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_SD_05 (pin 70) */ + GPIO_PinInit(GPIO2, 5U, &USER_BUTTON_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITBUTTONPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0x01B0A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitCOMBO_SENSORPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '11', peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_02, slew_rate: Slow, software_input_on: Enable, open_drain: Enable, drive_strength: R0_4, pull_keeper_select: Keeper, + pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_22K_Ohm, hysteresis_enable: Disable} + - {pin_num: '12', peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_01, slew_rate: Slow, software_input_on: Enable, open_drain: Enable, drive_strength: R0_4, pull_keeper_select: Keeper, + pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_22K_Ohm, hysteresis_enable: Disable} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitCOMBO_SENSORPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitCOMBO_SENSORPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_01_LPI2C1_SDA, 1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_02_LPI2C1_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_01_LPI2C1_SDA, 0xD8A0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_02_LPI2C1_SCL, 0xD8A0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/board/pin_mux.h b/ports/mimxrt10xx/boards/metro_m7_1011/board/pin_mux.h new file mode 100644 index 000000000..0b78406ae --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011/board/pin_mux.h @@ -0,0 +1,265 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x09U /*!< Select GPIO1 or GPIO2: affected bits mask */ + +/* GPIO_AD_03 (number 57), LPSPI1_SDI/J57[10]/U27[2] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LPSPI1_SDI_PERIPHERAL LPSPI1 /*!< Peripheral name */ +#define BOARD_INITPINS_LPSPI1_SDI_SIGNAL SDI /*!< Signal name */ + +/* GPIO_AD_04 (number 56), LPSPI1_SDO/J57[8]/U27[5] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LPSPI1_SDO_PERIPHERAL LPSPI1 /*!< Peripheral name */ +#define BOARD_INITPINS_LPSPI1_SDO_SIGNAL SDO /*!< Signal name */ + +/* GPIO_AD_06 (number 52), LPSPI1_SCK/INT2_COMBO/J56[8]/J57[12]/U26[9]/U27[6] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LPSPI1_SCK_PERIPHERAL LPSPI1 /*!< Peripheral name */ +#define BOARD_INITPINS_LPSPI1_SCK_SIGNAL SCK /*!< Signal name */ + +/* GPIO_AD_00 (number 60), USB_OTG1_PWR */ +/* Routed pin properties */ +#define BOARD_INITPINS_USB_OTG1_PWR_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_USB_OTG1_PWR_SIGNAL TRACE /*!< Signal name */ +#define BOARD_INITPINS_USB_OTG1_PWR_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_13 (number 79), USB_OTG1_ID/J9[4]/Q9[2] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USB_OTG1_ID_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_USB_OTG1_ID_SIGNAL TRACE /*!< Signal name */ +#define BOARD_INITPINS_USB_OTG1_ID_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_12 (number 80), USB_OTG1_OC/U7[A2] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USB_OTG1_OC_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_USB_OTG1_OC_SIGNAL TRACE /*!< Signal name */ +#define BOARD_INITPINS_USB_OTG1_OC_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_11 (number 1), GPIO_11 */ +/* Routed pin properties */ +#define BOARD_INITPINS_GPIO_11_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_GPIO_11_SIGNAL TRACE /*!< Signal name */ +#define BOARD_INITPINS_GPIO_11_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_AD_02 (number 58), ADC12_2/J26[12]/J56[16] */ +/* Routed pin properties */ +#define BOARD_INITPINS_ADC12_2_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_ADC12_2_SIGNAL arm_trace_clk /*!< Signal name */ + +/* GPIO_SD_05 (number 70), USER_BUTTON/SW4 */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 5U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 5U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 5U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 5U) /*!< PORT pin mask */ + +/* GPIO_02 (number 11), I2C1_SCL/U10[17]/J57[20]/U26[4] */ +/* Routed pin properties */ +#define BOARD_INITPINS_I2C1_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */ +#define BOARD_INITPINS_I2C1_SCL_SIGNAL SCL /*!< Signal name */ + +/* GPIO_03 (number 10), SAI1_RXD0/U10[16] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpiomux_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 3U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 3U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 3U) /*!< PORT pin mask */ + +/* GPIO_00 (number 13), AUD_INT/U10[15] */ +/* Routed pin properties */ +#define BOARD_INITPINS_NEOPIXEL_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_NEOPIXEL_SIGNAL gpiomux_io /*!< Signal name */ +#define BOARD_INITPINS_NEOPIXEL_CHANNEL 0U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_NEOPIXEL_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_NEOPIXEL_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_NEOPIXEL_GPIO_PIN 0U /*!< GPIO pin number */ +#define BOARD_INITPINS_NEOPIXEL_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_NEOPIXEL_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_NEOPIXEL_PIN 0U /*!< PORT pin number */ +#define BOARD_INITPINS_NEOPIXEL_PIN_MASK (1U << 0U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */ + +/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_10 (number 65), FlexSPI_CLK_A/U13[6] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_09 (number 66), FlexSPI_D0_A/U13[5] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_07 (number 68), FlexSPI_D1_A/U13[2] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_08 (number 67), FlexSPI_D2_A/U13[3] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_11 (number 64), FlexSPI_D3_A/U13[7] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_06 (number 69), FlexSPI_SS0/U13[1] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#define BOARD_INITLEDPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x0800U /*!< Select GPIO1 or GPIO2: affected bits mask */ + +/* GPIO_11 (number 1), GPIO_11 */ +/* Routed pin properties */ +#define BOARD_INITLEDPINS_GPIO_11_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITLEDPINS_GPIO_11_SIGNAL gpiomux_io /*!< Signal name */ +#define BOARD_INITLEDPINS_GPIO_11_CHANNEL 11U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDPINS_GPIO_11_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_GPIO_11_INIT_GPIO_VALUE 1U /*!< GPIO output initial state */ +#define BOARD_INITLEDPINS_GPIO_11_GPIO_PIN 11U /*!< GPIO pin number */ +#define BOARD_INITLEDPINS_GPIO_11_GPIO_PIN_MASK (1U << 11U) /*!< GPIO pin mask */ +#define BOARD_INITLEDPINS_GPIO_11_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITLEDPINS_GPIO_11_PIN 11U /*!< PORT pin number */ +#define BOARD_INITLEDPINS_GPIO_11_PIN_MASK (1U << 11U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDPins(void); + +#define BOARD_INITBUTTONPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x20U /*!< Select GPIO1 or GPIO2: affected bits mask */ + +/* GPIO_SD_05 (number 70), USER_BUTTON/SW4 */ +/* Routed pin properties */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_CHANNEL 5U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_GPIO_PIN 5U /*!< GPIO pin number */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_PIN 5U /*!< PORT pin number */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_PIN_MASK (1U << 5U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONPins(void); + +/* GPIO_02 (number 11), I2C1_SCL/U10[17]/J57[20]/U26[4] */ +/* Routed pin properties */ +#define BOARD_INITCOMBO_SENSORPINS_I2C1_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */ +#define BOARD_INITCOMBO_SENSORPINS_I2C1_SCL_SIGNAL SCL /*!< Signal name */ + +/* GPIO_01 (number 12), I2C1_SDA/U10[18]/J57[18]/U26[6] */ +/* Routed pin properties */ +#define BOARD_INITCOMBO_SENSORPINS_I2C1_SDA_PERIPHERAL LPI2C1 /*!< Peripheral name */ +#define BOARD_INITCOMBO_SENSORPINS_I2C1_SDA_SIGNAL SDA /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitCOMBO_SENSORPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/clock_config.h b/ports/mimxrt10xx/boards/metro_m7_1011/clock_config.h deleted file mode 100644 index 76f3df422..000000000 --- a/ports/mimxrt10xx/boards/metro_m7_1011/clock_config.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL - -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c index 5807090d8..30654cb97 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c +++ b/ports/mimxrt10xx/boards/metro_m7_1011/flash_config.c @@ -9,172 +9,122 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for W25Q64JVSIQ with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x0200, - .configCmdEnable = 1u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .configCmdSeqs[0] = { - .seqId = 2u, + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = + { + .seqId = 4u, .seqNum = 1u, }, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* command code */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* command code */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: Read Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* command code */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Read Status XPI ( DPI/QPI/OPI) i.e QE bit - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* command code */, - READ_SDR, FLEXSPI_1PAD, 1), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 3: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* command code */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Write Quad enabled i.e Write Status1 & Status2 - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* command code */, - WRITE_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* command code */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* command code */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program single mode - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* command code */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty Page program (Quad mode) candidate - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* command code */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 2u, + .seqNum = 1u, }, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* command code */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* command code */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: Read Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* command code */, READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Read Status XPI ( DPI/QPI/OPI) i.e QE bit + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* command code */, READ_SDR, FLEXSPI_1PAD, 1), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 3: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* command code */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Write Quad enabled i.e Write Status1 & Status2 + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* command code */, WRITE_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* command code */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* command code */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program single mode + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* command code */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty Page program (Quad mode) candidate + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* command code */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/metro_m7_1011/metro_m7_1011.mex b/ports/mimxrt10xx/boards/metro_m7_1011/metro_m7_1011.mex index 606ec2cfc..6bd5289a5 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011/metro_m7_1011.mex +++ b/ports/mimxrt10xx/boards/metro_m7_1011/metro_m7_1011.mex @@ -1,5 +1,5 @@ - + MIMXRT1011xxxxx MIMXRT1011DAE5A @@ -13,19 +13,23 @@ true - false false true + true false - + - 13.0.2 + 25.09.10 + + + + @@ -42,17 +46,17 @@ true - + true - + true - + true @@ -67,6 +71,11 @@ true + + + true + + @@ -79,17 +88,28 @@ + + + + + + + + + + + Configures pin routing and optionally pin electrical features. - true + false core0 true - + true @@ -118,7 +138,7 @@ true - + true @@ -192,7 +212,7 @@ true - + true @@ -238,7 +258,7 @@ true - + true @@ -283,13 +303,13 @@ - + - 13.0.2 + 25.09.10 @@ -425,45 +445,52 @@ - + - + true - - - 2.5.1 + + + 2.5.0 - + true - + 2.0.1 - + true - + - 2.0.3 + 2.0.3 + + + + + true + + + + + true - - - - + - 13.0.2 + 25.09.10 @@ -507,7 +534,7 @@ - + @@ -555,7 +582,7 @@ - + @@ -582,7 +609,7 @@ - + @@ -594,7 +621,7 @@ - + @@ -614,13 +641,13 @@ - + - + @@ -638,6 +665,7 @@ + @@ -660,6 +688,7 @@ + diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/board.cmake b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board.cmake index 975ddb0c7..4836ebdb4 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011_sd/board.cmake +++ b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board.cmake @@ -5,11 +5,8 @@ set(PYOCD_TARGET mimxrt1010) set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010) function(update_board TARGET) - target_sources(${TARGET} PRIVATE - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash_config.c - ) + target_compile_definitions(${TARGET} PUBLIC CPU_MIMXRT1011DAE5A ) -endfunction() +endfunction() diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/board.h b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board.h index 29e175bc0..ea6aaf3d1 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011_sd/board.h +++ b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board.h @@ -1,81 +1,81 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Ha Thach for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// Size of on-board external flash -#define BOARD_FLASH_SIZE (8*1024*1024) - -//--------------------------------------------------------------------+ -// LED -//--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_03_GPIOMUX_IO03 -#define LED_PORT GPIO1 -#define LED_PIN 3 -#define LED_STATE_ON 1 - -#define LED_PWM_PINMUX IOMUXC_GPIO_03_FLEXPWM1_PWM1_B -#define LED_PWM_BASE PWM1 -#define LED_PWM_MODULE kPWM_Module_1 -#define LED_PWM_CHANNEL kPWM_PwmB - -//--------------------------------------------------------------------+ -// Neopixel -//--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 1 -#define NEOPIXEL_PINMUX IOMUXC_GPIO_00_GPIOMUX_IO00 -#define NEOPIXEL_PORT GPIO1 -#define NEOPIXEL_PIN 0 - -//--------------------------------------------------------------------+ -// USB UF2 -//--------------------------------------------------------------------+ - -#define USB_VID 0x239A -#define USB_PID 0x0141 -#define USB_MANUFACTURER "Adafruit" -#define USB_PRODUCT "Metro M7 iMX RT1011 SD" - -#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT -#define UF2_BOARD_ID "MIMXRT1011-Metro-SD-revA" -#define UF2_VOLUME_LABEL "METROM7BOOT" -#define UF2_INDEX_URL "https://www.adafruit.com/product/4950" // TODO change to correct PID later - -//--------------------------------------------------------------------+ -// UART -//--------------------------------------------------------------------+ - -#define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_09_LPUART1_RXD -#define UART_TX_PINMUX IOMUXC_GPIO_10_LPUART1_TXD - - -#endif /* BOARD_H_ */ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Ha Thach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Size of on-board external flash +#define BOARD_FLASH_SIZE (8*1024*1024) + +//--------------------------------------------------------------------+ +// LED +//--------------------------------------------------------------------+ + +#define LED_PINMUX IOMUXC_GPIO_03_GPIOMUX_IO03 +#define LED_PORT GPIO1 +#define LED_PIN 3 +#define LED_STATE_ON 1 + +#define LED_PWM_PINMUX IOMUXC_GPIO_03_FLEXPWM1_PWM1_B +#define LED_PWM_BASE PWM1 +#define LED_PWM_MODULE kPWM_Module_1 +#define LED_PWM_CHANNEL kPWM_PwmB + +//--------------------------------------------------------------------+ +// Neopixel +//--------------------------------------------------------------------+ + +// Number of neopixels +#define NEOPIXEL_NUMBER 1 +#define NEOPIXEL_PINMUX IOMUXC_GPIO_00_GPIOMUX_IO00 +#define NEOPIXEL_PORT GPIO1 +#define NEOPIXEL_PIN 0 + +//--------------------------------------------------------------------+ +// USB UF2 +//--------------------------------------------------------------------+ + +#define USB_VID 0x239A +#define USB_PID 0x0141 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Metro M7 iMX RT1011 SD" + +#define UF2_PRODUCT_NAME USB_MANUFACTURER " " USB_PRODUCT +#define UF2_BOARD_ID "MIMXRT1011-Metro-SD-revA" +#define UF2_VOLUME_LABEL "METROM7BOOT" +#define UF2_INDEX_URL "https://www.adafruit.com/product/4950" // TODO change to correct PID later + +//--------------------------------------------------------------------+ +// UART +//--------------------------------------------------------------------+ + +#define UART_DEV LPUART1 +#define UART_RX_PINMUX IOMUXC_GPIO_09_LPUART1_RXD +#define UART_TX_PINMUX IOMUXC_GPIO_10_LPUART1_TXD + + +#endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/clock_config.c b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/clock_config.c new file mode 100644 index 000000000..76cb0a480 --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/clock_config.c @@ -0,0 +1,340 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: MIMXRT1011xxxxx +package_id: MIMXRT1011DAE5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1010-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ADC_ALT_CLK.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz} +- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY_CLK.outFreq, value: 480 MHz} +settings: +- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} +- {id: CCM.IPG_PODF.scale, value: '4'} +- {id: CCM.LPSPI_PODF.scale, value: '5'} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} +- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} +- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM_ANALOG.PLL2.denom, value: '1'} +- {id: CCM_ANALOG.PLL2.num, value: '0'} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Xbar1); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0); + CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0); +#endif + /* Disable ADC_ACLK_EN clock gate. */ + CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK; + /* Set ADC_ACLK_PODF. */ + CLOCK_SetDiv(kCLOCK_AdcDiv, 11); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); +#endif + /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */ + /* Set Pll3 SW clock source to use the USB1 PLL output. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Set safe value of the AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 1); + /* Set periph clock2 clock source to use the PLL3_SW_CLK. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/clock_config.h b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/clock_config.h new file mode 100644 index 000000000..cc627cf6a --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/clock_config.h @@ -0,0 +1,97 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL /* Clock consumers of ADC_ALT_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL /* Clock consumers of CORE_CLK_ROOT output : ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AIPSTZ1, AIPSTZ2, AOI, ARM, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, OCOTP, PWM1, RTWDOG, SAI1, SAI3, SNVS, SPDIF, SRC, TEMPMON, TRNG, USB, WDOG1, WDOG2, XBARA */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */ + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/pin_mux.c b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/pin_mux.c new file mode 100644 index 000000000..e11126e68 --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/pin_mux.c @@ -0,0 +1,256 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1011xxxxx +package_id: MIMXRT1011DAE5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1010-EVK +external_user_signals: {} +pin_labels: +- {pin_num: '10', pin_signal: GPIO_03, label: 'SAI1_RXD0/U10[16]', identifier: USER_LED} +- {pin_num: '13', pin_signal: GPIO_00, label: 'AUD_INT/U10[15]', identifier: NEOPIXEL} +power_domains: {NVCC_GPIO: '3.3'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '57', peripheral: LPSPI1, signal: SDI, pin_signal: GPIO_AD_03} + - {pin_num: '56', peripheral: LPSPI1, signal: SDO, pin_signal: GPIO_AD_04} + - {pin_num: '52', peripheral: LPSPI1, signal: SCK, pin_signal: GPIO_AD_06} + - {pin_num: '60', peripheral: ARM, signal: 'TRACE, 0', pin_signal: GPIO_AD_00} + - {pin_num: '79', peripheral: ARM, signal: 'TRACE, 1', pin_signal: GPIO_13} + - {pin_num: '80', peripheral: ARM, signal: 'TRACE, 2', pin_signal: GPIO_12} + - {pin_num: '1', peripheral: ARM, signal: 'TRACE, 3', pin_signal: GPIO_11} + - {pin_num: '58', peripheral: ARM, signal: arm_trace_clk, pin_signal: GPIO_AD_02} + - {pin_num: '11', peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_02} + - {pin_num: '10', peripheral: GPIO1, signal: 'gpiomux_io, 03', pin_signal: GPIO_03, direction: OUTPUT} + - {pin_num: '13', peripheral: GPIO1, signal: 'gpiomux_io, 00', pin_signal: GPIO_00, direction: OUTPUT, slew_rate: Fast} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of NEOPIXEL on GPIO_00 (pin 13) */ + gpio_pin_config_t NEOPIXEL_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_00 (pin 13) */ + GPIO_PinInit(GPIO1, 0U, &NEOPIXEL_config); + + /* GPIO configuration of USER_LED on GPIO_03 (pin 10) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_03 (pin 10) */ + GPIO_PinInit(GPIO1, 3U, &USER_LED_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_00_GPIOMUX_IO00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_02_LPI2C1_SCL, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_03_GPIOMUX_IO03, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_03_LPSPI1_SDI, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_04_LPSPI1_SDO, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_06_LPSPI1_SCK, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_00_GPIOMUX_IO00, 0x10A1U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09} + - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '65', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_10} + - {pin_num: '66', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_09} + - {pin_num: '68', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_07} + - {pin_num: '67', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_08} + - {pin_num: '64', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_11} + - {pin_num: '69', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_06} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '1', peripheral: GPIO1, signal: 'gpiomux_io, 11', pin_signal: GPIO_11, direction: OUTPUT, gpio_init_state: 'true', slew_rate: Slow, software_input_on: Disable, + open_drain: Disable, drive_strength: R0_4, pull_keeper_select: Keeper, pull_keeper_enable: Enable, pull_up_down_config: Pull_Down_100K_Ohm, hysteresis_enable: Disable} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitLEDPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of GPIO_11 on GPIO_11 (pin 1) */ + gpio_pin_config_t GPIO_11_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 1U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_11 (pin 1) */ + GPIO_PinInit(GPIO1, 11U, &GPIO_11_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITLEDPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_11_GPIOMUX_IO11, 0x10A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '70', peripheral: GPIO2, signal: 'gpio_io, 05', pin_signal: GPIO_SD_05, direction: INPUT, gpio_interrupt: kGPIO_NoIntmode, slew_rate: Slow, software_input_on: Disable, + open_drain: Disable, drive_strength: R0_4, pull_keeper_select: Pull, pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, hysteresis_enable: Enable} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitBUTTONPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of USER_BUTTON on GPIO_SD_05 (pin 70) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_SD_05 (pin 70) */ + GPIO_PinInit(GPIO2, 5U, &USER_BUTTON_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0U); + IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 & + (~(BOARD_INITBUTTONPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR26_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0x01B0A0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitCOMBO_SENSORPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '11', peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_02, slew_rate: Slow, software_input_on: Enable, open_drain: Enable, drive_strength: R0_4, pull_keeper_select: Keeper, + pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_22K_Ohm, hysteresis_enable: Disable} + - {pin_num: '12', peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_01, slew_rate: Slow, software_input_on: Enable, open_drain: Enable, drive_strength: R0_4, pull_keeper_select: Keeper, + pull_keeper_enable: Enable, pull_up_down_config: Pull_Up_22K_Ohm, hysteresis_enable: Disable} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitCOMBO_SENSORPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitCOMBO_SENSORPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_01_LPI2C1_SDA, 1U); + IOMUXC_SetPinMux(IOMUXC_GPIO_02_LPI2C1_SCL, 1U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_01_LPI2C1_SDA, 0xD8A0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_02_LPI2C1_SCL, 0xD8A0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/pin_mux.h b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/pin_mux.h new file mode 100644 index 000000000..26bfdaca2 --- /dev/null +++ b/ports/mimxrt10xx/boards/metro_m7_1011_sd/board/pin_mux.h @@ -0,0 +1,251 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x09U /*!< Select GPIO1 or GPIO2: affected bits mask */ + +/* GPIO_AD_03 (number 57), LPSPI1_SDI/J57[10]/U27[2] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LPSPI1_SDI_PERIPHERAL LPSPI1 /*!< Peripheral name */ +#define BOARD_INITPINS_LPSPI1_SDI_SIGNAL SDI /*!< Signal name */ + +/* GPIO_AD_04 (number 56), LPSPI1_SDO/J57[8]/U27[5] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LPSPI1_SDO_PERIPHERAL LPSPI1 /*!< Peripheral name */ +#define BOARD_INITPINS_LPSPI1_SDO_SIGNAL SDO /*!< Signal name */ + +/* GPIO_AD_06 (number 52), LPSPI1_SCK/INT2_COMBO/J56[8]/J57[12]/U26[9]/U27[6] */ +/* Routed pin properties */ +#define BOARD_INITPINS_LPSPI1_SCK_PERIPHERAL LPSPI1 /*!< Peripheral name */ +#define BOARD_INITPINS_LPSPI1_SCK_SIGNAL SCK /*!< Signal name */ + +/* GPIO_AD_00 (number 60), USB_OTG1_PWR */ +/* Routed pin properties */ +#define BOARD_INITPINS_USB_OTG1_PWR_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_USB_OTG1_PWR_SIGNAL TRACE /*!< Signal name */ +#define BOARD_INITPINS_USB_OTG1_PWR_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_13 (number 79), USB_OTG1_ID/J9[4]/Q9[2] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USB_OTG1_ID_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_USB_OTG1_ID_SIGNAL TRACE /*!< Signal name */ +#define BOARD_INITPINS_USB_OTG1_ID_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_12 (number 80), USB_OTG1_OC/U7[A2] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USB_OTG1_OC_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_USB_OTG1_OC_SIGNAL TRACE /*!< Signal name */ +#define BOARD_INITPINS_USB_OTG1_OC_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_11 (number 1), GPIO_11 */ +/* Routed pin properties */ +#define BOARD_INITPINS_GPIO_11_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_GPIO_11_SIGNAL TRACE /*!< Signal name */ +#define BOARD_INITPINS_GPIO_11_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_AD_02 (number 58), ADC12_2/J26[12]/J56[16] */ +/* Routed pin properties */ +#define BOARD_INITPINS_ADC12_2_PERIPHERAL ARM /*!< Peripheral name */ +#define BOARD_INITPINS_ADC12_2_SIGNAL arm_trace_clk /*!< Signal name */ + +/* GPIO_02 (number 11), I2C1_SCL/U10[17]/J57[20]/U26[4] */ +/* Routed pin properties */ +#define BOARD_INITPINS_I2C1_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */ +#define BOARD_INITPINS_I2C1_SCL_SIGNAL SCL /*!< Signal name */ + +/* GPIO_03 (number 10), SAI1_RXD0/U10[16] */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpiomux_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 3U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 3U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 3U) /*!< PORT pin mask */ + +/* GPIO_00 (number 13), AUD_INT/U10[15] */ +/* Routed pin properties */ +#define BOARD_INITPINS_NEOPIXEL_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_NEOPIXEL_SIGNAL gpiomux_io /*!< Signal name */ +#define BOARD_INITPINS_NEOPIXEL_CHANNEL 0U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_NEOPIXEL_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_NEOPIXEL_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_NEOPIXEL_GPIO_PIN 0U /*!< GPIO pin number */ +#define BOARD_INITPINS_NEOPIXEL_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_NEOPIXEL_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_NEOPIXEL_PIN 0U /*!< PORT pin number */ +#define BOARD_INITPINS_NEOPIXEL_PIN_MASK (1U << 0U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */ + +/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_10 (number 65), FlexSPI_CLK_A/U13[6] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_09 (number 66), FlexSPI_D0_A/U13[5] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_07 (number 68), FlexSPI_D1_A/U13[2] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_08 (number 67), FlexSPI_D2_A/U13[3] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_11 (number 64), FlexSPI_D3_A/U13[7] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_06 (number 69), FlexSPI_SS0/U13[1] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#define BOARD_INITLEDPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x0800U /*!< Select GPIO1 or GPIO2: affected bits mask */ + +/* GPIO_11 (number 1), GPIO_11 */ +/* Routed pin properties */ +#define BOARD_INITLEDPINS_GPIO_11_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITLEDPINS_GPIO_11_SIGNAL gpiomux_io /*!< Signal name */ +#define BOARD_INITLEDPINS_GPIO_11_CHANNEL 11U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDPINS_GPIO_11_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITLEDPINS_GPIO_11_INIT_GPIO_VALUE 1U /*!< GPIO output initial state */ +#define BOARD_INITLEDPINS_GPIO_11_GPIO_PIN 11U /*!< GPIO pin number */ +#define BOARD_INITLEDPINS_GPIO_11_GPIO_PIN_MASK (1U << 11U) /*!< GPIO pin mask */ +#define BOARD_INITLEDPINS_GPIO_11_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITLEDPINS_GPIO_11_PIN 11U /*!< PORT pin number */ +#define BOARD_INITLEDPINS_GPIO_11_PIN_MASK (1U << 11U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDPins(void); + +#define BOARD_INITBUTTONPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x20U /*!< Select GPIO1 or GPIO2: affected bits mask */ + +/* GPIO_SD_05 (number 70), USER_BUTTON/SW4 */ +/* Routed pin properties */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_CHANNEL 5U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_GPIO_PIN 5U /*!< GPIO pin number */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_PIN 5U /*!< PORT pin number */ +#define BOARD_INITBUTTONPINS_USER_BUTTON_PIN_MASK (1U << 5U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONPins(void); + +/* GPIO_02 (number 11), I2C1_SCL/U10[17]/J57[20]/U26[4] */ +/* Routed pin properties */ +#define BOARD_INITCOMBO_SENSORPINS_I2C1_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */ +#define BOARD_INITCOMBO_SENSORPINS_I2C1_SCL_SIGNAL SCL /*!< Signal name */ + +/* GPIO_01 (number 12), I2C1_SDA/U10[18]/J57[18]/U26[6] */ +/* Routed pin properties */ +#define BOARD_INITCOMBO_SENSORPINS_I2C1_SDA_PERIPHERAL LPI2C1 /*!< Peripheral name */ +#define BOARD_INITCOMBO_SENSORPINS_I2C1_SDA_SIGNAL SDA /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitCOMBO_SENSORPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/clock_config.c b/ports/mimxrt10xx/boards/metro_m7_1011_sd/clock_config.c deleted file mode 100644 index 178d62a84..000000000 --- a/ports/mimxrt10xx/boards/metro_m7_1011_sd/clock_config.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. - * - * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. - * - * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v6.0 -processor: MIMXRT1011xxxxx -package_id: MIMXRT1011DAE5A -mcu_data: ksdk2_0 -processor_version: 0.0.1 -board: MIMXRT1010-EVK - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "clock_config.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: ADC_ALT_CLK.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz} -- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -settings: -- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} -- {id: CCM.IPG_PODF.scale, value: '4'} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} -- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.div, value: '22'} -- {id: CCM_ANALOG.PLL2.num, value: '0'} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { - .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Xbar1); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); - CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0); -#endif - /* Disable ADC_ACLK_EN clock gate. */ - CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK; - /* Set ADC_ACLK_PODF. */ - CLOCK_SetDiv(kCLOCK_AdcDiv, 11); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/clock_config.h b/ports/mimxrt10xx/boards/metro_m7_1011_sd/clock_config.h deleted file mode 100644 index 76f3df422..000000000 --- a/ports/mimxrt10xx/boards/metro_m7_1011_sd/clock_config.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL - -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/flash_config.c b/ports/mimxrt10xx/boards/metro_m7_1011_sd/flash_config.c index 5807090d8..30654cb97 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011_sd/flash_config.c +++ b/ports/mimxrt10xx/boards/metro_m7_1011_sd/flash_config.c @@ -9,172 +9,122 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for W25Q64JVSIQ with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x0200, - .configCmdEnable = 1u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .configCmdSeqs[0] = { - .seqId = 2u, + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = + { + .seqId = 4u, .seqNum = 1u, }, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .deviceModeArg = 0x0200, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* command code */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* command code */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: Read Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* command code */, - READ_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Read Status XPI ( DPI/QPI/OPI) i.e QE bit - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* command code */, - READ_SDR, FLEXSPI_1PAD, 1), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 3: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* command code */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Write Quad enabled i.e Write Status1 & Status2 - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* command code */, - WRITE_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* command code */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* command code */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program single mode - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* command code */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty Page program (Quad mode) candidate - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* command code */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 2u, + .seqNum = 1u, }, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* command code */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* command code */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: Read Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* command code */, READ_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Read Status XPI ( DPI/QPI/OPI) i.e QE bit + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35 /* command code */, READ_SDR, FLEXSPI_1PAD, 1), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 3: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* command code */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Write Quad enabled i.e Write Status1 & Status2 + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* command code */, WRITE_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* command code */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* command code */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program single mode + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* command code */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty Page program (Quad mode) candidate + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* command code */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex b/ports/mimxrt10xx/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex index 606ec2cfc..fd5e46666 100644 --- a/ports/mimxrt10xx/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex +++ b/ports/mimxrt10xx/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex @@ -1,5 +1,5 @@ - + MIMXRT1011xxxxx MIMXRT1011DAE5A @@ -13,19 +13,23 @@ true - false false true + true false - + - 13.0.2 + 25.09.10 + + + + @@ -42,17 +46,17 @@ true - + true - + true - + true @@ -67,6 +71,11 @@ true + + + true + + @@ -77,19 +86,29 @@ - + + + + + + + + + + + Configures pin routing and optionally pin electrical features. - true + false core0 true - + true @@ -118,7 +137,7 @@ true - + true @@ -192,7 +211,7 @@ true - + true @@ -238,7 +257,7 @@ true - + true @@ -283,13 +302,13 @@ - + - 13.0.2 + 25.09.10 @@ -425,45 +444,52 @@ - + - + true - - - 2.5.1 + + + 2.5.0 - + true - + 2.0.1 - + true - + - 2.0.3 + 2.0.3 + + + + + true + + + + + true - - - - + - 13.0.2 + 25.09.10 @@ -507,7 +533,7 @@ - + @@ -555,7 +581,7 @@ - + @@ -582,7 +608,7 @@ - + @@ -594,7 +620,7 @@ - + @@ -614,13 +640,13 @@ - + - + @@ -638,6 +664,7 @@ + @@ -660,6 +687,7 @@ + diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/board.cmake b/ports/mimxrt10xx/boards/olimex_rt1010/board.cmake new file mode 100644 index 000000000..ec823c0e3 --- /dev/null +++ b/ports/mimxrt10xx/boards/olimex_rt1010/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT MIMXRT1011) + +set(JLINK_DEVICE MIMXRT1011DAE5A) +set(PYOCD_TARGET mimxrt1010) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1011DAE5A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/board.h b/ports/mimxrt10xx/boards/olimex_rt1010/board.h index f01ab7450..ffa6ebb48 100644 --- a/ports/mimxrt10xx/boards/olimex_rt1010/board.h +++ b/ports/mimxrt10xx/boards/olimex_rt1010/board.h @@ -34,50 +34,18 @@ //--------------------------------------------------------------------+ // LED //--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_11_GPIOMUX_IO11 -#define LED_PORT GPIO1 -#define LED_PIN 11 +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL #define LED_STATE_ON 1 -#if 0 -// PWM Test on Arduino header D8 -#define LED_PWM_PINMUX IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A -#define LED_PWM_BASE PWM1 -#define LED_PWM_MODULE kPWM_Module_0 -#define LED_PWM_CHANNEL kPWM_PwmA -#endif - //--------------------------------------------------------------------+ // Neopixel //--------------------------------------------------------------------+ - -// Number of neopixels -#if 1 -#define NEOPIXEL_NUMBER 0 - -#else -// Neopixel Test on Arduino header A0 -#define NEOPIXEL_NUMBER 1 -#define NEOPIXEL_PINMUX IOMUXC_GPIO_AD_07_GPIOMUX_IO21 -#define NEOPIXEL_PORT GPIO1 -#define NEOPIXEL_PIN 21 -#endif - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// SW8 button -#define BUTTON_PINMUX IOMUXC_GPIO_SD_05_GPIO2_IO05 -#define BUTTON_PORT GPIO2 -#define BUTTON_PIN 5 -#define BUTTON_STATE_ACTIVE 0 +#define NEOPIXEL_NUMBER 0 // Number of neopixels //--------------------------------------------------------------------+ // USB UF2 //--------------------------------------------------------------------+ - #define USB_VID 0x15ba #define USB_PID 0x0046 #define USB_MANUFACTURER "Olimex" @@ -91,9 +59,6 @@ //--------------------------------------------------------------------+ // UART //--------------------------------------------------------------------+ - #define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_09_LPUART1_RXD -#define UART_TX_PINMUX IOMUXC_GPIO_10_LPUART1_TXD #endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/board/clock_config.c b/ports/mimxrt10xx/boards/olimex_rt1010/board/clock_config.c new file mode 100644 index 000000000..76cb0a480 --- /dev/null +++ b/ports/mimxrt10xx/boards/olimex_rt1010/board/clock_config.c @@ -0,0 +1,340 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: MIMXRT1011xxxxx +package_id: MIMXRT1011DAE5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1010-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ADC_ALT_CLK.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz} +- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY_CLK.outFreq, value: 480 MHz} +settings: +- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} +- {id: CCM.IPG_PODF.scale, value: '4'} +- {id: CCM.LPSPI_PODF.scale, value: '5'} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} +- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} +- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM_ANALOG.PLL2.denom, value: '1'} +- {id: CCM_ANALOG.PLL2.num, value: '0'} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Xbar1); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0); + CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0); +#endif + /* Disable ADC_ACLK_EN clock gate. */ + CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK; + /* Set ADC_ACLK_PODF. */ + CLOCK_SetDiv(kCLOCK_AdcDiv, 11); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); +#endif + /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */ + /* Set Pll3 SW clock source to use the USB1 PLL output. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Set safe value of the AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 1); + /* Set periph clock2 clock source to use the PLL3_SW_CLK. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/board/clock_config.h b/ports/mimxrt10xx/boards/olimex_rt1010/board/clock_config.h new file mode 100644 index 000000000..cc627cf6a --- /dev/null +++ b/ports/mimxrt10xx/boards/olimex_rt1010/board/clock_config.h @@ -0,0 +1,97 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL /* Clock consumers of ADC_ALT_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL /* Clock consumers of CORE_CLK_ROOT output : ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AIPSTZ1, AIPSTZ2, AOI, ARM, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, OCOTP, PWM1, RTWDOG, SAI1, SAI3, SNVS, SPDIF, SRC, TEMPMON, TRNG, USB, WDOG1, WDOG2, XBARA */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */ + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/board/pin_mux.c b/ports/mimxrt10xx/boards/olimex_rt1010/board/pin_mux.c new file mode 100644 index 000000000..18c0d6cd4 --- /dev/null +++ b/ports/mimxrt10xx/boards/olimex_rt1010/board/pin_mux.c @@ -0,0 +1,112 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1011xxxxx +package_id: MIMXRT1011DAE5A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1010-EVK +external_user_signals: {} +pin_labels: +- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: USER_LED} +power_domains: {NVCC_GPIO: '3.3'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '1', peripheral: GPIO1, signal: 'gpiomux_io, 11', pin_signal: GPIO_11} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09} + - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '65', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_10} + - {pin_num: '66', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_09} + - {pin_num: '68', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_07} + - {pin_num: '67', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_08} + - {pin_num: '64', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_11} + - {pin_num: '69', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_06} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3, 0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/board/pin_mux.h b/ports/mimxrt10xx/boards/olimex_rt1010/board/pin_mux.h new file mode 100644 index 000000000..e250c81ca --- /dev/null +++ b/ports/mimxrt10xx/boards/olimex_rt1010/board/pin_mux.h @@ -0,0 +1,123 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/* GPIO_11 (number 1), GPIO_11 */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpiomux_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 11U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 11U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 11U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 11U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 11U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */ + +/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_10 (number 65), FlexSPI_CLK_A/U13[6] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_09 (number 66), FlexSPI_D0_A/U13[5] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_07 (number 68), FlexSPI_D1_A/U13[2] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_08 (number 67), FlexSPI_D2_A/U13[3] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_11 (number 64), FlexSPI_D3_A/U13[7] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_06 (number 69), FlexSPI_SS0/U13[1] */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/clock_config.c b/ports/mimxrt10xx/boards/olimex_rt1010/clock_config.c deleted file mode 100644 index 178d62a84..000000000 --- a/ports/mimxrt10xx/boards/olimex_rt1010/clock_config.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. - * - * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. - * - * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v6.0 -processor: MIMXRT1011xxxxx -package_id: MIMXRT1011DAE5A -mcu_data: ksdk2_0 -processor_version: 0.0.1 -board: MIMXRT1010-EVK - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "clock_config.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: ADC_ALT_CLK.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz} -- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -settings: -- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} -- {id: CCM.IPG_PODF.scale, value: '4'} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} -- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1'} -- {id: CCM_ANALOG.PLL2.div, value: '22'} -- {id: CCM_ANALOG.PLL2.num, value: '0'} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = { - .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Xbar1); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 0); - CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0); -#endif - /* Disable ADC_ACLK_EN clock gate. */ - CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK; - /* Set ADC_ACLK_PODF. */ - CLOCK_SetDiv(kCLOCK_AdcDiv, 11); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/clock_config.h b/ports/mimxrt10xx/boards/olimex_rt1010/clock_config.h deleted file mode 100644 index 76f3df422..000000000 --- a/ports/mimxrt10xx/boards/olimex_rt1010/clock_config.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL - -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/flash_config.c b/ports/mimxrt10xx/boards/olimex_rt1010/flash_config.c index 386483ca1..c9b5b153f 100644 --- a/ports/mimxrt10xx/boards/olimex_rt1010/flash_config.c +++ b/ports/mimxrt10xx/boards/olimex_rt1010/flash_config.c @@ -9,162 +9,114 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for EN25Q16B-104HIP with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 1u, - .deviceModeType = kDeviceConfigCmdType_QuadEnable, - .deviceModeSeq = { - .seqId = 4u, - .seqNum = 1u, - }, - .deviceModeArg = 0x40, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = FLASH_SIZE, - .lookupTable = + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 1u, + .deviceModeType = kDeviceConfigCmdType_QuadEnable, + .deviceModeSeq = { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x02), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - EMPTY_SEQUENCE, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, - WRITE_SDR, FLEXSPI_1PAD, 0x01), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE + .seqId = 4u, + .seqNum = 1u, }, + .deviceModeArg = 0x40, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x02), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + EMPTY_SEQUENCE, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01 /* the command to send */, WRITE_SDR, FLEXSPI_1PAD, 0x01), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/olimex_rt1010/olimex_rt1010.mex b/ports/mimxrt10xx/boards/olimex_rt1010/olimex_rt1010.mex new file mode 100644 index 000000000..66db400ab --- /dev/null +++ b/ports/mimxrt10xx/boards/olimex_rt1010/olimex_rt1010.mex @@ -0,0 +1,542 @@ + + + + MIMXRT1011xxxxx + MIMXRT1011DAE5A + MIMXRT1010-EVK + A + ksdk2_0 + + + + + + + true + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 0.0.0 + + + + + + + + true + + + + + 2.5.0 + + + + + true + + + + + 2.0.1 + + + + + true + + + + + 2.0.3 + + + + + true + + + + + true + + + + + + 25.09.10 + + + + + + + + + 0 + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + diff --git a/ports/mimxrt10xx/boards/teensy40/board.cmake b/ports/mimxrt10xx/boards/teensy40/board.cmake new file mode 100644 index 000000000..2fe422775 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy40/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT MIMXRT1062) + +set(PYOCD_TARGET mimxrt1060) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1062DVL6A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/teensy40/board.h b/ports/mimxrt10xx/boards/teensy40/board.h index eeb9f0148..5efa6fa86 100644 --- a/ports/mimxrt10xx/boards/teensy40/board.h +++ b/ports/mimxrt10xx/boards/teensy40/board.h @@ -34,33 +34,18 @@ //--------------------------------------------------------------------+ // LED //--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_B0_03_GPIO2_IO03 -#define LED_PORT GPIO2 -#define LED_PIN 3 +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL #define LED_STATE_ON 0 //--------------------------------------------------------------------+ // Neopixel //--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 0 - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// Teensy 4.1 pin 23. -#define BUTTON_PINMUX IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 -#define BUTTON_PORT GPIO1 -#define BUTTON_PIN 25 -#define BUTTON_STATE_ACTIVE 0 +#define NEOPIXEL_NUMBER 0 // Number of neopixels //--------------------------------------------------------------------+ // USB UF2 //--------------------------------------------------------------------+ - #define USB_VID 0x239A #define USB_PID 0x0085 #define USB_MANUFACTURER "PJRC" @@ -74,9 +59,6 @@ //--------------------------------------------------------------------+ // UART //--------------------------------------------------------------------+ - #define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_13_LPUART1_RX -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_12_LPUART1_TX #endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/teensy41/clock_config.c b/ports/mimxrt10xx/boards/teensy40/board/clock_config.c similarity index 74% rename from ports/mimxrt10xx/boards/teensy41/clock_config.c rename to ports/mimxrt10xx/boards/teensy40/board/clock_config.c index 38f0b8f99..31329ed60 100644 --- a/ports/mimxrt10xx/boards/teensy41/clock_config.c +++ b/ports/mimxrt10xx/boards/teensy40/board/clock_config.c @@ -1,10 +1,3 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* * How to setup clock using clock driver functions: * @@ -22,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v5.0 +product: Clocks v18.0 processor: MIMXRT1062xxxxA package_id: MIMXRT1062DVL6A mcu_data: ksdk2_0 -processor_version: 0.0.0 +processor_version: 25.09.10 board: MIMXRT1060-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -40,8 +33,6 @@ board: MIMXRT1060-EVK /******************************************************************************* * Variables ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ @@ -65,9 +56,7 @@ called_from_default_init: true - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} -- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} @@ -77,13 +66,13 @@ called_from_default_init: true - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} - {id: MQS_MCLK.outFreq, value: 1080/17 MHz} - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} @@ -96,8 +85,10 @@ called_from_default_init: true - {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} settings: @@ -107,10 +98,13 @@ called_from_default_init: true - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} @@ -131,32 +125,57 @@ called_from_default_init: true - {id: CCM_ANALOG.PLL4.denom, value: '50'} - {id: CCM_ANALOG.PLL4.div, value: '47'} - {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} - {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -222,9 +241,8 @@ void BOARD_BootClockRUN(void) /* Set Usdhc2 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); @@ -236,9 +254,8 @@ void BOARD_BootClockRUN(void) CLOCK_SetMux(kCLOCK_SemcMux, 0); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); @@ -271,9 +288,9 @@ void BOARD_BootClockRUN(void) /* Disable TRACE clock gate. */ CLOCK_DisableClock(kCLOCK_Trace); /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); + CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ @@ -367,10 +384,12 @@ void BOARD_BootClockRUN(void) /* Init ARM PLL. */ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ @@ -383,9 +402,8 @@ void BOARD_BootClockRUN(void) CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); #endif /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Init Usb1 PLL. */ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); @@ -397,8 +415,6 @@ void BOARD_BootClockRUN(void) CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); /* Init Usb1 pfd3. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); @@ -409,36 +425,41 @@ void BOARD_BootClockRUN(void) CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); /* DeInit Enet PLL. */ CLOCK_DeinitEnetPll(); /* Bypass Enet PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); /* Enable Enet output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; /* Set Enet2 output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); /* Enable Enet2 output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; /* Enable Enet25M output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); /* Set preperiph clock source. */ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ @@ -448,8 +469,7 @@ void BOARD_BootClockRUN(void) /* Set per clock source. */ CLOCK_SetMux(kCLOCK_PerclkMux, 0); /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = - (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); /* Set clock out1 divider. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); /* Set clock out1 source. */ @@ -475,15 +495,11 @@ void BOARD_BootClockRUN(void) /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET1 Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); - /* Set ENET2 Tx clock source. */ -#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); -#else - IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); -#endif + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ diff --git a/ports/mimxrt10xx/boards/teensy40/board/clock_config.h b/ports/mimxrt10xx/boards/teensy40/board/clock_config.h new file mode 100644 index 000000000..2fa713c0d --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy40/board/clock_config.h @@ -0,0 +1,123 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/teensy40/board/pin_mux.c b/ports/mimxrt10xx/boards/teensy40/board/pin_mux.c new file mode 100644 index 000000000..5b61c4c63 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy40/board/pin_mux.c @@ -0,0 +1,177 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1060-EVK +pin_labels: +- {pin_num: E7, pin_signal: GPIO_B0_01, label: LCDIF_ENABLE, identifier: USER_BUTTON} +- {pin_num: D8, pin_signal: GPIO_B0_03, label: LCDIF_VSYNC, identifier: USER_LED} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); + BOARD_InitDEBUG_UARTPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: D8, peripheral: GPIO2, signal: 'gpio_io, 03', pin_signal: GPIO_B0_03, direction: OUTPUT} + - {pin_num: E7, peripheral: GPIO2, signal: 'gpio_io, 01', pin_signal: GPIO_B0_01, direction: INPUT, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of USER_BUTTON on GPIO_B0_01 (pin E7) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_B0_01 (pin E7) */ + GPIO_PinInit(GPIO2, 1U, &USER_BUTTON_config); + + /* GPIO configuration of USER_LED on GPIO_B0_03 (pin D8) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_B0_03 (pin D8) */ + GPIO_PinInit(GPIO2, 3U, &USER_LED_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_GPIO2_IO01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_GPIO2_IO03, 0U); + IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 & + (~(BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_GPIO2_IO01, 0xB0B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSDHCPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05} + - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04} + - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03} + - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02} + - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00} + - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01} + - {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitUSDHCPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitUSDHCPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} + - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} + - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} + - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} + - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/teensy40/board/pin_mux.h b/ports/mimxrt10xx/boards/teensy40/board/pin_mux.h new file mode 100644 index 000000000..91d47513b --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy40/board/pin_mux.h @@ -0,0 +1,190 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x0AU /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */ + +/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 3U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 3U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 3U) /*!< PORT pin mask */ + +/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 1U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 1U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 1U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 1U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 1U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_B0_05 (coord J2), SD1_D3 */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL usdhc_data /*!< Signal name */ +#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL 3U /*!< Signal channel */ + +/* GPIO_SD_B0_04 (coord H2), SD1_D2 */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL usdhc_data /*!< Signal name */ +#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL 2U /*!< Signal channel */ + +/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL usdhc_data /*!< Signal name */ +#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL 1U /*!< Signal channel */ + +/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL usdhc_data /*!< Signal name */ +#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL 0U /*!< Signal channel */ + +/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< Signal name */ + +/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL usdhc_clk /*!< Signal name */ + +/* GPIO_B1_14 (coord C14), SD0_VSELECT */ +/* Routed pin properties */ +#define BOARD_INITUSDHCPINS_SD0_VSELECT_PERIPHERAL USDHC1 /*!< Peripheral name */ +#define BOARD_INITUSDHCPINS_SD0_VSELECT_SIGNAL usdhc_vselect /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSDHCPins(void); + +/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/teensy40/clock_config.h b/ports/mimxrt10xx/boards/teensy40/clock_config.h deleted file mode 100644 index 082202484..000000000 --- a/ports/mimxrt10xx/boards/teensy40/clock_config.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/teensy40/flash_config.c b/ports/mimxrt10xx/boards/teensy40/flash_config.c index 7dd325ef5..4662c34a0 100644 --- a/ports/mimxrt10xx/boards/teensy40/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy40/flash_config.c @@ -9,155 +9,109 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for on-chip W25Q64JVXGIM Q64JVXGIM with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = 0x56010000, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 0u, - .deviceModeArg = 0x0000, - .configCmdEnable = 0u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = BOARD_FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + .tag = FLEXSPI_CFG_BLK_TAG, + .version = 0x56010000, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 0u, + .deviceModeArg = 0x0000, + .configCmdEnable = 0u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = BOARD_FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/teensy40/teensy40.mex b/ports/mimxrt10xx/boards/teensy40/teensy40.mex new file mode 100644 index 000000000..6c9b839bf --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy40/teensy40.mex @@ -0,0 +1,617 @@ + + + + MIMXRT1062xxxxA + MIMXRT1062DVL6A + MIMXRT1060-EVK + A2 + ksdk2_0 + + + + + + + false + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 0.0.0 + + + + + + + 13.0.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + kELCDIF_CurFrameDoneInterruptEnable + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + diff --git a/ports/mimxrt10xx/boards/teensy41/board.cmake b/ports/mimxrt10xx/boards/teensy41/board.cmake new file mode 100644 index 000000000..2fe422775 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy41/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT MIMXRT1062) + +set(PYOCD_TARGET mimxrt1060) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + CPU_MIMXRT1062DVL6A + ) +endfunction() diff --git a/ports/mimxrt10xx/boards/teensy41/board.h b/ports/mimxrt10xx/boards/teensy41/board.h index fc027ac1b..329c7601a 100644 --- a/ports/mimxrt10xx/boards/teensy41/board.h +++ b/ports/mimxrt10xx/boards/teensy41/board.h @@ -34,33 +34,18 @@ //--------------------------------------------------------------------+ // LED //--------------------------------------------------------------------+ - -#define LED_PINMUX IOMUXC_GPIO_B0_03_GPIO2_IO03 -#define LED_PORT GPIO2 -#define LED_PIN 3 +#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL +#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL #define LED_STATE_ON 0 //--------------------------------------------------------------------+ // Neopixel //--------------------------------------------------------------------+ - -// Number of neopixels -#define NEOPIXEL_NUMBER 0 - -//--------------------------------------------------------------------+ -// Button -//--------------------------------------------------------------------+ - -// Teensy 4.1 pin 23. -#define BUTTON_PINMUX IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 -#define BUTTON_PORT GPIO1 -#define BUTTON_PIN 25 -#define BUTTON_STATE_ACTIVE 0 +#define NEOPIXEL_NUMBER 0 // Number of neopixels //--------------------------------------------------------------------+ // USB UF2 //--------------------------------------------------------------------+ - #define USB_VID 0x239A #define USB_PID 0x00AD #define USB_MANUFACTURER "PJRC" @@ -74,9 +59,6 @@ //--------------------------------------------------------------------+ // UART //--------------------------------------------------------------------+ - #define UART_DEV LPUART1 -#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_13_LPUART1_RX -#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_12_LPUART1_TX #endif /* BOARD_H_ */ diff --git a/ports/mimxrt10xx/boards/teensy41/board/clock_config.c b/ports/mimxrt10xx/boards/teensy41/board/clock_config.c new file mode 100644 index 000000000..31329ed60 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy41/board/clock_config.c @@ -0,0 +1,509 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1060-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable Flexspi2 clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi2); + /* Set FLEXSPI2_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + /* Set Flexspi2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can3); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + CLOCK_DisableClock(kCLOCK_Can3S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/ports/mimxrt10xx/boards/teensy41/board/clock_config.h b/ports/mimxrt10xx/boards/teensy41/board/clock_config.h new file mode 100644 index 000000000..2fa713c0d --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy41/board/clock_config.h @@ -0,0 +1,123 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/teensy41/board/pin_mux.c b/ports/mimxrt10xx/boards/teensy41/board/pin_mux.c new file mode 100644 index 000000000..16469fb33 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy41/board/pin_mux.c @@ -0,0 +1,143 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: MIMXRT1060-EVK +pin_labels: +- {pin_num: E7, pin_signal: GPIO_B0_01, label: LCDIF_ENABLE, identifier: USER_BUTTON} +- {pin_num: D8, pin_signal: GPIO_B0_03, label: LCDIF_VSYNC, identifier: USER_LED} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: D8, peripheral: GPIO2, signal: 'gpio_io, 03', pin_signal: GPIO_B0_03, direction: OUTPUT} + - {pin_num: E7, peripheral: GPIO2, signal: 'gpio_io, 01', pin_signal: GPIO_B0_01, direction: INPUT, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* GPIO configuration of USER_BUTTON on GPIO_B0_01 (pin E7) */ + gpio_pin_config_t USER_BUTTON_config = { + .direction = kGPIO_DigitalInput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_B0_01 (pin E7) */ + GPIO_PinInit(GPIO2, 1U, &USER_BUTTON_config); + + /* GPIO configuration of USER_LED on GPIO_B0_03 (pin D8) */ + gpio_pin_config_t USER_LED_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on GPIO_B0_03 (pin D8) */ + GPIO_PinInit(GPIO2, 3U, &USER_LED_config); + + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_GPIO2_IO01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_GPIO2_IO03, 0U); + IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 & + (~(BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK))) + | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U) + ); + IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_GPIO2_IO01, 0xB0B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, + pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitQSPIPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} + - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} + - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} + - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} + - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} + - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} + - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitQSPIPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitQSPIPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/teensy41/board/pin_mux.h b/ports/mimxrt10xx/boards/teensy41/board/pin_mux.h new file mode 100644 index 000000000..0e1808eb8 --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy41/board/pin_mux.h @@ -0,0 +1,145 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define BOARD_INITPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x0AU /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */ + +/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_LED_CHANNEL 3U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_LED_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_LED_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_PIN 3U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 3U) /*!< PORT pin mask */ + +/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */ +/* Routed pin properties */ +#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */ +#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ +#define BOARD_INITPINS_USER_BUTTON_CHANNEL 1U /*!< Signal channel */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 1U /*!< GPIO pin number */ +#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 1U) /*!< GPIO pin mask */ +#define BOARD_INITPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */ +#define BOARD_INITPINS_USER_BUTTON_PIN 1U /*!< PORT pin number */ +#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 1U) /*!< PORT pin mask */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + +/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ + +/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ + +/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ + +/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ + +/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ + +/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ + +/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */ +/* Routed pin properties */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */ +#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitQSPIPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/ports/mimxrt10xx/boards/teensy41/clock_config.h b/ports/mimxrt10xx/boards/teensy41/clock_config.h deleted file mode 100644 index 082202484..000000000 --- a/ports/mimxrt10xx/boards/teensy41/clock_config.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt10xx/boards/teensy41/flash_config.c b/ports/mimxrt10xx/boards/teensy41/flash_config.c index 7dd325ef5..4662c34a0 100644 --- a/ports/mimxrt10xx/boards/teensy41/flash_config.c +++ b/ports/mimxrt10xx/boards/teensy41/flash_config.c @@ -9,155 +9,109 @@ #include "fsl_flexspi_nor_boot.h" #include "boards.h" - -__attribute__((section(".boot_hdr.ivt"))) -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address) */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -__attribute__((section(".boot_hdr.boot_data"))) -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T g_boot_data = { - BOARD_BOOT_START, /* boot start location */ - BOARD_BOOT_LENGTH, - PLUGIN_FLAG, /* Plugin flag */ - 0xFFFFFFFF /* empty - extra data word */ -}; - // Config for on-chip W25Q64JVXGIM Q64JVXGIM with QSPI routed. -__attribute__((section(".boot_hdr.conf"))) -const flexspi_nor_config_t qspiflash_config = { - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, - .blockSize = 0x00010000, - .isUniformBlockSize = false, - .memConfig = +__attribute__((section(".boot_hdr.conf"))) const flexspi_nor_config_t flash_nor_config = { + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, + .blockSize = 0x00010000, + .isUniformBlockSize = false, + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = 0x56010000, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - - .busyOffset = 0u, // Status bit 0 indicates busy. - .busyBitPolarity = 0u, // Busy when the bit is 1. - - .deviceModeCfgEnable = 0u, - .deviceModeArg = 0x0000, - .configCmdEnable = 0u, - .configModeType[0] = kDeviceConfigCmdType_Generic, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = BOARD_FLASH_SIZE, - .lookupTable = - { - // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) - // The high 16 bits is command 1 and the low are command 0. - // Within a command, the top 6 bits are the opcode, the next two are the number - // of pads and then last byte is the operand. The operand's meaning changes - // per opcode. - - // Indices with ROM should always have the same function because the ROM - // bootloader uses it. - - // 0: ROM: Read LUTs - // Quad version - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, - RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, - READ_SDR, FLEXSPI_4PAD, 0x04), - // Single fast read version, good for debugging. - // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, - // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, - // READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 1: ROM: Read status - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, - READ_SDR, FLEXSPI_1PAD, 0x04), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 2: Empty - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - - // 3: ROM: Write Enable - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, - STOP, FLEXSPI_1PAD, 0x00), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 4: Config: Write Status - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - - // 5: ROM: Erase Sector - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 6: Empty - EMPTY_SEQUENCE, - - // 7: Empty - EMPTY_SEQUENCE, - - // 8: Block Erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 9: ROM: Page program - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, - RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), - - FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 10: Empty - EMPTY_SEQUENCE, - - // 11: ROM: Chip erase - SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, - STOP, FLEXSPI_1PAD, 0), - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS, - TWO_EMPTY_STEPS), - - // 12: Empty - EMPTY_SEQUENCE, - - // 13: ROM: Read SFDP - EMPTY_SEQUENCE, - - // 14: ROM: Restore no cmd - EMPTY_SEQUENCE, - - // 15: ROM: Dummy - EMPTY_SEQUENCE - }, + .tag = FLEXSPI_CFG_BLK_TAG, + .version = 0x56010000, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromSckPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + + .busyOffset = 0u, // Status bit 0 indicates busy. + .busyBitPolarity = 0u, // Busy when the bit is 1. + + .deviceModeCfgEnable = 0u, + .deviceModeArg = 0x0000, + .configCmdEnable = 0u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = BOARD_FLASH_SIZE, + .lookupTable = + {// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) + // The high 16 bits is command 1 and the low are command 0. + // Within a command, the top 6 bits are the opcode, the next two are the number + // of pads and then last byte is the operand. The operand's meaning changes + // per opcode. + + // Indices with ROM should always have the same function because the ROM + // bootloader uses it. + + // 0: ROM: Read LUTs + // Quad version + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, RADDR_SDR, FLEXSPI_4PAD, + 24 /* bits to transmit */), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, READ_SDR, + FLEXSPI_4PAD, 0x04), + // Single fast read version, good for debugging. + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, + // READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 1: ROM: Read status + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, READ_SDR, FLEXSPI_1PAD, 0x04), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 2: Empty + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + + // 3: ROM: Write Enable + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, STOP, FLEXSPI_1PAD, 0x00), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 4: Config: Write Status + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + + // 5: ROM: Erase Sector + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 6: Empty + EMPTY_SEQUENCE, + + // 7: Empty + EMPTY_SEQUENCE, + + // 8: Block Erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 9: ROM: Page program + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, RADDR_SDR, FLEXSPI_1PAD, + 24 /* bits to transmit */), + + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, STOP, FLEXSPI_1PAD, 0), TWO_EMPTY_STEPS, + TWO_EMPTY_STEPS), + + // 10: Empty + EMPTY_SEQUENCE, + + // 11: ROM: Chip erase + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, STOP, FLEXSPI_1PAD, 0), + TWO_EMPTY_STEPS, TWO_EMPTY_STEPS, TWO_EMPTY_STEPS), + + // 12: Empty + EMPTY_SEQUENCE, + + // 13: ROM: Read SFDP + EMPTY_SEQUENCE, + + // 14: ROM: Restore no cmd + EMPTY_SEQUENCE, + + // 15: ROM: Dummy + EMPTY_SEQUENCE}, }, }; diff --git a/ports/mimxrt10xx/boards/teensy41/teensy41.mex b/ports/mimxrt10xx/boards/teensy41/teensy41.mex new file mode 100644 index 000000000..6c9b839bf --- /dev/null +++ b/ports/mimxrt10xx/boards/teensy41/teensy41.mex @@ -0,0 +1,617 @@ + + + + MIMXRT1062xxxxA + MIMXRT1062DVL6A + MIMXRT1060-EVK + A2 + ksdk2_0 + + + + + + + false + false + true + true + false + + + + + + + + + 25.09.10 + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + 0.0.0 + + + + + + + 13.0.2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + kELCDIF_CurFrameDoneInterruptEnable + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0.0.0 + + + + diff --git a/ports/mimxrt10xx/family.cmake b/ports/mimxrt10xx/family.cmake index 066a48fa8..d606aa673 100644 --- a/ports/mimxrt10xx/family.cmake +++ b/ports/mimxrt10xx/family.cmake @@ -1,8 +1,5 @@ include_guard(GLOBAL) -#------------------------------------ -# Config -#------------------------------------ set(UF2_FAMILY_ID 0x4fb2d5bd) set(SDK_DIR ${TOP}/lib/mcu/nxp/mcux-sdk) set(CMSIS_DIR ${TOP}/lib/CMSIS_5) @@ -26,6 +23,14 @@ set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../cmake/toolchain/arm_${T # Note: The .elf file cannot be written directly to flash since the target # is RAM and the addresses need to be translated. #--------------------------------------------------------- +if (NOT DEFINED SDPHOST) + set(SDPHOST sdphost) +endif () + +if (NOT DEFINED BLHOST) + set(BLHOST blhost) +endif () + set(SDP_MIMXRT1011_PID 0x0145) set(SDP_MIMXRT1015_PID 0x0130) set(SDP_MIMXRT1021_PID 0x0130) @@ -36,27 +41,18 @@ set(SDP_MIMXRT1062_PID 0x0135) set(SDP_MIMXRT1064_PID 0x0135) set(SDP_MIMXRT1176_PID 0x013d) -set(UF2_MIMXRT1011_ADDR 0x60000400) -set(UF2_MIMXRT1015_ADDR 0x60000000) -set(UF2_MIMXRT1021_ADDR 0x60000000) -set(UF2_MIMXRT1024_ADDR 0x60000000) -set(UF2_MIMXRT1042_ADDR 0x60000000) -set(UF2_MIMXRT1052_ADDR 0x60000000) -set(UF2_MIMXRT1062_ADDR 0x60000000) -set(UF2_MIMXRT1064_ADDR 0x70000000) -set(UF2_MIMXRT1176_ADDR 0x30000400) - set(SDP_PID ${SDP_${MCU_VARIANT}_PID}) -set(UF2_ADDR ${UF2_${MCU_VARIANT}_ADDR}) -set(FLASHLOADER_PID ${FLASHLOADER_${MCU_VARIANT}_PID}) cmake_print_variables(MCU_VARIANT) file(STRINGS ${CMAKE_CURRENT_LIST_DIR}/linker/${MCU_VARIANT}_ram.ld FCFB_ORIGIN REGEX "_fcfb_origin *=") string(REGEX REPLACE ".*= *(0x[0-9a-fA-F]+).*" "\\1" FCFB_ORIGIN ${FCFB_ORIGIN}) +file(STRINGS ${CMAKE_CURRENT_LIST_DIR}/linker/${MCU_VARIANT}_ram.ld FLASH_BASE REGEX "_flash_base *=") +string(REGEX REPLACE ".*= *(0x[0-9a-fA-F]+).*" "\\1" FLASH_BASE ${FLASH_BASE}) math(EXPR IVT_ORIGIN "( ${FCFB_ORIGIN} & ~0xFFF ) + 0x1000" OUTPUT_FORMAT HEXADECIMAL) +math(EXPR FLASH_FCFB_ADDR "( ${FLASH_BASE} + (${FCFB_ORIGIN} & 0xFFF) )" OUTPUT_FORMAT HEXADECIMAL) -cmake_print_variables(FCFB_ORIGIN IVT_ORIGIN) +cmake_print_variables(FCFB_ORIGIN IVT_ORIGIN FLASH_FCFB_ADDR) #------------------------------------ # BOARD_TARGET @@ -77,6 +73,9 @@ function(family_add_board_target BOARD_TARGET) ${SDK_DIR}/drivers/ocotp/fsl_ocotp.c ${SDK_DIR}/drivers/pwm/fsl_pwm.c ${SDK_DIR}/drivers/xbara/fsl_xbara.c + ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/flash_config.c + ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board/clock_config.c + ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board/pin_mux.c ) # ROM API is present on most parts except RT1011. @@ -154,19 +153,11 @@ endfunction() function(family_gen_bin_hex TARGET) add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary $ $/${TARGET}.bin - COMMAND ${CMAKE_OBJCOPY} -Ibinary -Oihex --change-addresses ${UF2_ADDR} $/${TARGET}.bin $/${TARGET}.hex + COMMAND ${CMAKE_OBJCOPY} -Ibinary -Oihex --change-addresses ${FLASH_FCFB_ADDR} $/${TARGET}.bin $/${TARGET}.hex VERBATIM) endfunction() function(family_flash_sdp TARGET) - if (NOT DEFINED SDPHOST) - set(SDPHOST sdphost) - endif () - - if (NOT DEFINED BLHOST) - set(BLHOST blhost) - endif () - if (MCU_VARIANT STREQUAL "MIMXRT1176") # Create a ROM load-image friendly binary with IVT at file offset 0. add_custom_command(TARGET ${TARGET} POST_BUILD diff --git a/ports/mimxrt10xx/linker/common.ld b/ports/mimxrt10xx/linker/common.ld index 58184ebfb..edccf2be1 100644 --- a/ports/mimxrt10xx/linker/common.ld +++ b/ports/mimxrt10xx/linker/common.ld @@ -27,8 +27,6 @@ HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0; -_board_dfu_dbl_tap = ORIGIN(m_data) + LENGTH(m_data); - /* Define output sections */ SECTIONS { diff --git a/ports/mimxrt10xx/port.mk b/ports/mimxrt10xx/port.mk index b5aa05c02..43ee262eb 100644 --- a/ports/mimxrt10xx/port.mk +++ b/ports/mimxrt10xx/port.mk @@ -26,6 +26,9 @@ CFLAGS += -Wno-error=unused-parameter # Port source SRC_C += \ + $(BOARD_DIR)/flash_config.c \ + $(BOARD_DIR)/board/clock_config.c \ + $(BOARD_DIR)/board/pin_mux.c \ $(MCU_DIR)/drivers/fsl_clock.c \ $(SDK_DIR)/drivers/cache/armv7-m7/fsl_cache.c \ $(SDK_DIR)/drivers/common/fsl_common.c \ @@ -34,8 +37,7 @@ SRC_C += \ $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c \ $(SDK_DIR)/drivers/ocotp/fsl_ocotp.c \ $(SDK_DIR)/drivers/pwm/fsl_pwm.c \ - $(SDK_DIR)/drivers/xbara/fsl_xbara.c \ - $(BOARD_DIR)/clock_config.c + $(SDK_DIR)/drivers/xbara/fsl_xbara.c ifeq ($(MCU),MIMXRT1176) SRC_C += $(MCU_DIR)/system_$(MCU)_cm7.c @@ -61,7 +63,6 @@ ifndef BUILD_NO_TINYUSB SRC_C += lib/tinyusb/src/portable/chipidea/ci_hs/dcd_ci_hs.c endif - # Port include INC += \ $(TOP)/$(PORT_DIR) \ diff --git a/ports/stm32f3/README.md b/ports/stm32f3/README.md index b86368edf..286f2f7d0 100644 --- a/ports/stm32f3/README.md +++ b/ports/stm32f3/README.md @@ -17,3 +17,7 @@ From bin uf2conv.py -c -b 0x08004000 -f STM32F3 firmware.bin uf2conv.py -c -b 0x08004000 -f 0x6b846188 firmware.bin ``` + +## Supported Boards + +See the board list for this family in [supported_boards.md](../../supported_boards.md#stm32f3). diff --git a/ports/stm32f4/README.md b/ports/stm32f4/README.md index a81057254..4fdba2703 100644 --- a/ports/stm32f4/README.md +++ b/ports/stm32f4/README.md @@ -19,3 +19,7 @@ From bin uf2conv.py -c -b 0x08010000 -f STM32F4 firmware.bin uf2conv.py -c -b 0x08010000 -f 0x57755a57 firmware.bin ``` + +## Supported Boards + +See the board list for this family in [supported_boards.md](../../supported_boards.md#stm32f4). diff --git a/ports/stm32h5/README.md b/ports/stm32h5/README.md index f22b2e9c6..6a8f165fc 100644 --- a/ports/stm32h5/README.md +++ b/ports/stm32h5/README.md @@ -3,6 +3,7 @@ TinyUF2 occupies around 16Kb + 1KB for CF2 in flash. Since H5 has uniform sector size of 8KB, ideally we would have bootloader size set to 24KB. However, due to the fact that only H503 can protect/secure individual sector, the rest of H5 family (H52x, H56x) can only secure flash in 4-sector (group) unit. Therefore application should start at - H503: `0x08006000`, boot size is 24KB - H52x, H56x, H57x: `0x08008000`, boot size is 32KB + To create a UF2 image from a .bin file, either use family option `STM32H5` or its magic number as follows: From hex @@ -25,3 +26,7 @@ From bin for H52x, H56x, H57x uf2conv.py -c -b 0x08008000 -f STM32H5 firmware.bin uf2conv.py -c -b 0x08008000 -f 0x4e8f1c5d firmware.bin ``` + +## Supported Boards + +See the board list for this family in [supported_boards.md](../../supported_boards.md#stm32h5). diff --git a/ports/stm32h7/README.md b/ports/stm32h7/README.md index 8269659e8..20ac0009f 100644 --- a/ports/stm32h7/README.md +++ b/ports/stm32h7/README.md @@ -1,3 +1,7 @@ # TinyUF2 for STM32H7 TinyUF2 reserves 64KB like the F4 port to be compatible with existing application. + +## Supported Boards + +See the board list for this family in [supported_boards.md](../../supported_boards.md#stm32h7). diff --git a/ports/stm32l4/README.md b/ports/stm32l4/README.md index 89899eb64..b721b9d01 100644 --- a/ports/stm32l4/README.md +++ b/ports/stm32l4/README.md @@ -17,3 +17,7 @@ From bin uf2conv.py -c -b 0x08010000 -f STM32L4 firmware.bin uf2conv.py -c -b 0x08010000 -f 0x00ff6919 firmware.bin ``` + +## Supported Boards + +See the board list for this family in [supported_boards.md](../../supported_boards.md#stm32l4). diff --git a/src/board_api.h b/src/board_api.h index fc2fb9a26..1563c871b 100644 --- a/src/board_api.h +++ b/src/board_api.h @@ -68,7 +68,7 @@ #ifndef TUF2_LOG - #define TUF2_LOG 2 + #define TUF2_LOG 1 #endif // Use LED for part of indicator diff --git a/src/main.c b/src/main.c index 498f18f19..bf295f988 100644 --- a/src/main.c +++ b/src/main.c @@ -35,21 +35,21 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTOTYPES //--------------------------------------------------------------------+ -//#define USE_DFU_BUTTON 1 +// #define USE_DFU_BUTTON 1 #ifndef NEOPIXEL_INVERT_RG -uint8_t RGB_USB_UNMOUNTED[] = { 0xff, 0x00, 0x00 }; // Red -uint8_t RGB_USB_MOUNTED[] = { 0x00, 0xff, 0x00 }; // Green -uint8_t RGB_WRITING[] = { 0xcc, 0x66, 0x00 }; -uint8_t RGB_DOUBLE_TAP[] = { 0x80, 0x00, 0xff }; // Purple +uint8_t RGB_USB_UNMOUNTED[] = {0xff, 0x00, 0x00}; // Red +uint8_t RGB_USB_MOUNTED[] = {0x00, 0xff, 0x00}; // Green +uint8_t RGB_WRITING[] = {0xcc, 0x66, 0x00}; +uint8_t RGB_DOUBLE_TAP[] = {0x80, 0x00, 0xff}; // Purple #else -uint8_t RGB_USB_UNMOUNTED[] = { 0x00, 0xff, 0x00 }; // Red -uint8_t RGB_USB_MOUNTED[] = { 0xff, 0x00, 0x00 }; // Green -uint8_t RGB_WRITING[] = { 0x66, 0xcc, 0x00 }; -uint8_t RGB_DOUBLE_TAP[] = { 0x00, 0x80, 0xff }; // Purple +uint8_t RGB_USB_UNMOUNTED[] = {0x00, 0xff, 0x00}; // Red +uint8_t RGB_USB_MOUNTED[] = {0xff, 0x00, 0x00}; // Green +uint8_t RGB_WRITING[] = {0x66, 0xcc, 0x00}; +uint8_t RGB_DOUBLE_TAP[] = {0x00, 0x80, 0xff}; // Purple #endif -uint8_t RGB_UNKNOWN[] = { 0x00, 0x00, 0x88 }; // for debug -uint8_t RGB_OFF[] = { 0x00, 0x00, 0x00 }; +uint8_t RGB_UNKNOWN[] = {0x00, 0x00, 0x88}; // for debug +uint8_t RGB_OFF[] = {0x00, 0x00, 0x00}; static volatile uint32_t _timer_count = 0; @@ -60,7 +60,9 @@ static bool check_dfu_mode(void); int main(void) { board_init(); - if (board_init2) board_init2(); + if (board_init2) { + board_init2(); + } TUF2_LOG1("TinyUF2\r\n"); #if TINYUF2_PROTECT_BOOTLOADER @@ -70,8 +72,12 @@ int main(void) { // if not DFU mode, jump to App if (!check_dfu_mode()) { TUF2_LOG1("Jump to application\r\n"); - if (board_teardown) board_teardown(); - if (board_teardown2) board_teardown2(); + if (board_teardown) { + board_teardown(); + } + if (board_teardown2) { + board_teardown2(); + } board_app_jump(); TUF2_LOG1("Failed to jump\r\n"); while (1) {} @@ -92,7 +98,7 @@ int main(void) { #endif #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO - while(1) { + while (1) { tud_task(); } #endif @@ -111,9 +117,9 @@ static bool check_dfu_mode(void) { } #if TINYUF2_DBL_TAP_DFU - TUF2_LOG1_HEX(TINYUF2_DBL_TAP_REG); + TUF2_LOG1_HEX(TINYUF2_DBL_TAP_REG); - switch(TINYUF2_DBL_TAP_REG) { + switch (TINYUF2_DBL_TAP_REG) { case DBL_TAP_MAGIC_QUICK_BOOT: // Boot to app quickly TUF2_LOG1("Quick boot to App\r\n"); @@ -152,7 +158,7 @@ static bool check_dfu_mode(void) { board_rgb_write(RGB_DOUBLE_TAP); // delay a fraction of second if Reset pin is tap during this delay --> we will enter dfu - while(_timer_count < TINYUF2_DBL_TAP_DELAY) {} + while (_timer_count < TINYUF2_DBL_TAP_DELAY) {} board_timer_stop(); // Turn off indicator @@ -184,7 +190,7 @@ void tud_umount_cb(void) { //--------------------------------------------------------------------+ static uint32_t indicator_state = STATE_BOOTLOADER_STARTED; -static uint8_t indicator_rgb[3]; +static uint8_t indicator_rgb[3]; void indicator_set(uint32_t state) { indicator_state = state; @@ -224,7 +230,9 @@ void board_timer_handler(void) { case STATE_USB_PLUGGED: { // Fading with LED TODO option to skip for unsupported MCUs uint8_t duty = _timer_count & 0xff; - if (_timer_count & 0x100) duty = 255 - duty; + if (_timer_count & 0x100) { + duty = 255 - duty; + } board_led_write(duty); // Skip RGB fading since it is too similar to CircuitPython @@ -257,19 +265,25 @@ void board_timer_handler(void) { // Enable only with LOG is enabled (Note: ESP32-S2 has built-in support already) #if (CFG_TUSB_DEBUG || TUF2_LOG) && (CFG_TUSB_MCU != OPT_MCU_ESP32S2 && CFG_TUSB_MCU != OPT_MCU_RP2040) -#if defined(LOGGER_RTT) -#include "SEGGER_RTT.h" -#endif + #if defined(LOGGER_RTT) + #include "SEGGER_RTT.h" + #endif -TU_ATTR_USED int _write (int fhdl, const void *buf, size_t count) { - (void) fhdl; +TU_ATTR_USED int _write(int fhdl, const void *buf, size_t count) { + (void)fhdl; -#if defined(LOGGER_RTT) - SEGGER_RTT_Write(0, (char*) buf, (int) count); + #if defined(LOGGER_RTT) + SEGGER_RTT_Write(0, (char *)buf, (int)count); return count; -#else + #elif defined(LOGGER_SWO) + const uint8_t *data = (const uint8_t *)buf; + for (size_t i = 0; i < count; i++) { + ITM_SendChar(data[i]); + } + return (int)count; + #else return board_uart_write(buf, count); -#endif + #endif } #endif diff --git a/supported_boards.md b/supported_boards.md new file mode 100644 index 000000000..a8c6c4a3f --- /dev/null +++ b/supported_boards.md @@ -0,0 +1,198 @@ +# Supported Boards + +## espressif + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| adafruit_camera_esp32s3 | Adafruit PyCamera | 0x239A:0x0117 | https://www.adafruit.com/ | +| adafruit_feather_esp32s2 | Adafruit Feather ESP32-S2 | 0x239A:0x00EB | https://www.adafruit.com/product/5000 | +| adafruit_feather_esp32s2_reverse_tft | Adafruit Feather ESP32-S2 Reverse TFT | 0x239A:0x00ED | https://www.adafruit.com/product/5345 | +| adafruit_feather_esp32s2_tft | Adafruit Feather ESP32-S2 TFT | 0x239A:0x010F | https://www.adafruit.com/product/5300 | +| adafruit_feather_esp32s3 | Adafruit Feather ESP32-S3 | 0x239A:0x011B | https://www.adafruit.com/product/5477 | +| adafruit_feather_esp32s3_nopsram | Adafruit Feather ESP32-S3 No PSRAM | 0x239A:0x0113 | https://www.adafruit.com/product/5323 | +| adafruit_feather_esp32s3_reverse_tft | Adafruit Feather ESP32-S3 Reverse TFT | 0x239A:0x0123 | https://www.adafruit.com/ | +| adafruit_feather_esp32s3_tft | Adafruit Feather ESP32-S3 TFT | 0x239A:0x011D | https://www.adafruit.com/product/5483 | +| adafruit_funhouse_esp32s2 | Adafruit FunHouse | 0x239A:0x00F9 | https://www.adafruit.com/ | +| adafruit_magtag_29gray | Adafruit MagTag 2.9 Grayscale | 0x239A:0x00E5 | https://www.adafruit.com/product/4800 | +| adafruit_matrixportal_s3 | Adafruit MatrixPortal S3 | 0x239A:0x0125 | https://www.adafruit.com/ | +| adafruit_metro_esp32s2 | Adafruit Metro ESP32-S2 | 0x239A:0x00DF | https://www.adafruit.com/product/4775 | +| adafruit_metro_esp32s3 | Adafruit Metro ESP32-S3 | 0x239A:0x0145 | https://www.adafruit.com/product/5500 | +| adafruit_mylittlehacker_esp32s2 | Adafruit My Little Hacker ESP32-S2 | 0x239A:0x013F | https://www.adafruit.com/products/5742 | +| adafruit_qtpy_esp32s2 | Adafruit QT Py ESP32-S2 | 0x239A:0x0111 | https://www.adafruit.com/product/5325 | +| adafruit_qtpy_esp32s3 | Adafruit QT Py ESP32-S3 | 0x239A:0x0119 | https://adafruit.com/product/5426 | +| adafruit_qtpy_esp32s3_n4r2 | Adafruit QT Py ESP32-S3 (4M Flash, 2M PSRAM) | 0x239A:0x0143 | https://adafruit.com/product/5700 | +| adafruit_qualia_s3_rgb666 | Adafruit Qualia ESP32-S3 RGB666 | 0x239A:0x0147 | https://www.adafruit.com/5800 | +| adafruit_vindie_s2 | Adafruit Vindie S2 | 0x239A:0x015F | https://www.adafruit.com/product/5901 | +| artisense_rd00 | Artisense Reference Design RD00 | 0x303A:0x80B0 | https://artisense.ai/ | +| atmegazero_esp32s2 | ATMegaZero ATMegaZero ESP32-S2 | 0x239A:0x800B | https://atmegazero.com | +| bpi_bit_s2 | Banana Pi BPI-BIT-S2 | 0x303A:0x80E4 | https://banana-pi.org/ | +| bpi_leaf_s2 | Banana Pi BPI-Leaf-S2 | 0x303A:0x80E1 | https://banana-pi.org/ | +| bpi_leaf_s3 | Banana Pi BPI-Leaf-S3 | 0x303A:0x80DE | https://banana-pi.org/ | +| bpi_picow_s3 | BananaPi BPI-PicoW-S3 | 0x303A:0x812D | N/A | +| circuitart_zero_s3 | CircuiArt ZeroS3 | 0x303A:0x80DC | https://github.com/CircuitART | +| cytron_maker_feather_aiot_s3 | Cytron Maker Feather AIoT S3 | 0x303A:0x80FA | http://www.cytron.io/p-maker-feather-aiot-s3 | +| deneyap_kart_1a_v2 | T3 Foundation Deneyap Kart 1A v2 | 0x303A:0x8149 | https://magaza.deneyapkart.org/tr/product/detail/deneyap-kart-1a-v2-type-c | +| deneyap_mini | T3 Foundation Deneyap Mini | 0x303A:0x8143 | https://magaza.deneyapkart.org/tr/product/detail/deneyap-mini | +| deneyap_mini_v2 | T3 Foundation Deneyap Mini v2 | 0x303A:0x8146 | https://magaza.deneyapkart.org/tr/product/detail/deneyap-mini-v2-type-c | +| department_of_alchemy_minimain_esp32s2 | Department of Alchemy MiniMain ESP32-S2 | 0x303A:0x8101 | https://github.com/DepartmentOfAlchemy/minimain-esp32-s2 | +| es3ink | Czech maker ES3ink | 0x239A:0x2031 | https://github.com/dronecz/es3ink | +| espressif_esp32s2_devkitc_1 | Espressif ESP32S2 DevKitC 1 | 0x303A:0x7008 | https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-s2-devkitc-1.html | +| espressif_esp32s3_box | Espressif ESP32S3 Box 2.5 | 0x303A:0x7004 | https://github.com/espressif/esp-box | +| espressif_esp32s3_devkitc_1 | Espressif ESP32S3 DevKitC 1 | 0x239A:0x00A5 | https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html | +| espressif_esp32s3_devkitm_1 | Espressif ESP32S3 DevKitM 1 | 0x239A:0x00A5 | https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html | +| espressif_esp32s3_eye | Espressif ESP32S3 EYE | 0x303A:0x700E | https://github.com/espressif/esp-who/blob/master/docs/en/get-started/ESP32-S3-EYE_Getting_Started_Guide.md | +| espressif_hmi_1 | Espressif HMI 1 | 0x303A:0x7000 | https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit.html | +| espressif_kaluga_1 | Espressif Kaluga 1 | 0x239A:0x00C7 | https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit.html | +| espressif_saola_1_wroom | Espressif Saola 1M WROOM | 0x239A:0x00A7 | https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html | +| espressif_saola_1_wrover | Espressif Saola 1R WROVER | 0x239A:0x00A5 | https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html | +| firebeetle2_esp32s3 | DFRobot FireBeetle 2 ESP32-S3 | 0x3343:0x83CF | https://www.dfrobot.com/product-2676.html | +| generic_esp32s3_super_mini | GENERIC ESP32-S3-Super-Mini | 0x303A:0x8248 | https://www.nologo.tech/product/esp32/esp32s3supermini/esp32S3SuperMini.html | +| gravitech_cucumberRIS_v1.1 | Gravitech CucumberRIS v1.1 | 0x303A:0x800E | https://www.gravitech.us/curisdebowis.html | +| heltec_vision_master_t190 | Heltec Vision Master T190 | 0x303A:0x1001 | https://heltec.org/project/vision-master-t190 | +| heltec_wireless_tracker | Heltec Wireless Tracker | 0x303A:0x81A1 | https://heltec.org/project/wireless-tracker | +| hexky_s2 | FutureKeys HexKy-S2 | 0x303A:0x80DA | https://futurekeys.net/index.html | +| hiibot_iots2 | HIIBOT HiiBot IoTs2 | 0x80E7:0x8111 | https://www.tindie.com/products/bradchan/hiibot-iots2/ | +| lilygo_tdeck | LILYGO T-Deck | 0x303A:0x81B7 | https://github.com/Xinyuan-LilyGO/T-Deck | +| lilygo_tdisplay_s3 | LILYGO T-Display S3 | 0x303A:0x8140 | https://github.com/Xinyuan-LilyGO/T-Display-S3 | +| lilygo_tdongle_s3 | LILYGO T-Dongle S3 | 0x303A:0x82C3 | https://github.com/Xinyuan-LilyGO/T-Dongle-S3 | +| lilygo_tqt_pro_nopsram | LILYGO T-QT PRO (8M Flash, NO PSRAM) | 0x303A:0x8155 | https://lilygo.cc/products/t-qt-pro | +| lilygo_tqt_pro_psram | LILYGO T-QT PRO (4M Flash, 2M PSRAM) | 0x303A:0x8155 | https://lilygo.cc/products/t-qt-pro | +| lilygo_ttgo_t8_s2 | LILYGO TTGO_T8_S2 | 0x303A:0x80EE | http://www.lilygo.cn/prod_view.aspx?TypeId=50063&Id=1300&FId=t3:50063:3 | +| lilygo_ttgo_t8_s2_st7789 | LILYGO TTGO_T8_S2_Display | 0x303A:0x8008 | http://www.lilygo.cn/prod_view.aspx?TypeId=50033&Id=1321&FId=t3:50033:3 | +| lilygo_ttgo_t8_s2_wroom | LILYGO TTGO_T8_S2_WROOM | 0x303A:0x80EB | http://www.lilygo.cn/prod_view.aspx?TypeId=50063&Id=1320&FId=t3:50063:3 | +| lilygo_ttgo_t_twr_plus | LilyGO T-TWR Plus | 0x303A:0x8191 | https://www.lilygo.cc/products/t-twr-plus | +| lilygo_ttgo_tbeam_s3 | LilyGO T-Beam Supreme | 0x303A:0x8134 | https://www.lilygo.cc/products/softrf-t-beamsupreme | +| lilygo_twatch_s3 | LILYGO T-Watch-S3 | 0x303A:0x821D | https://github.com/Xinyuan-LilyGO/TTGO_TWatch_Library/tree/t-watch-s3 | +| lolin_s2_mini | Lolin S2 Mini | 0x303A:0x80C4 | https://circuitpython.org/board/lolin_s2_mini/ | +| lolin_s2_pico | Lolin S2 Pico | 0x303A:0x80C7 | https://www.wemos.cc/en/latest/s2/s2_pico.html | +| lolin_s3 | Lolin S3 | 0x303A:0x8118 | https://circuitpython.org/board/lolin_s3/ | +| lolin_s3_mini | Lolin S3Mini | 0x303A:0x8169 | https://www.wemos.cc/en/latest/s3/s3_mini.html | +| m5stack_atoms3 | M5Stack AtomS3 | 0x303A:0x8121 | https://shop.m5stack.com/products/atoms3-dev-kit-w-0-85-inch-screen | +| m5stack_atoms3_lite | M5Stack AtomS3 Lite | 0x303A:0x8160 | https://shop.m5stack.com/products/atoms3-lite-esp32s3-dev-kit | +| m5stack_atoms3u | M5Stack AtomS3U | 0x303A:0x8188 | https://docs.m5stack.com/en/core/AtomS3U | +| m5stack_cores3 | M5Stack CoreS3 | 0x303A:0x811B | https://shop.m5stack.com/products/m5stack-cores3-esp32s3-lotdevelopment-kit | +| m5stack_stamps3 | M5Stack Stamp S3 | 0x303A:0x811A | https://docs.m5stack.com/en/core/StampS3 | +| magiclick_s3_n4r2 | MakerM0 MagiClick S3 | 0x303A:0x81AC | https://github.com/MakerM0/MagiClick-esp32s3 | +| maker_badge | Czech maker Maker badge | 0x239A:0x2030 | https://github.com/dronecz/maker_badge | +| microdev_micro_s2 | MicroDev microS2 | 0x239A:0x00C5 | https://github.com/microDev1/microS2/wiki | +| morpheans_morphesp-240 | MORPHEANS MORPHESP-240 | 0x303A:0x80B6 | https://github.com/ccadic/ESP32-S2-DevBoardTFT | +| muselab_nanoesp32-s2_wroom | Muse Lab nanoESP32-S2 WROOM | 0x239A:0x00DE | https://github.com/wuxx/nanoESP32-S2 | +| muselab_nanoesp32-s2_wrover | Muse Lab nanoESP32-S2 WROVER | 0x303A:0x80B3 | https://github.com/wuxx/nanoESP32-S2 | +| olimex_esp32s2_devkit_lipo_vB1 | Olimex ESP32S2 DevKit Lipo | 0x15BA:0x28DC | https://www.olimex.com/Products/IoT/ESP32-S2/ESP32-S2-DevKit-Lipo/open-source-hardware | +| seeed_xiao_esp32s3 | Seeed Studio XIAO ESP32-S3 | 0x2886:0x8056 | https://www.seeedstudio.com/XIAO-ESP32S3-p-5627.html | +| sensebox_eye_esp32s3 | senseBox eye ESP32S3 | 0x303A:0x82D3 | https://sensebox.de | +| sensebox_mcu_esp32s2 | senseBox MCU-S2 ESP32S2 | 0x303A:0x81BA | https://sensebox.de | +| smartbeedesigns_bee_motion_s3 | Smart Bee Designs Bee Motion S3 | 0x303A:0x8115 | N/A | +| smartbeedesigns_bee_s3 | Smart Bee Designs Bee S3 | 0x303A:0x8112 | N/A | +| targett_mcb_wroom | Targett Module Clip w/Wroom | 0x1209:0x3252 | https://www.targettpcb.co.uk/s2-mcb-1 | +| targett_mcb_wrover | Targett Module Clip w/Wrover | 0x1209:0x3253 | https://www.targettpcb.co.uk/s2-mcb-1 | +| unexpectedmaker_bling | Unexpected Maker Bling! | 0x303A:0x8181 | https://circuitpython.org/board/unexpectedmaker_bling/ | +| unexpectedmaker_edges3d | Unexpected Maker EDGES3D | 0x303A:0x82DE | https://circuitpython.org/board/unexpectedmaker_edges3d/ | +| unexpectedmaker_feathers2 | Unexpected Maker FeatherS2 | 0x239A:0x00AB | https://circuitpython.org/board/unexpectedmaker_feathers2/ | +| unexpectedmaker_feathers2_neo | Unexpected Maker FeatherS2 Neo | 0x303A:0x80B5 | https://circuitpython.org/board/unexpectedmaker_featherS2_neo/ | +| unexpectedmaker_feathers3 | Unexpected Maker FeatherS3 | 0x303A:0x80D8 | https://circuitpython.org/board/unexpectedmaker_feathers3/ | +| unexpectedmaker_feathers3_neo | Unexpected Maker FeatherS3 Neo | 0x303A:0x81FD | https://circuitpython.org/board/unexpectedmaker_feathers3_neo/ | +| unexpectedmaker_nanos3 | Unexpected Maker NanoS3 | 0x303A:0x817B | https://circuitpython.org/board/unexpectedmaker_nanos3/ | +| unexpectedmaker_omgs3 | Unexpected Maker OMGS3 | 0x303A:0x8226 | https://circuitpython.org/board/unexpectedmaker_omgs3/ | +| unexpectedmaker_pros3 | Unexpected Maker ProS3 | 0x303A:0x80D5 | https://circuitpython.org/board/unexpectedmaker_pros3/ | +| unexpectedmaker_rgbtouch_mini | Unexpected Maker RGB Touch Mini | 0x303A:0x8200 | N/A | +| unexpectedmaker_tinys2 | Unexpected Maker TinyS2 | 0x303A:0x8005 | https://circuitpython.org/board/unexpectedmaker_tinys2/ | +| unexpectedmaker_tinys3 | Unexpected Maker TinyS3 | 0x303A:0x80D2 | https://circuitpython.org/board/unexpectedmaker_tinys3/ | +| unexpectedmaker_tinywatchs3 | Unexpected Maker TinyWATCHS3 | 0x303A:0x81B2 | N/A | +| waveshare_esp32_s2_pico_lcd | Waveshare Electronics ESP32-S2-Pico-LCD | 0x303A:0x810B | http://www.waveshare.com/wiki/ESP32-S2-Pico | +| waveshare_esp32_s3_matrix | Waveshare Electronics ESP32-S3-Matrix | 0x303A:0x826F | https://www.waveshare.com/wiki/ESP32-S3-Matrix | +| waveshare_esp32_s3_pico | Waveshare Electronics ESP32-S3-Pico | 0x303A:0x81A2 | http://www.waveshare.com/wiki/ESP32-S2-Pico | +| waveshare_esp32_s3_touch_lcd_169 | Waveshare Electronics ESP32-S3-Touch-LCD-1.69 | 0x303A:0x8220 | https://www.waveshare.com/product/esp32-s3-touch-lcd-1.69.htm | +| waveshare_esp32_s3_touch_lcd_2 | Waveshare Electronics ESP32-S3-Touch-LCD-2 | 0x303A:0x82CF | https://www.waveshare.com/esp32-s3-touch-lcd-2.htm?sku=29667 | +| waveshare_esp32_s3_zero | Waveshare Electronics ESP32-S3-Zero | 0x303A:0x81B3 | https://www.waveshare.com/wiki/ESP32-S3-Zero | +| waveshare_esp32s2_pico | Waveshare Electronics ESP32-S2-Pico | 0x303A:0x8109 | http://www.waveshare.com/wiki/ESP32-S2-Pico | +| waveshare_esp32s3_lcd_169 | Waveshare Electronics ESP32-S3-LCD-1.69 | 0x303A:0x8223 | https://www.waveshare.com/product/esp32-s3-lcd-1.69.htm | +| waveshare_esp32s3_lcd_19 | Waveshare ESP32-S3_LCD_1.9 | 0x303A:0x8223 | https://www.waveshare.com/esp32-s3-lcd-1.9.htm | +| yd_esp32_s3_n16r8 | VCC-GND YD-ESP32-S3 | 0x303A:0x8165 | https://github.com/vcc-gnd/YD-ESP32-S3 | +| yd_esp32_s3_n8r8 | VCC-GND YD-ESP32-S3 | 0x303A:0x8165 | https://github.com/vcc-gnd/YD-ESP32-S3 | + +## kinetis_k32l2 + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| frdm_k32l2b | NXP FRDM-K32L2B3 | 0x1FC9:0x0154 | https://www.nxp.com/FRDM-K32L2B3 | +| kuiic | NXP KUIIC | 0x1FC9:0x0154 | https://www.nxp.com/docs/en/data-sheet/K32L2B3x.pdf | + +## lpc55 + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| double_m33_express | Steiert Solutions Double M33 | 0x1FC9:0x0094 | https://www.crowdsupply.com/steiert-solutions/double-m33-express | +| lpcxpresso55s28 | NXP LPCXpresso 55s28 | 0x1FC9:0x0094 | https://www.nxp.com/LPC55S28-EVK | +| lpcxpresso55s69 | NXP LPCXpresso 55s69 | 0x1FC9:0x0094 | https://www.nxp.com/LPC55S69-EVK | + +## maxim + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| apard32690 | Analog Devices AD-APARD32690-SL | 0x0456:0xA010 | https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html | +| max32650evkit | Analog Devices MAX32650EvKit | 0x0456:0xA010 | https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html | +| max32650fthr | Analog Devices MAX32650FTHR | 0x0456:0xA010 | https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html | +| max32666evkit | Analog Devices MAX32666EvKit | 0x0456:0xA010 | https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html | +| max32666fthr | Analog Devices MAX32666FTHR | 0x0456:0xA010 | https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html | +| max32690evkit | Analog Devices MAX32690EvKit | 0x0456:0xA010 | https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html | +| max78002evkit | Analog Devices MAX78002EvKit | 0x0456:0xA010 | https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html | + +## mimxrt10xx + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| arch_mix_1052 | Seeed Technology Co., Ltd. RT1052 ARCH MIX | 0x2886:0x0010 | https://https://wiki.seeedstudio.com/Arch_Mix/ | +| imxrt1010_evk | NXP RT1010 EVK | 0x239A:0x0077 | https://www.nxp.com/part/MIMXRT1010-EVK#/ | +| imxrt1015_evk | NXP RT1015 EVK | 0x239A:0x0137 | https://www.nxp.com/part/MIMXRT1015-EVK#/ | +| imxrt1020_evk | NXP RT1020 EVK | 0x239A:0x0081 | https://www.nxp.com/part/MIMXRT1020-EVK#/ | +| imxrt1024_evk | NXP RT1024 EVK | 0x239A:0x0081 | https://www.nxp.com/part/MIMXRT1024-EVK#/ | +| imxrt1040_evk | NXP RT1040 EVK | 0x239A:0x0135 | https://www.nxp.com/part/MIMXRT1040-EVK#/ | +| imxrt1050_evkb | NXP RT1050 EVK | 0x239A:0x0133 | https://www.nxp.com/part/IMXRT1050-EVKB#/ | +| imxrt1060_evk | NXP RT1060 EVK | 0x239A:0x0083 | https://www.nxp.com/part/MIMXRT1060-EVK#/ | +| imxrt1064_evk | NXP RT1064 EVK | 0x239A:0x0083 | https://www.nxp.com/part/MIMXRT1064-EVK#/ | +| imxrt1170_evk | NXP RT1170 EVK | 0x239A:0x0099 | https://www.nxp.com/part/MIMXRT1170-EVK#/ | +| makerdiary_rt1011 | Makerdiary iMX RT1011 Nano Kit | 0x2886:0xF00F | https://makerdiary.com/products/imxrt1011-nanokit/ | +| metro_m7_1011 | Adafruit Metro M7 iMX RT1011 | 0x239A:0x00E1 | https://www.adafruit.com/product/4950 | +| metro_m7_1011_sd | Adafruit Metro M7 iMX RT1011 SD | 0x239A:0x0141 | https://www.adafruit.com/product/4950 | +| olimex_rt1010 | Olimex RT1010 | 0x15BA:0x0046 | https://www.olimex.com/Products/MicroPython/RT1010-Py | +| teensy40 | PJRC Teensy 4.0 | 0x239A:0x0085 | https://www.pjrc.com/store/teensy40.html | +| teensy41 | PJRC Teensy 4.1 | 0x239A:0x00AD | https://www.pjrc.com/store/teensy41.html | + +## stm32f3 + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| stm32f303disco | ST STM32F303 Discovery | 0xCAFE:0xFFFF | https://www.st.com/en/evaluation-tools/stm32f3discovery.html | + +## stm32f4 + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| feather_stm32f405_express | Adafruit Feather STM32F405 Express | 0x239A:0x0059 | https://www.adafruit.com/product/4382 | +| sparkfun_micromod_stm32 | SparkFun MicroMod STM32F405 | 0x1B4F:0x002D | https://www.sparkfun.com/products/21326 | +| sparkfun_stm32_thing_plus | SparkFun Thing Plus - STM32 | 0x1B4F:0x002C | https://www.sparkfun.com/products/17712 | +| stm32f401_blackpill | STM32 STM32F401CxUx | 0x239A:0x005D | https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0.html | +| stm32f411ce_blackpill | ST STM32F411 BlackPill | 0x239A:0x0069 | https://www.adafruit.com/product/4877 | +| stm32f411ve_discovery | ST STM32F411 Discovery | 0x239A:0x005D | https://www.st.com/en/evaluation-tools/32f411ediscovery.html | + +## stm32h5 + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| stm32h503_coreboard | ST TinyUF2 for STM32H5 | 0x239A:0x0163 | https://github.com/WeActStudio/WeActStudio.STM32H503CoreBoard | +| stm32h503_nucleo | ST TinyUF2 for STM32H5 | 0x239A:0x0163 | https://www.st.com/en/evaluation-tools/nucleo-h503rb.html | +| stm32h563_nucleo | ST TinyUF2 for STM32H5 | 0x239A:0x0163 | https://www.st.com/en/evaluation-tools/nucleo-h563zi.html | + +## stm32h7 + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| daisy_seed | STM32 STM32FH750IB | 0x0483:0x5740 | https://electro-smith.com/products/daisy-seed | +| mini_stm32h750_v11 | STM32 STM32FH750VBT6 | 0x239A:0x005D | https://github.com/WeActStudio/MiniSTM32H7xx | + +## stm32l4 + +| Board | Name | VID PID | URL | +| --- | --- | --- | --- | +| swan_r5 | Blues Inc. Swan R5 | 0x30A4:0x0002 | https://blues.io/blog/introducing-swan-from-blues-wireless/ | diff --git a/tools/gen_boards.py b/tools/gen_boards.py new file mode 100644 index 000000000..dd65dbe2d --- /dev/null +++ b/tools/gen_boards.py @@ -0,0 +1,125 @@ +#!/usr/bin/env python3 +from __future__ import annotations + +import argparse +import re +from pathlib import Path + + +BOARD_H_GLOB = "ports/*/boards/*/board.h" +SKIP_FAMILIES = {"test_ghostfat", "template_port"} +SKIP_BOARDS = {"ch32v203_r0_1v0"} + + +def _first_match(pattern: str, text: str) -> str | None: + match = re.search(pattern, text, flags=re.MULTILINE) + return match.group(1).strip() if match else None + + +def _parse_int(value: str | None) -> int | None: + if value is None: + return None + value = value.strip() + if value.lower().startswith("0x"): + try: + return int(value, 16) + except ValueError: + return None + try: + return int(value, 10) + except ValueError: + return None + + +def _fmt_vid_pid(vid: int | None, pid: int | None) -> str: + if vid is None or pid is None: + return "N/A" + return f"0x{vid:04X}:0x{pid:04X}" + + +def _escape_md(value: str) -> str: + return value.replace("|", "\\|") + + +def _load_board(board_h: Path, repo_root: Path) -> dict[str, str]: + text = board_h.read_text(errors="ignore") + rel = board_h.relative_to(repo_root) + parts = rel.parts + family = parts[1] if len(parts) >= 4 else "unknown" + board = parts[3] if len(parts) >= 4 else board_h.parent.name + + if family in SKIP_FAMILIES or board in SKIP_BOARDS: + return {} + + vid = _parse_int(_first_match(r"^\s*#define\s+USB_VID\s+([0-9A-Fa-fxX]+)", text)) + pid = _parse_int(_first_match(r"^\s*#define\s+USB_PID\s+([0-9A-Fa-fxX]+)", text)) + manufacturer = _first_match(r'^\s*#define\s+USB_MANUFACTURER\s+"([^"]+)"', text) + product = _first_match(r'^\s*#define\s+USB_PRODUCT\s+"([^"]+)"', text) + name = None + if manufacturer and product: + name = f"{manufacturer} {product}" + elif product: + name = product + elif manufacturer: + name = manufacturer + else: + name = _first_match(r'^\s*#define\s+UF2_PRODUCT_NAME\s+"([^"]+)"', text) + + url = _first_match(r'^\s*#define\s+UF2_INDEX_URL\s+"([^"]+)"', text) + + return { + "family": family, + "board": board, + "name": name or "N/A", + "vid_pid": _fmt_vid_pid(vid, pid), + "url": url or "N/A", + } + + +def generate(repo_root: Path, output: Path) -> None: + boards: dict[str, list[dict[str, str]]] = {} + for board_h in sorted(repo_root.glob(BOARD_H_GLOB)): + entry = _load_board(board_h, repo_root) + if not entry: + continue + boards.setdefault(entry["family"], []).append(entry) + + lines: list[str] = [] + lines.append("# Supported Boards") + lines.append("") + for family in sorted(boards.keys(), key=str.lower): + lines.append(f"## {family}") + lines.append("") + lines.append("| Board | Name | VID PID | URL |") + lines.append("| --- | --- | --- | --- |") + for entry in sorted(boards[family], key=lambda e: e["board"].lower()): + lines.append( + f"| {_escape_md(entry['board'])} | {_escape_md(entry['name'])} | " + f"{_escape_md(entry['vid_pid'])} | {_escape_md(entry['url'])} |" + ) + lines.append("") + + output.write_text("\n".join(lines)) + + +def main() -> None: + parser = argparse.ArgumentParser( + description="Generate supported_boards.md from ports/*/boards/*/board.h" + ) + parser.add_argument( + "--output", + default="supported_boards.md", + help="Output markdown file (default: supported_boards.md)", + ) + args = parser.parse_args() + + repo_root = Path(__file__).resolve().parents[1] + output = Path(args.output) + if not output.is_absolute(): + output = repo_root / output + + generate(repo_root, output) + + +if __name__ == "__main__": + main()