Skip to content

Commit c0fbed6

Browse files
author
Victor Do Nascimento
committed
aarch64: Add xs variants of tlbip operands
The 2020 Architecture Extensions to the Arm A-profile architecture added FEAT_XS, the XS attribute feature, giving cores the ability to identify devices which can be subject to long response delays. TLB invalidate (TLBI) operations and barriers can also be annotated with this attribute[1]. With the introduction of the 128-bit translation tables with the Armv8.9-a/Armv9.4-a Translation Hardening Extension, a series of new TLB invalidate operations are introduced which make use of this extension. These are added to aarch64_sys_regs_tlbi[] for use with the `tlbip' insn. [1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2020
1 parent a9e2cef commit c0fbed6

File tree

2 files changed

+125
-0
lines changed

2 files changed

+125
-0
lines changed

‎opcodes/aarch64-opc.c‎

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4919,6 +4919,67 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
49194919
{ "paallos", CPENS (6, C8, C1, 4), 0},
49204920
{ "paall", CPENS (6, C8, C7, 4), 0},
49214921

4922+
{ "vae1osnxs", CPENS (0, C9, C1, 1), F_HASXT | F_ARCHEXT },
4923+
{ "vaae1osnxs", CPENS (0, C9, C1, 3), F_HASXT | F_ARCHEXT },
4924+
{ "vale1osnxs", CPENS (0, C9, C1, 5), F_HASXT | F_ARCHEXT },
4925+
{ "vaale1osnxs", CPENS (0, C9, C1, 7), F_HASXT | F_ARCHEXT },
4926+
{ "rvae1isnxs", CPENS (0, C9, C2, 1), F_HASXT | F_ARCHEXT },
4927+
{ "rvaae1isnxs", CPENS (0, C9, C2, 3), F_HASXT | F_ARCHEXT },
4928+
{ "rvale1isnxs", CPENS (0, C9, C2, 5), F_HASXT | F_ARCHEXT },
4929+
{ "rvaale1isnxs", CPENS (0, C9, C2, 7), F_HASXT | F_ARCHEXT },
4930+
{ "vae1isnxs", CPENS (0, C9, C3, 1), F_HASXT },
4931+
{ "vaae1isnxs", CPENS (0, C9, C3, 3), F_HASXT },
4932+
{ "vale1isnxs", CPENS (0, C9, C3, 5), F_HASXT },
4933+
{ "vaale1isnxs", CPENS (0, C9, C3, 7), F_HASXT },
4934+
{ "rvae1osnxs", CPENS (0, C9, C5, 1), F_HASXT | F_ARCHEXT },
4935+
{ "rvaae1osnxs", CPENS (0, C9, C5, 3), F_HASXT | F_ARCHEXT },
4936+
{ "rvale1osnxs", CPENS (0, C9, C5, 5), F_HASXT | F_ARCHEXT },
4937+
{ "rvaale1osnxs", CPENS (0, C9, C5, 7), F_HASXT | F_ARCHEXT },
4938+
{ "rvae1nxs", CPENS (0, C9, C6, 1), F_HASXT | F_ARCHEXT },
4939+
{ "rvaae1nxs", CPENS (0, C9, C6, 3), F_HASXT | F_ARCHEXT },
4940+
{ "rvale1nxs", CPENS (0, C9, C6, 5), F_HASXT | F_ARCHEXT },
4941+
{ "rvaale1nxs", CPENS (0, C9, C6, 7), F_HASXT | F_ARCHEXT },
4942+
{ "vae1nxs", CPENS (0, C9, C7, 1), F_HASXT },
4943+
{ "vaae1nxs", CPENS (0, C9, C7, 3), F_HASXT },
4944+
{ "vale1nxs", CPENS (0, C9, C7, 5), F_HASXT },
4945+
{ "vaale1nxs", CPENS (0, C9, C7, 7), F_HASXT },
4946+
{ "ipas2e1isnxs", CPENS (4, C9, C0, 1), F_HASXT },
4947+
{ "ripas2e1isnxs", CPENS (4, C9, C0, 2), F_HASXT | F_ARCHEXT },
4948+
{ "ipas2le1isnxs", CPENS (4, C9, C0, 5), F_HASXT },
4949+
{ "ripas2le1isnxs", CPENS (4, C9, C0, 6), F_HASXT | F_ARCHEXT },
4950+
{ "vae2osnxs", CPENS (4, C9, C1, 1), F_HASXT | F_ARCHEXT },
4951+
{ "vale2osnxs", CPENS (4, C9, C1, 5), F_HASXT | F_ARCHEXT },
4952+
{ "rvae2isnxs", CPENS (4, C9, C2, 1), F_HASXT | F_ARCHEXT },
4953+
{ "rvale2isnxs", CPENS (4, C9, C2, 5), F_HASXT | F_ARCHEXT },
4954+
{ "vae2isnxs", CPENS (4, C9, C3, 1), F_HASXT },
4955+
{ "vale2isnxs", CPENS (4, C9, C3, 5), F_HASXT },
4956+
{ "ipas2e1osnxs", CPENS (4, C9, C4, 0), F_HASXT | F_ARCHEXT },
4957+
{ "ipas2e1nxs", CPENS (4, C9, C4, 1), F_HASXT },
4958+
{ "ripas2e1nxs", CPENS (4, C9, C4, 2), F_HASXT | F_ARCHEXT },
4959+
{ "ripas2e1osnxs", CPENS (4, C9, C4, 3), F_HASXT | F_ARCHEXT },
4960+
{ "ipas2le1osnxs", CPENS (4, C9, C4, 4), F_HASXT | F_ARCHEXT },
4961+
{ "ipas2le1nxs", CPENS (4, C9, C4, 5), F_HASXT },
4962+
{ "ripas2le1nxs", CPENS (4, C9, C4, 6), F_HASXT | F_ARCHEXT },
4963+
{ "ripas2le1osnxs", CPENS (4, C9, C4, 7), F_HASXT | F_ARCHEXT },
4964+
{ "rvae2osnxs", CPENS (4, C9, C5, 1), F_HASXT | F_ARCHEXT },
4965+
{ "rvale2osnxs", CPENS (4, C9, C5, 5), F_HASXT | F_ARCHEXT },
4966+
{ "rvae2nxs", CPENS (4, C9, C6, 1), F_HASXT | F_ARCHEXT },
4967+
{ "rvale2nxs", CPENS (4, C9, C6, 5), F_HASXT | F_ARCHEXT },
4968+
{ "vae2nxs", CPENS (4, C9, C7, 1), F_HASXT },
4969+
{ "vale2nxs", CPENS (4, C9, C7, 5), F_HASXT },
4970+
{ "vae3osnxs", CPENS (6, C9, C1, 1), F_HASXT | F_ARCHEXT },
4971+
{ "vale3osnxs", CPENS (6, C9, C1, 5), F_HASXT | F_ARCHEXT },
4972+
{ "rvae3isnxs", CPENS (6, C9, C2, 1), F_HASXT | F_ARCHEXT },
4973+
{ "rvale3isnxs", CPENS (6, C9, C2, 5), F_HASXT | F_ARCHEXT },
4974+
{ "vae3isnxs", CPENS (6, C9, C3, 1), F_HASXT },
4975+
{ "vale3isnxs", CPENS (6, C9, C3, 5), F_HASXT },
4976+
{ "rvae3osnxs", CPENS (6, C9, C5, 1), F_HASXT | F_ARCHEXT },
4977+
{ "rvale3osnxs", CPENS (6, C9, C5, 5), F_HASXT | F_ARCHEXT },
4978+
{ "rvae3nxs", CPENS (6, C9, C6, 1), F_HASXT | F_ARCHEXT },
4979+
{ "rvale3nxs", CPENS (6, C9, C6, 5), F_HASXT | F_ARCHEXT },
4980+
{ "vae3nxs", CPENS (6, C9, C7, 1), F_HASXT },
4981+
{ "vale3nxs", CPENS (6, C9, C7, 5), F_HASXT },
4982+
49224983
{ 0, CPENS(0,0,0,0), 0 }
49234984
};
49244985

@@ -5043,6 +5104,69 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
50435104
&& AARCH64_CPU_HAS_FEATURE (features, MEMTAG))
50445105
return true;
50455106

5107+
if ((reg_value == CPENS (0, C9, C1, 1)
5108+
|| reg_value == CPENS (0, C9, C1, 3)
5109+
|| reg_value == CPENS (0, C9, C1, 5)
5110+
|| reg_value == CPENS (0, C9, C1, 7)
5111+
|| reg_value == CPENS (0, C9, C2, 1)
5112+
|| reg_value == CPENS (0, C9, C2, 3)
5113+
|| reg_value == CPENS (0, C9, C2, 5)
5114+
|| reg_value == CPENS (0, C9, C2, 7)
5115+
|| reg_value == CPENS (0, C9, C3, 1)
5116+
|| reg_value == CPENS (0, C9, C3, 3)
5117+
|| reg_value == CPENS (0, C9, C3, 5)
5118+
|| reg_value == CPENS (0, C9, C3, 7)
5119+
|| reg_value == CPENS (0, C9, C5, 1)
5120+
|| reg_value == CPENS (0, C9, C5, 3)
5121+
|| reg_value == CPENS (0, C9, C5, 5)
5122+
|| reg_value == CPENS (0, C9, C5, 7)
5123+
|| reg_value == CPENS (0, C9, C6, 1)
5124+
|| reg_value == CPENS (0, C9, C6, 3)
5125+
|| reg_value == CPENS (0, C9, C6, 5)
5126+
|| reg_value == CPENS (0, C9, C6, 7)
5127+
|| reg_value == CPENS (0, C9, C7, 1)
5128+
|| reg_value == CPENS (0, C9, C7, 3)
5129+
|| reg_value == CPENS (0, C9, C7, 5)
5130+
|| reg_value == CPENS (0, C9, C7, 7)
5131+
|| reg_value == CPENS (4, C9, C0, 1)
5132+
|| reg_value == CPENS (4, C9, C0, 2)
5133+
|| reg_value == CPENS (4, C9, C0, 5)
5134+
|| reg_value == CPENS (4, C9, C0, 6)
5135+
|| reg_value == CPENS (4, C9, C1, 1)
5136+
|| reg_value == CPENS (4, C9, C1, 5)
5137+
|| reg_value == CPENS (4, C9, C2, 1)
5138+
|| reg_value == CPENS (4, C9, C2, 5)
5139+
|| reg_value == CPENS (4, C9, C3, 1)
5140+
|| reg_value == CPENS (4, C9, C3, 5)
5141+
|| reg_value == CPENS (4, C9, C4, 0)
5142+
|| reg_value == CPENS (4, C9, C4, 1)
5143+
|| reg_value == CPENS (4, C9, C4, 2)
5144+
|| reg_value == CPENS (4, C9, C4, 3)
5145+
|| reg_value == CPENS (4, C9, C4, 4)
5146+
|| reg_value == CPENS (4, C9, C4, 5)
5147+
|| reg_value == CPENS (4, C9, C4, 6)
5148+
|| reg_value == CPENS (4, C9, C4, 7)
5149+
|| reg_value == CPENS (4, C9, C5, 1)
5150+
|| reg_value == CPENS (4, C9, C5, 5)
5151+
|| reg_value == CPENS (4, C9, C6, 1)
5152+
|| reg_value == CPENS (4, C9, C6, 5)
5153+
|| reg_value == CPENS (4, C9, C7, 1)
5154+
|| reg_value == CPENS (4, C9, C7, 5)
5155+
|| reg_value == CPENS (6, C9, C1, 1)
5156+
|| reg_value == CPENS (6, C9, C1, 5)
5157+
|| reg_value == CPENS (6, C9, C2, 1)
5158+
|| reg_value == CPENS (6, C9, C2, 5)
5159+
|| reg_value == CPENS (6, C9, C3, 1)
5160+
|| reg_value == CPENS (6, C9, C3, 5)
5161+
|| reg_value == CPENS (6, C9, C5, 1)
5162+
|| reg_value == CPENS (6, C9, C5, 5)
5163+
|| reg_value == CPENS (6, C9, C6, 1)
5164+
|| reg_value == CPENS (6, C9, C6, 5)
5165+
|| reg_value == CPENS (6, C9, C7, 1)
5166+
|| reg_value == CPENS (6, C9, C7, 5))
5167+
&& AARCH64_CPU_HAS_FEATURE (features, D128))
5168+
return true;
5169+
50465170
/* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
50475171
if ((reg_value == CPENS (0, C7, C9, 0)
50485172
|| reg_value == CPENS (0, C7, C9, 1))

‎opcodes/aarch64-opc.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -300,6 +300,7 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
300300
#undef F_REG_128
301301
#define F_REG_128 (1 << 7) /* System regsister implementable as 128-bit wide. */
302302

303+
303304
/* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
304305
Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
305306
In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below

0 commit comments

Comments
 (0)