sw-sysemu: Inject interrupts via validation1 in DV context

[vidas]

Sysemu has several "virtual" (not present in silicon) validation registers that provide support during testing.

VALIDATION1 serves several functions, one of which is raising external interrupt, but it's only enabled in standalone (SYS_EMU defined) build. Also, it triggers external interrupt directly on CPU, bypassing the PLIC

et-platform/sw-sysemu/insns/zicsr.cpp

Line 1232 in 2cbce83

case ET_DIAG_IRQ_INJ:

This functionality is used by DV on rtl emulator, and would be great to have it in sysemu/cosim context too.

Requested behavior: when user writes ET_DIAG_IRQ_INJ (0x5) together with subopcode (ET_DIAG_IRQ_INJ_MEI, ET_DIAG_IRQ_INJ_TI, ET_DIAG_IRQ_INJ_SEI), corresponding interrupt should be raised/cleared via PLIC (so that PLIC registers represent true situation). This should work when SYS_EMU is not defined. Q: Do we want to keep existing behavior when SYS_EMU is defined?

Note: I think on Erbium rvtimer interrupt does not go through PLIC, please verify.

[AFOliveira]

@yhxln Do you have a solution for this on the DV-only side? Or is it something that would still be nice to have?