2121#include "airspy_conf.h"
2222
2323#define AIRSPY_CONF_M0_M4_NB (2)
24- #define AIRSPY_CONF_M0_M4_ALT_NB (2 )
24+ #define AIRSPY_CONF_M0_M4_ALT_NB (3 )
2525#define AIRSPY_CONF_SI5351C_NB (2)
2626#define NULL_ADDR (0)
2727
@@ -98,7 +98,7 @@ airspy_nos_conf_t __attribute__ ((section(".nocopy_data"))) airspy_nos_conf =
9898 /* r820t_priv_t r820t_conf_rw = */
9999 {
100100 20000000 , // xtal_freq => 20MHz
101- 5000000 , // Freq 20MHz => 10Mhz IQ => IF Freq = 5MHz ( r820t_if_freq)
101+ 0 , // Set at boot to airspy_m0_m4_conf_t conf0 -> r820t_if_freq
102102 100000000 , /* Default Freq 100Mhz */
103103 {
104104 /* 05 */ 0x90 , // LNA manual gain mode, init to 0
@@ -150,7 +150,7 @@ airspy_nos_conf_t __attribute__ ((section(".nocopy_data"))) airspy_nos_conf =
150150
151151 /* 1st Expansion Conf Point M0/M4 Data */
152152 /*
153- SampleRate configuration with GP_CLKIN=20MHz
153+ SampleRate configuration with GP_CLKIN=20MHz from SI5351C CLK7 LPC4370 GP_CLKIN
154154 Configuration of PLL0AUDIO shall not exceed 80MHz for ADCHS
155155 For PLL0AUDIO sys_clock_samplerate() set SEL_EXT to 1 => MDEC enabled. Fractional divider not used.
156156 For PLL0AUDIO see UM10503 Rev1.8 "Fig 34. PLL0 with fractional divider" Page 184 / 1420 for more details.
@@ -161,7 +161,6 @@ airspy_nos_conf_t __attribute__ ((section(".nocopy_data"))) airspy_nos_conf =
161161 /* Conf 0 => 10 MSPS */
162162 {
163163 /*
164- CGU_SRC_GP_CLKIN=20MHz from SI5351C CLK7 LPC4370 GP_CLKIN
165164 airspy_sys_samplerate_t airspy_m4_conf
166165 */
167166 {
@@ -207,55 +206,76 @@ airspy_nos_conf_t __attribute__ ((section(".nocopy_data"))) airspy_nos_conf =
207206
208207 /* 2nd Expansion Conf Point M0/M4 ALT Data */
209208 /*
210- SampleRate configuration with GP_CLKIN=20MHz
209+ SampleRate configuration with GP_CLKIN=20MHz from SI5351C CLK7 LPC4370 GP_CLKIN
211210 Configuration of PLL0AUDIO shall not exceed 80MHz for ADCHS
212211 For PLL0AUDIO sys_clock_samplerate() set SEL_EXT to 1 => MDEC enabled. Fractional divider not used.
213212 For PLL0AUDIO see UM10503 Rev1.8 "Fig 34. PLL0 with fractional divider" Page 184 / 1420 for more details.
214213 Configuration of IDIVB => Integer divider B divider values (1/(IDIV + 1))
215214 */
216215 /* const airspy_m0_m4_conf_t airspy_m0_m4_alt_conf[AIRSPY_CONF_M0_M4_ALT_NB] = */
217216 {
218- /* Conf 0 => 10 MSPS */
217+ /* Conf 0 => 12 MSPS */
219218 {
220219 /*
221- CGU_SRC_GP_CLKIN=20MHz from SI5351C CLK7 LPC4370 GP_CLKIN
222220 airspy_sys_samplerate_t airspy_m4_conf
223221 */
224222 {
225223 /* PLL0AUDIO */
226- 0x00000000 , // uint32_t pll0audio_mdiv;
227- 0x00000000 , // uint32_t pll0audio_npdiv;
228- 0x00000000 , // uint32_t pll0audio_ctrl_flags; DirectI=PLL0AUDIO_CTRL_FLAG_DIRECT_I or/and DirectO=PLL0AUDIO_CTRL_FLAG_DIRECT_O */
229- /* IDIVB (from GP_CLKIN) */
224+ 0x000003FF , // uint32_t pll0audio_mdiv;
225+ 0x0000000E , // uint32_t pll0audio_npdiv;
226+ PLL0AUDIO_CTRL_FLAG_DIRECT_I , // uint32_t pll0audio_ctrl_flags; DirectI=PLL0AUDIO_CTRL_FLAG_DIRECT_I or/and DirectO=PLL0AUDIO_CTRL_FLAG_DIRECT_O */
227+ /* IDIVB not used set it to 0 */
230228 0 , // uint8_t adchs_idivb; /* 0 to 15 (0 means direct connection GP_CLKIN to ADCHS_CLK) */
231229 { 0 , 0 , 0 } /* uint8_t padding[3] */
232230 },
233231 /* airspy_m0_conf_t airspy_m0_conf */
234232 {
235- 5000000 , // Freq 20MHz => 10MHz IQ => IF Freq = 5MHz (r820t_if_freq)
236- 59 , // uint8_t r820t_bw;
233+ 6000000 , // Freq 24MHz => 12MHz IQ => IF Freq = 6MHz (r820t_if_freq)
234+ 63 , // uint8_t r820t_bw;
237235 0 ,// uint8_t padding0;
238236 0 // uint16_t padding1;
239237 }
240238 },
241- /* Conf 1 => 2.5 MSPS */
239+ /* Conf 1 => 6 MSPS */
242240 {
243241 /*
244242 airspy_sys_samplerate_t airspy_m4_conf
245243 */
246244 {
247245 /* PLL0AUDIO */
248- 0x00000000 , // uint32_t pll0audio_mdiv;
249- 0x00000000 , // uint32_t pll0audio_npdiv;
246+ 0x0000007F , // uint32_t pll0audio_mdiv;
247+ 0x00000018 , // uint32_t pll0audio_npdiv;
248+ PLL0AUDIO_CTRL_FLAG_DIRECT_I , // uint32_t pll0audio_ctrl_flags; DirectI=PLL0AUDIO_CTRL_FLAG_DIRECT_I or/and DirectO=PLL0AUDIO_CTRL_FLAG_DIRECT_O */
249+ /* IDIVB not used set it to 0 */
250+ 0 , // uint8_t adchs_idivb; /* 0 to 15 (0 means direct connection GP_CLKIN to ADCHS_CLK) */
251+ { 0 , 0 , 0 } /* uint8_t padding[3] */
252+ },
253+ /* airspy_m0_conf_t airspy_m0_conf */
254+ {
255+ 3000000 , // Freq 12MHz => 6MHz IQ => IF Freq = 3MHz (r820t_if_freq)
256+ 32 , // uint8_t r820t_bw;
257+ 0 ,// uint8_t padding0;
258+ 0 // uint16_t padding1;
259+ }
260+ },
261+ /* Conf 2 => 4.096 MSPS */
262+ {
263+ /*
264+ airspy_sys_samplerate_t airspy_m4_conf
265+ */
266+ {
267+ /* PLL0AUDIO */
268+ 0x00004924 , // uint32_t pll0audio_mdiv;
269+ 0x0003F006 , // uint32_t pll0audio_npdiv;
250270 0x00000000 , // uint32_t pll0audio_ctrl_flags; DirectI=PLL0AUDIO_CTRL_FLAG_DIRECT_I or/and DirectO=PLL0AUDIO_CTRL_FLAG_DIRECT_O */
251271 /* IDIVB not used set it to 0 */
252- 3 , // uint8_t adchs_idivb; /* 0 to 15 (0 means direct connection GP_CLKIN to ADCHS_CLK) */
272+ 0 , // uint8_t adchs_idivb; /* 0 to 15 (0 means direct connection GP_CLKIN to ADCHS_CLK) */
253273 { 0 , 0 , 0 } /* uint8_t padding[3] */
254274 },
255275 /* airspy_m0_conf_t airspy_m0_conf */
256276 {
257- 1250000 , // Freq 5MHz => 2.5MHz IQ => IF Freq = 1.25MHz (r820t_if_freq)
258- 0 , // uint8_t r820t_bw;
277+ 2048000 , // Freq 8.192MHz => 4.096MHz IQ => IF Freq = 2.048MHz (r820t_if_freq)
278+ 25 , // uint8_t r820t_bw;
259279 0 , // uint8_t padding0;
260280 0 // uint16_t padding1;
261281 }
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