Merge branch 'master' into JDK-8353196-full

Author: alexeysemenyukoracle

make/autoconf/toolchain.m4

@@ -622,7 +622,7 @@ AC_DEFUN_ONCE([TOOLCHAIN_DETECT_TOOLCHAIN_CORE],
     LDCXX="$CXX"
     # Force use of lld, since that is what we expect when setting flags later on
     if test "x$TOOLCHAIN_TYPE" = xclang; then
-      if test "x$OPENJDK_BUILD_OS" != "xmacosx"; then
+      if test "x$OPENJDK_TARGET_OS" = xlinux; then
         LD="$LD -fuse-ld=lld"
         LDCXX="$LDCXX -fuse-ld=lld"
       fi

make/ide/vscode/hotspot/indexers/ccls-settings.txt

@@ -22,7 +22,7 @@
 		],
 
 		// Disable conflicting features from cpptools
-		"C_Cpp.autocomplete": "Disabled",
-		"C_Cpp.errorSquiggles": "Disabled",
-		"C_Cpp.formatting": "Disabled",
-		"C_Cpp.intelliSenseEngine": "Disabled",
+		"C_Cpp.autocomplete": "disabled",
+		"C_Cpp.errorSquiggles": "disabled",
+		"C_Cpp.formatting": "disabled",
+		"C_Cpp.intelliSenseEngine": "disabled",

make/ide/vscode/hotspot/indexers/clangd-settings.txt

@@ -11,7 +11,7 @@
 		],
 
 		// Disable conflicting features from cpptools
-		"C_Cpp.autocomplete": "Disabled",
-		"C_Cpp.errorSquiggles": "Disabled",
-		"C_Cpp.formatting": "Disabled",
-		"C_Cpp.intelliSenseEngine": "Disabled",
+		"C_Cpp.autocomplete": "disabled",
+		"C_Cpp.errorSquiggles": "disabled",
+		"C_Cpp.formatting": "disabled",
+		"C_Cpp.intelliSenseEngine": "disabled",

make/ide/vscode/hotspot/indexers/rtags-settings.txt

@@ -8,7 +8,7 @@
 		"rtags.misc.compilationDatabaseDirectory": "{{OUTPUTDIR}}",
 
 		// Disable conflicting features from cpptools
-		"C_Cpp.autocomplete": "Disabled",
-		"C_Cpp.errorSquiggles": "Disabled",
-		"C_Cpp.formatting": "Disabled",
-		"C_Cpp.intelliSenseEngine": "Disabled",
+		"C_Cpp.autocomplete": "disabled",
+		"C_Cpp.errorSquiggles": "disabled",
+		"C_Cpp.formatting": "disabled",
+		"C_Cpp.intelliSenseEngine": "disabled",

src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp

@@ -584,14 +584,14 @@ void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
       else {
         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
-        reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
+        reg2stack(FrameMap::rscratch1_opr, dest, c->type());
       }
     }
     break;
   case T_ADDRESS:
     {
       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
-      reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
+      reg2stack(FrameMap::rscratch1_opr, dest, c->type());
     }
   case T_INT:
   case T_FLOAT:
@@ -716,7 +716,7 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
   }
 }
 
-void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
+void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
   precond(src->is_register() && dest->is_stack());
 
   uint const c_sz32 = sizeof(uint32_t);
@@ -752,7 +752,7 @@ void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool po
 }
 
 
-void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
+void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
   LIR_Address* to_addr = dest->as_address_ptr();
   PatchingStub* patch = nullptr;
   Register compressed_src = rscratch1;
@@ -905,7 +905,7 @@ void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
     temp = FrameMap::rscratch1_opr;
 
   stack2reg(src, temp, src->type());
-  reg2stack(temp, dest, dest->type(), false);
+  reg2stack(temp, dest, dest->type());
 }
 
 
@@ -1598,7 +1598,7 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L
     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
 }
 
-void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
+void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
   assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
 
   if (left->is_single_cpu()) {
@@ -1769,9 +1769,6 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
   }
 }
 
-void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
-
-
 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
   switch(code) {
   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
@@ -2849,8 +2846,7 @@ void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* arg
 
 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
   if (dest->is_address() || src->is_address()) {
-    move_op(src, dest, type, lir_patch_none, info,
-            /*pop_fpu_stack*/false, /*wide*/false);
+    move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
   } else {
     ShouldNotReachHere();
   }

src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.hpp

@@ -33,8 +33,6 @@ friend class ArrayCopyStub;
 
   int array_element_size(BasicType type) const;
 
-  void arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack);
-
   // helper functions which checks for overflow and sets bailout if it
   // occurs.  Always returns a valid embeddable pointer but in the
   // bailout case the pointer won't be to unique storage.