initializing AXIL instances defined as unpacked SystemVerilog

[jhuryszblvt]

My default way to initialize a new AXIL Master is the following:

axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "axil_if"), dut.clk, dut.rst)

However, let's say I have axil_if declared as:

logic axil_if_(signal)[5];

Is their a way to create 5 unique instances of axil_master_<0-5>, without breaking apart the signal declaration into seperate declarations? i.e axil_if_0, axil_if_1 etc.