Add example when using directionally split records for the bus

[timkoers]

I've gotten directionally splitted bus records to work with the components in this package.

Since our feedback signals live inside another record (with a different signal direction), I needed to use some Python trickery (shallow copy) to get that to work.

Below is an example of record mapping of an AXI4-Stream where the feedback signal lives in another signal.

import copy

stream_bus = AxiStreamBus.from_prefix(dut.axi_mosi, "")
stream_bus.tready = copy.copy(dut.axi_miso.tready)

You can then just initialize a source/sink/whatever as normal and use this.

This also works for AXI4 records, but require more shallow copies as, for each channel, you'd have to create a single structure that contains both incoming and outgoing signals for that channel.
This is also verified to work by using it with an AxiRam.

[peteut]

Neat trick, works for me. Thanks @timkoers!
The signals should be assigned using bus._add_signal:

def get_axilite_bus(dut) -> AxiLiteBus:
    ar_bus = AxiLiteARBus.from_prefix(dut, "AxiReadMaster")
    ar_bus._add_signal("arready", "AxiReadSlave_ARready")
    r_bus = AxiLiteRBus.from_prefix(dut, "AxiReadSlave")
    r_bus._add_signal("rready", "AxiReadMaster_Rready")
    aw_bus = AxiLiteAWBus.from_prefix(dut, "AxiWriteMaster")
    aw_bus._add_signal("awready", "AxiWriteSlave_AWready")
    w_bus = AxiLiteWBus.from_prefix(dut, "AxiWriteMaster")
    w_bus._add_signal("wready", "AxiWriteSlave_Wready")
    b_bus = AxiLiteBBus.from_prefix(dut, "AxiWriteSlave")
    b_bus._add_signal("bready", "AxiWriteMaster_Bready")

    return AxiLiteBus(
        AxiLiteWriteBus.from_channels(aw_bus, w_bus, b_bus),
        AxiLiteReadBus.from_channels(ar_bus, r_bus),
    )