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Simulation gets stuck with SIM=verilator 4.106 #35

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#37
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Simulation gets stuck with SIM=verilator 4.106#35
#37
@andreaskuster

Description

@andreaskuster
andreaskuster
opened on Jan 19, 2022

Thanks a lot for this great project! @alexforencich @rodrigomelo9

I am trying to run the axi-verilog designs using verilator, however, this library does not seem to be compatible with verilator. I use version 4.106 which should be compatible with cocotb (all their base examples work).

However, it seems as if the simulation tests are stuck here: https://github.com/alexforencich/cocotbext-axi/blob/master/cocotbext/axi/axi_master.py#L413

Commands for reproduction:

python3 -m pip install cocotbext-axi==0.1.18
git clone https://github.com/alexforencich/cocotbext-axi.git
cd cocotbext-axi/tests/axi/
git checkout v0.1.18
SIM=verilator make

running make without SIM=verilator works

The log for the axi test is:

make -f Makefile results.xml
make[1]: Entering directory '/home/andreas/Desktop/cocotbext-axi/tests/axi'
MODULE=test_axi TESTCASE= TOPLEVEL=test_axi TOPLEVEL_LANG=verilog \
         sim_build/Vtop 
     -.--ns INFO     cocotb.gpi                         ..mbed/gpi_embed.cpp:76   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     cocotb.gpi                         ../gpi/GpiCommon.cpp:99   in gpi_print_registered_impl       VPI registered
     0.00ns INFO     Running on Verilator version 4.106 2020-12-02
     0.00ns INFO     Running tests with cocotb v1.6.1 from /home/andreas/.local/lib/python3.8/site-packages/cocotb
     0.00ns INFO     Seeding Python random module with 1642601669
     0.00ns INFO     Found test test_axi.run_test_write_001
     0.00ns INFO     Found test test_axi.run_test_write_002
     0.00ns INFO     Found test test_axi.run_test_write_003
     0.00ns INFO     Found test test_axi.run_test_write_004
     0.00ns INFO     Found test test_axi.run_test_write_005
     0.00ns INFO     Found test test_axi.run_test_write_006
     0.00ns INFO     Found test test_axi.run_test_write_007
     0.00ns INFO     Found test test_axi.run_test_write_008
     0.00ns INFO     Found test test_axi.run_test_write_009
     0.00ns INFO     Found test test_axi.run_test_write_010
     0.00ns INFO     Found test test_axi.run_test_write_011
     0.00ns INFO     Found test test_axi.run_test_write_012
     0.00ns INFO     Found test test_axi.run_test_read_001
     0.00ns INFO     Found test test_axi.run_test_read_002
     0.00ns INFO     Found test test_axi.run_test_read_003
     0.00ns INFO     Found test test_axi.run_test_read_004
     0.00ns INFO     Found test test_axi.run_test_read_005
     0.00ns INFO     Found test test_axi.run_test_read_006
     0.00ns INFO     Found test test_axi.run_test_read_007
     0.00ns INFO     Found test test_axi.run_test_read_008
     0.00ns INFO     Found test test_axi.run_test_read_009
     0.00ns INFO     Found test test_axi.run_test_read_010
     0.00ns INFO     Found test test_axi.run_test_read_011
     0.00ns INFO     Found test test_axi.run_test_read_012
     0.00ns INFO     Found test test_axi.run_test_write_words_001
     0.00ns INFO     Found test test_axi.run_test_read_words_001
     0.00ns INFO     Found test test_axi.run_stress_test_001
     0.00ns INFO     running run_test_write_001 (1/27)
     0.00ns INFO     AXI master (write)
     0.00ns INFO     cocotbext-axi version 0.1.18
     0.00ns INFO     Copyright (c) 2020 Alex Forencich
     0.00ns INFO     https://github.com/alexforencich/cocotbext-axi
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     AXI master configuration:
     0.00ns INFO       Address width: 32 bits
     0.00ns INFO       ID width: 8 bits
     0.00ns INFO       Byte size: 8 bits
     0.00ns INFO       Data width: 32 bits (4 bytes)
     0.00ns INFO       Max burst size: 2 (4 bytes)
     0.00ns INFO       Max burst length: 256 cycles (1024 bytes)
     0.00ns INFO     AXI master signals:
     0.00ns INFO       awaddr width: 32 bits
     0.00ns INFO       awburst width: 2 bits
     0.00ns INFO       awcache width: 4 bits
     0.00ns INFO       awid width: 8 bits
     0.00ns INFO       awlen width: 8 bits
     0.00ns INFO       awlock width: 1 bits
     0.00ns INFO       awprot width: 3 bits
     0.00ns INFO       awqos width: 4 bits
     0.00ns INFO       awready width: 1 bits
     0.00ns INFO       awregion width: 4 bits
     0.00ns INFO       awsize width: 3 bits
     0.00ns INFO       awuser width: 1 bits
     0.00ns INFO       awvalid width: 1 bits
     0.00ns INFO       wdata width: 32 bits
     0.00ns INFO       wlast width: 1 bits
     0.00ns INFO       wready width: 1 bits
     0.00ns INFO       wstrb width: 4 bits
     0.00ns INFO       wuser width: 1 bits
     0.00ns INFO       wvalid width: 1 bits
     0.00ns INFO       bid width: 8 bits
     0.00ns INFO       bready width: 1 bits
     0.00ns INFO       bresp width: 2 bits
     0.00ns INFO       buser width: 1 bits
     0.00ns INFO       bvalid width: 1 bits
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     AXI master (read)
     0.00ns INFO     cocotbext-axi version 0.1.18
     0.00ns INFO     Copyright (c) 2020 Alex Forencich
     0.00ns INFO     https://github.com/alexforencich/cocotbext-axi
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     AXI master configuration:
     0.00ns INFO       Address width: 32 bits
     0.00ns INFO       ID width: 8 bits
     0.00ns INFO       Byte size: 8 bits
     0.00ns INFO       Data width: 32 bits (4 bytes)
     0.00ns INFO       Max burst size: 2 (4 bytes)
     0.00ns INFO       Max burst length: 256 cycles (1024 bytes)
     0.00ns INFO     AXI master signals:
     0.00ns INFO       araddr width: 32 bits
     0.00ns INFO       arburst width: 2 bits
     0.00ns INFO       arcache width: 4 bits
     0.00ns INFO       arid width: 8 bits
     0.00ns INFO       arlen width: 8 bits
     0.00ns INFO       arlock width: 1 bits
     0.00ns INFO       arprot width: 3 bits
     0.00ns INFO       arqos width: 4 bits
     0.00ns INFO       arready width: 1 bits
     0.00ns INFO       arregion width: 4 bits
     0.00ns INFO       arsize width: 3 bits
     0.00ns INFO       aruser width: 1 bits
     0.00ns INFO       arvalid width: 1 bits
     0.00ns INFO       rdata width: 32 bits
     0.00ns INFO       rid width: 8 bits
     0.00ns INFO       rlast width: 1 bits
     0.00ns INFO       rready width: 1 bits
     0.00ns INFO       rresp width: 2 bits
     0.00ns INFO       ruser width: 1 bits
     0.00ns INFO       rvalid width: 1 bits
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     AXI slave model (write)
     0.00ns INFO     cocotbext-axi version 0.1.18
     0.00ns INFO     Copyright (c) 2021 Alex Forencich
     0.00ns INFO     https://github.com/alexforencich/cocotbext-axi
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     AXI slave model configuration:
     0.00ns INFO       Address width: 32 bits
     0.00ns INFO       ID width: 8 bits
     0.00ns INFO       Byte size: 8 bits
     0.00ns INFO       Data width: 32 bits (4 bytes)
     0.00ns INFO     AXI slave model signals:
     0.00ns INFO       awaddr width: 32 bits
     0.00ns INFO       awburst width: 2 bits
     0.00ns INFO       awcache width: 4 bits
     0.00ns INFO       awid width: 8 bits
     0.00ns INFO       awlen width: 8 bits
     0.00ns INFO       awlock width: 1 bits
     0.00ns INFO       awprot width: 3 bits
     0.00ns INFO       awqos width: 4 bits
     0.00ns INFO       awready width: 1 bits
     0.00ns INFO       awregion width: 4 bits
     0.00ns INFO       awsize width: 3 bits
     0.00ns INFO       awuser width: 1 bits
     0.00ns INFO       awvalid width: 1 bits
     0.00ns INFO       wdata width: 32 bits
     0.00ns INFO       wlast width: 1 bits
     0.00ns INFO       wready width: 1 bits
     0.00ns INFO       wstrb width: 4 bits
     0.00ns INFO       wuser width: 1 bits
     0.00ns INFO       wvalid width: 1 bits
     0.00ns INFO       bid width: 8 bits
     0.00ns INFO       bready width: 1 bits
     0.00ns INFO       bresp width: 2 bits
     0.00ns INFO       buser width: 1 bits
     0.00ns INFO       bvalid width: 1 bits
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     AXI slave model (read)
     0.00ns INFO     cocotbext-axi version 0.1.18
     0.00ns INFO     Copyright (c) 2021 Alex Forencich
     0.00ns INFO     https://github.com/alexforencich/cocotbext-axi
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     Reset de-asserted
     0.00ns INFO     AXI slave model configuration:
     0.00ns INFO       Address width: 32 bits
     0.00ns INFO       ID width: 8 bits
     0.00ns INFO       Byte size: 8 bits
     0.00ns INFO       Data width: 32 bits (4 bytes)
     0.00ns INFO     AXI slave model signals:
     0.00ns INFO       araddr width: 32 bits
     0.00ns INFO       arburst width: 2 bits
     0.00ns INFO       arcache width: 4 bits
     0.00ns INFO       arid width: 8 bits
     0.00ns INFO       arlen width: 8 bits
     0.00ns INFO       arlock width: 1 bits
     0.00ns INFO       arprot width: 3 bits
     0.00ns INFO       arqos width: 4 bits
     0.00ns INFO       arready width: 1 bits
     0.00ns INFO       arregion width: 4 bits
     0.00ns INFO       arsize width: 3 bits
     0.00ns INFO       aruser width: 1 bits
     0.00ns INFO       arvalid width: 1 bits
     0.00ns INFO       rdata width: 32 bits
     0.00ns INFO       rid width: 8 bits
     0.00ns INFO       rlast width: 1 bits
     0.00ns INFO       rready width: 1 bits
     0.00ns INFO       rresp width: 2 bits
     0.00ns INFO       ruser width: 1 bits
     0.00ns INFO       rvalid width: 1 bits
     0.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
     2.00ns INFO     Reset de-asserted
    10.00ns INFO     length 1, offset 0
    10.00ns INFO     Write start addr: 0x00001000 awid: 0x0 prot: AxiProt.NONSECURE data: 00
    10.00ns INFO     Write burst start awid: 0x0 awaddr: 0x00001000 awlen: 0 awsize: 2 awprot: AxiProt.NONSECURE

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