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Commit 23142d1

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Clean up type casts
Signed-off-by: Alex Forencich <[email protected]>
1 parent 67aaa79 commit 23142d1

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2 files changed

+11
-11
lines changed

2 files changed

+11
-11
lines changed

cocotbext/i2c/i2c_device.py

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ def _set_scl(self, val):
7373
# self.scl.value = BinaryValue('z') if val else 0
7474

7575
async def _send_bit(self, b):
76-
if self.scl.value.integer:
76+
if int(self.scl.value):
7777
await FallingEdge(self.scl)
7878

7979
self._set_sda(bool(b))
@@ -88,19 +88,19 @@ async def _recv_bit(self):
8888
self._set_scl(1)
8989
self._set_sda(1)
9090

91-
if self.scl.value.integer:
91+
if int(self.scl.value):
9292
await First(FallingEdge(self.scl), RisingEdge(self.sda), FallingEdge(self.sda))
9393

94-
if self.scl.value.integer:
94+
if int(self.scl.value):
9595
# Got start or stop bit
96-
if self.sda.value.integer:
96+
if int(self.sda.value):
9797
return 'stop'
9898
else:
9999
return 'start'
100100

101101
await RisingEdge(self.scl)
102102

103-
return bool(self.sda.value.integer)
103+
return bool(int(self.sda.value))
104104

105105
async def _send_byte(self, b):
106106
for i in range(8):
@@ -133,7 +133,7 @@ async def _run(self):
133133

134134
await FallingEdge(self.sda)
135135

136-
if self.scl.value.integer:
136+
if int(self.scl.value):
137137
# start condition
138138
self.log.info("Got start bit")
139139
line_active = True

cocotbext/i2c/i2c_master.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ async def send_start(self):
7878
self._set_sda(1)
7979
await self._half_bit_t
8080
self._set_scl(1)
81-
while not self.scl.value:
81+
while not int(self.scl.value):
8282
await RisingEdge(self.scl)
8383
await self._half_bit_t
8484

@@ -96,7 +96,7 @@ async def send_stop(self):
9696
self._set_sda(0)
9797
await self._half_bit_t
9898
self._set_scl(1)
99-
while not self.scl.value:
99+
while not int(self.scl.value):
100100
await RisingEdge(self.scl)
101101
await self._half_bit_t
102102
self._set_sda(1)
@@ -111,7 +111,7 @@ async def send_bit(self, b):
111111
self._set_sda(bool(b))
112112
await self._half_bit_t
113113
self._set_scl(1)
114-
while not self.scl.value:
114+
while not int(self.scl.value):
115115
await RisingEdge(self.scl)
116116
await self._bit_t
117117
self._set_scl(0)
@@ -123,9 +123,9 @@ async def recv_bit(self):
123123

124124
self._set_sda(1)
125125
await self._half_bit_t
126-
b = bool(self.sda.value.integer)
126+
b = bool(int(self.sda.value))
127127
self._set_scl(1)
128-
while not self.scl.value:
128+
while not int(self.scl.value):
129129
await RisingEdge(self.scl)
130130
await self._bit_t
131131
self._set_scl(0)

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