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fpga/mqnic/ZCU102: Add 10G mqnic design for ZCU102
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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‎README.md‎

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@@ -41,6 +41,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
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* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
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* Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG)
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* Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV)
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For operation at 10G and 25G, Corundum uses the open source 10G/25G MAC and PHY modules from the verilog-ethernet repository, no extra licenses are required. However, it is possible to use other MAC and/or PHY modules.

‎docs/source/devicelist.rst‎

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============ ================= ==================== ==========
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Manufacturer Board FPGA Board ID
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============ ================= ==================== ==========
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Xilinx ZCU102 XCZU9EG-2FFVB1156E 0x10ee9066
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Xilinx ZCU106 XCZU7EV-2FFVC1156E 0x10ee906a
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============ ================= ==================== ==========
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================= ========= ========== =============================== =====
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Board PCIe IF Network IF DDR HBM
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================= ========= ========== =============================== =====
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ZCU102 \- 4x SFP+ 2 GB DDR4 2400 (256M x64) \-
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ZCU106 Gen 3 x4 2x SFP+ 2 GB DDR4 2400 (256M x64) \-
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================= ========= ========== =============================== =====
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================= ============ ============ ==========
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Board I2C :sup:`1` MAC :sup:`2` FW update
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================= ============ ============ ==========
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ZCU102 Y Y :sup:`3` N
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ZCU106 Y Y :sup:`3` N
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================= ============ ============ ==========
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================= ========================= ==== ======= ==== =====
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Board Design IFxP RXQ/TXQ MAC Sched
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================= ========================= ==== ======= ==== =====
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ZCU102 mqnic/fpga/fpga 2x1 32/32 10G RR
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ZCU106 mqnic/fpga_zynqmp/fpga 2x1 32/32 10G RR
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================= ========================= ==== ======= ==== =====

‎docs/source/index.rst‎

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* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
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* Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG)
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* Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV)
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Publications

‎fpga/mqnic/ZCU102/fpga/Makefile‎

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# Targets
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TARGETS:=
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# Subdirectories
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SUBDIRS = fpga
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SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
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# Rules
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.PHONY: all
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all: $(SUBDIRS) $(TARGETS)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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cd $@ && $(MAKE)
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.PHONY: $(SUBDIRS_CLEAN)
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$(SUBDIRS_CLEAN):
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cd $(@:.clean=) && $(MAKE) clean
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.PHONY: clean
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clean: $(SUBDIRS_CLEAN)
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-rm -rf $(TARGETS)
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program:
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#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit

‎fpga/mqnic/ZCU102/fpga/README.md‎

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# Corundum mqnic for ZCU102 using ZynqMP PS as host system
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## Introduction
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This design targets the Xilinx ZCU102 FPGA board. The host system of the NIC is
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the Zynq US+ MPSoC.
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FPGA: xczu9eg-ffvb1156-2-e
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PHY: 10G BASE-R PHY IP core and internal GTH transceiver
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## How to build
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Run make in this directory to build the bitstream and the .xsa
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file. Ensure that the Xilinx Vivado toolchain components are in PATH.
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Then change into sub-directory ps/petalinux/ and build the PetaLinux project.
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Ensure that the Xilinx PetaLinux toolchain components are in PATH.
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make -C ps/petalinux/ build-boot
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## How to test
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Copy the following, resulting files of building the PetaLinux project onto an
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SDcard suitable for then booting the ZCU102 in SDcard boot mode.
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ps/petalinux/images/linux/:
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BOOT.BIN
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boot.scr
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Image
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system.dtb
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rootfs.cpio.gz.u-boot

‎fpga/mqnic/ZCU102/fpga/app‎

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../../../app/

‎fpga/mqnic/ZCU102/fpga/common/vivado.mk‎

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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES))
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IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES))
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CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).bit
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vivado: $(FPGA_TOP).xpr
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vivado $(FPGA_TOP).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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update_config.tcl: $(CONFIG_TCL_FILES_REL)
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echo "open_project -quiet $(FPGA_TOP).xpr" > $@
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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$(FPGA_TOP).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) $(CONFIG_TCL_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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%.bit: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $*.runs/impl_1/$*.bit" >> generate_bit.tcl
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echo "write_hw_platform -fixed -force -include_bit $*.xsa" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $*.runs/impl_1/$*.bit .
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp $*.bit rev/$*_rev$$COUNT.bit; \
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cp $*.xsa rev/$*_rev$$COUNT.xsa; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";

‎fpga/mqnic/ZCU102/fpga/fpga.xdc‎

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# XDC constraints for the Xilinx ZCU102 board
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# part: xczu9eg-ffvb1156-2-e
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# General configuration
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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# System clocks
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# 125 MHz
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set_property -dict {LOC G21 IOSTANDARD LVDS_25} [get_ports clk_125mhz_p]
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set_property -dict {LOC F21 IOSTANDARD LVDS_25} [get_ports clk_125mhz_n]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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# LEDs
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set_property -dict {LOC AG14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC AF13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
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set_property -dict {LOC AE13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
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set_property -dict {LOC AJ14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
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set_property -dict {LOC AJ15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[4]}]
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set_property -dict {LOC AH13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[5]}]
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set_property -dict {LOC AH14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[6]}]
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set_property -dict {LOC AL12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[7]}]
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Reset button
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#set_property -dict {LOC AM13 IOSTANDARD LVCMOS33} [get_ports reset]
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#set_false_path -from [get_ports {reset}]
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#set_input_delay 0 [get_ports {reset}]
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# Push buttons
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set_property -dict {LOC AG15 IOSTANDARD LVCMOS33} [get_ports btnu]
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set_property -dict {LOC AF15 IOSTANDARD LVCMOS33} [get_ports btnl]
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set_property -dict {LOC AE15 IOSTANDARD LVCMOS33} [get_ports btnd]
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set_property -dict {LOC AE14 IOSTANDARD LVCMOS33} [get_ports btnr]
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set_property -dict {LOC AG13 IOSTANDARD LVCMOS33} [get_ports btnc]
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set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
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set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
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# DIP switches
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set_property -dict {LOC AN14 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]
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set_property -dict {LOC AP14 IOSTANDARD LVCMOS33} [get_ports {sw[1]}]
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set_property -dict {LOC AM14 IOSTANDARD LVCMOS33} [get_ports {sw[2]}]
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set_property -dict {LOC AN13 IOSTANDARD LVCMOS33} [get_ports {sw[3]}]
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set_property -dict {LOC AN12 IOSTANDARD LVCMOS33} [get_ports {sw[4]}]
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set_property -dict {LOC AP12 IOSTANDARD LVCMOS33} [get_ports {sw[5]}]
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set_property -dict {LOC AL13 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
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set_property -dict {LOC AK13 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# UART
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#set_property -dict {LOC F13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_txd]
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#set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
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#set_property -dict {LOC D12 IOSTANDARD LVCMOS33} [get_ports uart_rts]
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#set_property -dict {LOC E12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_cts]
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#set_false_path -to [get_ports {uart_txd uart_cts}]
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#set_output_delay 0 [get_ports {uart_txd uart_cts}]
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#set_false_path -from [get_ports {uart_rxd uart_rts}]
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#set_input_delay 0 [get_ports {uart_rxd uart_rts}]
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# I2C interfaces
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#set_property -dict {LOC J10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_scl]
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#set_property -dict {LOC J11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_sda]
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#set_property -dict {LOC K20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_scl]
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#set_property -dict {LOC L20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_sda]
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#set_false_path -to [get_ports {i2c1_sda i2c1_scl}]
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#set_output_delay 0 [get_ports {i2c1_sda i2c1_scl}]
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#set_false_path -from [get_ports {i2c1_sda i2c1_scl}]
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#set_input_delay 0 [get_ports {i2c1_sda i2c1_scl}]
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# SFP+ Interface
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set_property -dict {LOC D2 } [get_ports sfp0_rx_p] ;# MGTHRXP0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC D1 } [get_ports sfp0_rx_n] ;# MGTHRXN0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC E4 } [get_ports sfp0_tx_p] ;# MGTHTXP0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC E3 } [get_ports sfp0_tx_n] ;# MGTHTXN0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC C4 } [get_ports sfp1_rx_p] ;# MGTHRXP1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC C3 } [get_ports sfp1_rx_n] ;# MGTHRXN1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC D6 } [get_ports sfp1_tx_p] ;# MGTHTXP1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC D5 } [get_ports sfp1_tx_n] ;# MGTHTXN1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC B2 } [get_ports sfp2_rx_p] ;# MGTHRXP2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC B1 } [get_ports sfp2_rx_n] ;# MGTHRXN2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC B6 } [get_ports sfp2_tx_p] ;# MGTHTXP2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC B5 } [get_ports sfp2_tx_n] ;# MGTHTXN2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC A4 } [get_ports sfp3_rx_p] ;# MGTHRXP3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC A3 } [get_ports sfp3_rx_n] ;# MGTHRXN3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC A8 } [get_ports sfp3_tx_p] ;# MGTHTXP3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC A7 } [get_ports sfp3_tx_n] ;# MGTHTXN3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC C8 } [get_ports sfp_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U56 SI570 via U51 SI53340
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set_property -dict {LOC C7 } [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U56 SI570 via U51 SI53340
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#set_property -dict {LOC B10 } [get_ports sfp_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U20 CKOUT2 SI5328
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#set_property -dict {LOC B9 } [get_ports sfp_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U20 CKOUT2 SI5328
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#set_property -dict {LOC R10 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to U20 CKIN1 SI5328
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#set_property -dict {LOC R9 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U20 CKIN1 SI5328
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set_property -dict {LOC A12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp0_tx_disable_b]
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set_property -dict {LOC A13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp1_tx_disable_b]
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set_property -dict {LOC B13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp2_tx_disable_b]
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set_property -dict {LOC C13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp3_tx_disable_b]
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# 156.25 MHz MGT reference clock
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create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p]
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set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}]
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set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}]

‎fpga/mqnic/ZCU102/fpga/fpga/.gitignore‎

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*
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!/config.tcl
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!/Makefile

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