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alexforencichalexforencich
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fpga/mqnic/fb4CGg3: Add DRAM support on fb4CGg3
Signed-off-by: Alex Forencich <alex@alexforencich.com>
1 parent f1884b9 commit 6e67bd6

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26 files changed

+3769
-118
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26 files changed

+3769
-118
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‎fpga/mqnic/fb4CGg3/fpga_100g/boot.xdc‎

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# Timing constraints for FPGA boot logic
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set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"]
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set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"]

‎fpga/mqnic/fb4CGg3/fpga_100g/fpga.xdc‎

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‎fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile‎

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@@ -9,6 +9,7 @@ FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/bmc_spi.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/common/mqnic_core_pcie_us.v
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SYN_FILES += rtl/common/mqnic_core_pcie.v
@@ -114,6 +115,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += placement.xdc
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XDC_FILES += boot.xdc
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XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
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XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
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XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@@ -129,6 +131,8 @@ XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl
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IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus.tcl
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IP_TCL_FILES += ip/cmac_gty.tcl
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#IP_TCL_FILES += ip/ddr4_0.tcl
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#IP_TCL_FILES += ip/ddr4_sodimm_0.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl

‎fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl‎

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@@ -108,6 +108,12 @@ dict set params MAX_RX_SIZE "9214"
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dict set params TX_RAM_SIZE "131072"
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dict set params RX_RAM_SIZE "131072"
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# RAM configuration
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dict set params DDR_CH "4"
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dict set params DDR_ENABLE "0"
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dict set params AXI_DDR_ID_WIDTH "8"
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dict set params AXI_DDR_MAX_BURST_LEN "256"
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# Application block configuration
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dict set params APP_ID "32'h00000000"
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dict set params APP_ENABLE "0"
@@ -151,6 +157,43 @@ dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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dict set params STAT_ID_WIDTH "12"
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# DDR4 MIG settings
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if {[dict get $params DDR_ENABLE]} {
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# components (DDR4 A, DDR4 B)
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set ddr4 [get_ips ddr4_0]
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# performance-related configuration
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set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
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set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
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set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
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# set AXI ID width
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set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
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# extract AXI configuration
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dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
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dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
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dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
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if {[dict get $params DDR_CH] > 2} {
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# SO-DIMMs (DDR4 SODMM A, DDR4 SODIMM B)
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set ddr4 [get_ips ddr4_sodimm_0]
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# performance-related configuration
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set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
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set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
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set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
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# set AXI ID width
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set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
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# extract AXI configuration
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dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
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dict set params AXI_DDR_ADDR_WIDTH [expr max([get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4], [dict get $params AXI_DDR_ADDR_WIDTH])]
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dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && [dict get $params AXI_DDR_NARROW_BURST]]
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}
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}
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# PCIe IP core settings
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set pcie [get_ips pcie4_uscale_plus_0]
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‎fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/bmc_spi.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/common/mqnic_core_pcie_us.v
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SYN_FILES += rtl/common/mqnic_core_pcie.v
@@ -121,6 +122,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += placement.xdc
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XDC_FILES += boot.xdc
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XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
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XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
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XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
@@ -140,6 +142,8 @@ XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
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IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus.tcl
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IP_TCL_FILES += ip/cmac_gty.tcl
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IP_TCL_FILES += ip/ddr4_0.tcl
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IP_TCL_FILES += ip/ddr4_sodimm_0.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl

‎fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -108,6 +108,12 @@ dict set params MAX_RX_SIZE "9214"
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dict set params TX_RAM_SIZE "131072"
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dict set params RX_RAM_SIZE "131072"
110110

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# RAM configuration
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dict set params DDR_CH "4"
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dict set params DDR_ENABLE "1"
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dict set params AXI_DDR_ID_WIDTH "8"
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dict set params AXI_DDR_MAX_BURST_LEN "256"
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# Application block configuration
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dict set params APP_ID "32'h12348001"
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dict set params APP_ENABLE "1"
@@ -151,6 +157,43 @@ dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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dict set params STAT_ID_WIDTH "12"
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# DDR4 MIG settings
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if {[dict get $params DDR_ENABLE]} {
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# components (DDR4 A, DDR4 B)
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set ddr4 [get_ips ddr4_0]
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# performance-related configuration
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set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
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set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
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set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
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# set AXI ID width
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set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
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# extract AXI configuration
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dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
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dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
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dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
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if {[dict get $params DDR_CH] > 2} {
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# SO-DIMMs (DDR4 SODMM A, DDR4 SODIMM B)
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set ddr4 [get_ips ddr4_sodimm_0]
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# performance-related configuration
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set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
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set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
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set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
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# set AXI ID width
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set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
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# extract AXI configuration
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dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
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dict set params AXI_DDR_ADDR_WIDTH [expr max([get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4], [dict get $params AXI_DDR_ADDR_WIDTH])]
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dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && [dict get $params AXI_DDR_NARROW_BURST]]
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}
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}
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# PCIe IP core settings
155198
set pcie [get_ips pcie4_uscale_plus_0]
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‎fpga/mqnic/fb4CGg3/fpga_100g/ip/ddr4_0.tcl‎

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create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
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set_property -dict [list \
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CONFIG.C0.DDR4_AxiSelection {true} \
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CONFIG.C0.DDR4_AxiDataWidth {512} \
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CONFIG.C0.DDR4_AxiIDWidth {8} \
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CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
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CONFIG.C0.DDR4_TimePeriod {833} \
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CONFIG.C0.DDR4_InputClockPeriod {3750} \
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CONFIG.C0.DDR4_MemoryType {Components} \
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CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-083E} \
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CONFIG.C0.DDR4_DataWidth {64} \
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CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
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CONFIG.C0.DDR4_CasLatency {16} \
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CONFIG.C0.DDR4_CasWriteLatency {12} \
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CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
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] [get_ips ddr4_0]

‎fpga/mqnic/fb4CGg3/fpga_100g/ip/ddr4_sodimm_0.tcl‎

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create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_sodimm_0
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set_property -dict [list \
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CONFIG.C0.DDR4_AxiSelection {true} \
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CONFIG.C0.DDR4_AxiDataWidth {512} \
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CONFIG.C0.DDR4_AxiIDWidth {8} \
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CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
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CONFIG.C0.DDR4_TimePeriod {833} \
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CONFIG.C0.DDR4_InputClockPeriod {3750} \
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CONFIG.C0.DDR4_MemoryType {SODIMMs} \
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CONFIG.C0.DDR4_MemoryPart {MTA8ATF1G64HZ-2G3} \
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CONFIG.C0.DDR4_DataWidth {64} \
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CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
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CONFIG.C0.DDR4_CasLatency {17} \
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CONFIG.C0.DDR4_CasWriteLatency {12} \
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CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
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] [get_ips ddr4_sodimm_0]

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