@@ -62,7 +62,6 @@ module axis_frame_len #
6262
6363reg [LEN_WIDTH- 1 :0 ] frame_len_reg = 0 , frame_len_next;
6464reg frame_len_valid_reg = 1'b0 , frame_len_valid_next;
65- reg frame_reg = 1'b0 , frame_next;
6665
6766assign frame_len = frame_len_reg;
6867assign frame_len_valid = frame_len_valid_reg;
@@ -72,19 +71,17 @@ integer offset, i, bit_cnt;
7271always @* begin
7372 frame_len_next = frame_len_reg;
7473 frame_len_valid_next = 1'b0 ;
75- frame_next = frame_reg;
74+
75+ if (frame_len_valid_reg) begin
76+ frame_len_next = 0 ;
77+ end
7678
7779 if (monitor_axis_tready && monitor_axis_tvalid) begin
7880 // valid transfer cycle
7981
8082 if (monitor_axis_tlast) begin
8183 // end of frame
8284 frame_len_valid_next = 1'b1 ;
83- frame_next = 1'b0 ;
84- end else if (! frame_reg) begin
85- // first word after end of frame
86- frame_len_next = 0 ;
87- frame_next = 1'b1 ;
8885 end
8986
9087 // increment frame length by number of words transferred
@@ -101,14 +98,12 @@ always @* begin
10198end
10299
103100always @(posedge clk) begin
101+ frame_len_reg <= frame_len_next;
102+ frame_len_valid_reg <= frame_len_valid_next;
103+
104104 if (rst) begin
105105 frame_len_reg <= 0 ;
106106 frame_len_valid_reg <= 0 ;
107- frame_reg <= 1'b0 ;
108- end else begin
109- frame_len_reg <= frame_len_next;
110- frame_len_valid_reg <= frame_len_valid_next;
111- frame_reg <= frame_next;
112107 end
113108end
114109
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