Fix off by one error

alexforencich · alexforencich · commit 0b5fc5b0e0a0 · 2021-09-28T01:17:57.000-07:00
diff --git a/rtl/axis_pipeline_fifo.v b/rtl/axis_pipeline_fifo.v
@@ -83,7 +83,7 @@ module axis_pipeline_fifo #
     output wire [USER_WIDTH-1:0]  m_axis_tuser
 );
 
-parameter FIFO_ADDR_WIDTH = LENGTH < 2 ? 3 : $clog2(LENGTH*4);
+parameter FIFO_ADDR_WIDTH = LENGTH < 2 ? 3 : $clog2(LENGTH*4+1);
 
 generate
 
