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alexforencichalexforencich
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Decouple tid/tdest signal widths for routing components
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16 files changed

+418
-365
lines changed

16 files changed

+418
-365
lines changed

‎rtl/axis_arb_mux.v‎

Lines changed: 25 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,10 @@ module axis_arb_mux #
4343
parameter KEEP_WIDTH = (DATA_WIDTH/8),
4444
// Propagate tid signal
4545
parameter ID_ENABLE = 0,
46-
// tid signal width
47-
parameter ID_WIDTH = 8,
46+
// input tid signal width
47+
parameter S_ID_WIDTH = 8,
48+
// output tid signal width
49+
parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
4850
// Propagate tdest signal
4951
parameter DEST_ENABLE = 0,
5052
// tdest signal width
@@ -67,26 +69,26 @@ module axis_arb_mux #
6769
/*
6870
* AXI Stream inputs
6971
*/
70-
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
71-
input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
72-
input wire [S_COUNT-1:0] s_axis_tvalid,
73-
output wire [S_COUNT-1:0] s_axis_tready,
74-
input wire [S_COUNT-1:0] s_axis_tlast,
75-
input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid,
76-
input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
77-
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
72+
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
73+
input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
74+
input wire [S_COUNT-1:0] s_axis_tvalid,
75+
output wire [S_COUNT-1:0] s_axis_tready,
76+
input wire [S_COUNT-1:0] s_axis_tlast,
77+
input wire [S_COUNT*S_ID_WIDTH-1:0] s_axis_tid,
78+
input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
79+
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
7880

7981
/*
8082
* AXI Stream output
8183
*/
82-
output wire [DATA_WIDTH-1:0] m_axis_tdata,
83-
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
84-
output wire m_axis_tvalid,
85-
input wire m_axis_tready,
86-
output wire m_axis_tlast,
87-
output wire [ID_WIDTH-1:0] m_axis_tid,
88-
output wire [DEST_WIDTH-1:0] m_axis_tdest,
89-
output wire [USER_WIDTH-1:0] m_axis_tuser
84+
output wire [DATA_WIDTH-1:0] m_axis_tdata,
85+
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
86+
output wire m_axis_tvalid,
87+
input wire m_axis_tready,
88+
output wire m_axis_tlast,
89+
output wire [M_ID_WIDTH-1:0] m_axis_tid,
90+
output wire [DEST_WIDTH-1:0] m_axis_tdest,
91+
output wire [USER_WIDTH-1:0] m_axis_tuser
9092
);
9193

9294
parameter CL_S_COUNT = $clog2(S_COUNT);
@@ -103,7 +105,7 @@ reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
103105
reg m_axis_tvalid_int;
104106
reg m_axis_tready_int_reg = 1'b0;
105107
reg m_axis_tlast_int;
106-
reg [ID_WIDTH-1:0] m_axis_tid_int;
108+
reg [M_ID_WIDTH-1:0] m_axis_tid_int;
107109
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
108110
reg [USER_WIDTH-1:0] m_axis_tuser_int;
109111
wire m_axis_tready_int_early;
@@ -116,7 +118,7 @@ wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[grant_encoded*KEEP_WIDTH +
116118
wire current_s_tvalid = s_axis_tvalid[grant_encoded];
117119
wire current_s_tready = s_axis_tready[grant_encoded];
118120
wire current_s_tlast = s_axis_tlast[grant_encoded];
119-
wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
121+
wire [S_ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH];
120122
wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
121123
wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
122124

@@ -157,15 +159,15 @@ reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
157159
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
158160
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
159161
reg m_axis_tlast_reg = 1'b0;
160-
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
162+
reg [M_ID_WIDTH-1:0] m_axis_tid_reg = {M_ID_WIDTH{1'b0}};
161163
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
162164
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
163165

164166
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
165167
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
166168
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
167169
reg temp_m_axis_tlast_reg = 1'b0;
168-
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
170+
reg [M_ID_WIDTH-1:0] temp_m_axis_tid_reg = {M_ID_WIDTH{1'b0}};
169171
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
170172
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
171173

@@ -178,7 +180,7 @@ assign m_axis_tdata = m_axis_tdata_reg;
178180
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
179181
assign m_axis_tvalid = m_axis_tvalid_reg;
180182
assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
181-
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
183+
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {M_ID_WIDTH{1'b0}};
182184
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
183185
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
184186

‎rtl/axis_arb_mux_wrap.py‎

Lines changed: 24 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -78,8 +78,10 @@ def generate(ports=4, name=None, output=None):
7878
parameter KEEP_WIDTH = (DATA_WIDTH/8),
7979
// Propagate tid signal
8080
parameter ID_ENABLE = 0,
81-
// tid signal width
82-
parameter ID_WIDTH = 8,
81+
// input tid signal width
82+
parameter S_ID_WIDTH = 8,
83+
// output tid signal width
84+
parameter M_ID_WIDTH = S_ID_WIDTH+{{cn}},
8385
// Propagate tdest signal
8486
parameter DEST_ENABLE = 0,
8587
// tdest signal width
@@ -96,33 +98,33 @@ def generate(ports=4, name=None, output=None):
9698
parameter ARB_LSB_HIGH_PRIORITY = 1
9799
)
98100
(
99-
input wire clk,
100-
input wire rst,
101+
input wire clk,
102+
input wire rst,
101103
102104
/*
103105
* AXI Stream inputs
104106
*/
105107
{%- for p in range(n) %}
106-
input wire [DATA_WIDTH-1:0] s{{'%02d'%p}}_axis_tdata,
107-
input wire [KEEP_WIDTH-1:0] s{{'%02d'%p}}_axis_tkeep,
108-
input wire s{{'%02d'%p}}_axis_tvalid,
109-
output wire s{{'%02d'%p}}_axis_tready,
110-
input wire s{{'%02d'%p}}_axis_tlast,
111-
input wire [ID_WIDTH-1:0] s{{'%02d'%p}}_axis_tid,
112-
input wire [DEST_WIDTH-1:0] s{{'%02d'%p}}_axis_tdest,
113-
input wire [USER_WIDTH-1:0] s{{'%02d'%p}}_axis_tuser,
108+
input wire [DATA_WIDTH-1:0] s{{'%02d'%p}}_axis_tdata,
109+
input wire [KEEP_WIDTH-1:0] s{{'%02d'%p}}_axis_tkeep,
110+
input wire s{{'%02d'%p}}_axis_tvalid,
111+
output wire s{{'%02d'%p}}_axis_tready,
112+
input wire s{{'%02d'%p}}_axis_tlast,
113+
input wire [S_ID_WIDTH-1:0] s{{'%02d'%p}}_axis_tid,
114+
input wire [DEST_WIDTH-1:0] s{{'%02d'%p}}_axis_tdest,
115+
input wire [USER_WIDTH-1:0] s{{'%02d'%p}}_axis_tuser,
114116
{% endfor %}
115117
/*
116118
* AXI Stream output
117119
*/
118-
output wire [DATA_WIDTH-1:0] m_axis_tdata,
119-
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
120-
output wire m_axis_tvalid,
121-
input wire m_axis_tready,
122-
output wire m_axis_tlast,
123-
output wire [ID_WIDTH-1:0] m_axis_tid,
124-
output wire [DEST_WIDTH-1:0] m_axis_tdest,
125-
output wire [USER_WIDTH-1:0] m_axis_tuser
120+
output wire [DATA_WIDTH-1:0] m_axis_tdata,
121+
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
122+
output wire m_axis_tvalid,
123+
input wire m_axis_tready,
124+
output wire m_axis_tlast,
125+
output wire [M_ID_WIDTH-1:0] m_axis_tid,
126+
output wire [DEST_WIDTH-1:0] m_axis_tdest,
127+
output wire [USER_WIDTH-1:0] m_axis_tuser
126128
);
127129
128130
axis_arb_mux #(
@@ -131,7 +133,8 @@ def generate(ports=4, name=None, output=None):
131133
.KEEP_ENABLE(KEEP_ENABLE),
132134
.KEEP_WIDTH(KEEP_WIDTH),
133135
.ID_ENABLE(ID_ENABLE),
134-
.ID_WIDTH(ID_WIDTH),
136+
.S_ID_WIDTH(S_ID_WIDTH),
137+
.M_ID_WIDTH(M_ID_WIDTH),
135138
.DEST_ENABLE(DEST_ENABLE),
136139
.DEST_WIDTH(DEST_WIDTH),
137140
.USER_ENABLE(USER_ENABLE),

‎rtl/axis_demux.v‎

Lines changed: 50 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -47,47 +47,49 @@ module axis_demux #
4747
parameter ID_WIDTH = 8,
4848
// Propagate tdest signal
4949
parameter DEST_ENABLE = 0,
50-
// tdest signal width
51-
parameter DEST_WIDTH = 8,
50+
// output tdest signal width
51+
parameter M_DEST_WIDTH = 8,
52+
// input tdest signal width
53+
parameter S_DEST_WIDTH = M_DEST_WIDTH+$clog2(M_COUNT),
5254
// Propagate tuser signal
5355
parameter USER_ENABLE = 1,
5456
// tuser signal width
5557
parameter USER_WIDTH = 1
5658
)
5759
(
58-
input wire clk,
59-
input wire rst,
60+
input wire clk,
61+
input wire rst,
6062

6163
/*
6264
* AXI input
6365
*/
64-
input wire [DATA_WIDTH-1:0] s_axis_tdata,
65-
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
66-
input wire s_axis_tvalid,
67-
output wire s_axis_tready,
68-
input wire s_axis_tlast,
69-
input wire [ID_WIDTH-1:0] s_axis_tid,
70-
input wire [DEST_WIDTH-1:0] s_axis_tdest,
71-
input wire [USER_WIDTH-1:0] s_axis_tuser,
66+
input wire [DATA_WIDTH-1:0] s_axis_tdata,
67+
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
68+
input wire s_axis_tvalid,
69+
output wire s_axis_tready,
70+
input wire s_axis_tlast,
71+
input wire [ID_WIDTH-1:0] s_axis_tid,
72+
input wire [S_DEST_WIDTH-1:0] s_axis_tdest,
73+
input wire [USER_WIDTH-1:0] s_axis_tuser,
7274

7375
/*
7476
* AXI outputs
7577
*/
76-
output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
77-
output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
78-
output wire [M_COUNT-1:0] m_axis_tvalid,
79-
input wire [M_COUNT-1:0] m_axis_tready,
80-
output wire [M_COUNT-1:0] m_axis_tlast,
81-
output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
82-
output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest,
83-
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser,
78+
output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
79+
output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
80+
output wire [M_COUNT-1:0] m_axis_tvalid,
81+
input wire [M_COUNT-1:0] m_axis_tready,
82+
output wire [M_COUNT-1:0] m_axis_tlast,
83+
output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
84+
output wire [M_COUNT*M_DEST_WIDTH-1:0] m_axis_tdest,
85+
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser,
8486

8587
/*
8688
* Control
8789
*/
88-
input wire enable,
89-
input wire drop,
90-
input wire [$clog2(M_COUNT)-1:0] select
90+
input wire enable,
91+
input wire drop,
92+
input wire [$clog2(M_COUNT)-1:0] select
9193
);
9294

9395
parameter CL_M_COUNT = $clog2(M_COUNT);
@@ -99,15 +101,15 @@ reg frame_reg = 1'b0, frame_ctl, frame_next;
99101
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
100102

101103
// internal datapath
102-
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
103-
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
104-
reg [M_COUNT-1:0] m_axis_tvalid_int;
105-
reg m_axis_tready_int_reg = 1'b0;
106-
reg m_axis_tlast_int;
107-
reg [ID_WIDTH-1:0] m_axis_tid_int;
108-
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
109-
reg [USER_WIDTH-1:0] m_axis_tuser_int;
110-
wire m_axis_tready_int_early;
104+
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
105+
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
106+
reg [M_COUNT-1:0] m_axis_tvalid_int;
107+
reg m_axis_tready_int_reg = 1'b0;
108+
reg m_axis_tlast_int;
109+
reg [ID_WIDTH-1:0] m_axis_tid_int;
110+
reg [M_DEST_WIDTH-1:0] m_axis_tdest_int;
111+
reg [USER_WIDTH-1:0] m_axis_tuser_int;
112+
wire m_axis_tready_int_early;
111113

112114
assign s_axis_tready = s_axis_tready_reg && enable;
113115

@@ -167,21 +169,21 @@ always @(posedge clk) begin
167169
end
168170

169171
// output datapath logic
170-
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
171-
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
172-
reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next;
173-
reg m_axis_tlast_reg = 1'b0;
174-
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
175-
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
176-
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
177-
178-
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
179-
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
180-
reg [M_COUNT-1:0] temp_m_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_tvalid_next;
181-
reg temp_m_axis_tlast_reg = 1'b0;
182-
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
183-
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
184-
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
172+
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
173+
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
174+
reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next;
175+
reg m_axis_tlast_reg = 1'b0;
176+
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
177+
reg [M_DEST_WIDTH-1:0] m_axis_tdest_reg = {M_DEST_WIDTH{1'b0}};
178+
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
179+
180+
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
181+
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
182+
reg [M_COUNT-1:0] temp_m_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_tvalid_next;
183+
reg temp_m_axis_tlast_reg = 1'b0;
184+
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
185+
reg [M_DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {M_DEST_WIDTH{1'b0}};
186+
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
185187

186188
// datapath control
187189
reg store_axis_int_to_output;
@@ -193,7 +195,7 @@ assign m_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_axis_tkeep_reg}} : {M_COUNT*KEEP
193195
assign m_axis_tvalid = m_axis_tvalid_reg;
194196
assign m_axis_tlast = {M_COUNT{m_axis_tlast_reg}};
195197
assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
196-
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
198+
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*M_DEST_WIDTH{1'b0}};
197199
assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
198200

199201
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)

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