Add default_nettype none and resetall directives

Author: alexforencich

rtl/arbiter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Arbiter module
@@ -153,3 +155,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axis_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream bus width adapter
@@ -552,3 +554,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axis_arb_mux.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream arbitrated multiplexer
@@ -250,3 +252,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axis_arb_mux_wrap.py

@@ -61,7 +61,9 @@ def generate(ports=4, name=None, output=None):
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port arbitrated mux (wrapper)
@@ -163,6 +165,8 @@ def generate(ports=4, name=None, output=None):
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

rtl/axis_async_fifo.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream asynchronous FIFO
@@ -618,3 +620,5 @@ always @(posedge m_clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axis_async_fifo_adapter.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream asynchronous FIFO with width converter
@@ -353,3 +355,5 @@ fifo_inst (
 );
 
 endmodule
+
+`resetall

rtl/axis_broadcast.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream broadcaster
@@ -189,3 +191,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axis_broadcast_wrap.py

@@ -61,7 +61,9 @@ def generate(ports=4, name=None, output=None):
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream {{n}} port broadcast (wrapper)
@@ -158,6 +160,8 @@ def generate(ports=4, name=None, output=None):
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

rtl/axis_cobs_decode.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream consistent overhead byte stuffing (COBS) decoder
@@ -326,3 +328,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

rtl/axis_cobs_encode.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * AXI4-Stream consistent overhead byte stuffing (COBS) encoder
@@ -504,3 +506,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall