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Reorganize FIFO adapter wrappers
Signed-off-by: Alex Forencich <[email protected]>
1 parent 1628a1a commit 9848095

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2 files changed

+142
-175
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2 files changed

+142
-175
lines changed

‎rtl/axis_async_fifo_adapter.v‎

Lines changed: 71 additions & 88 deletions
Original file line numberDiff line numberDiff line change
@@ -132,32 +132,32 @@ module axis_async_fifo_adapter #
132132
);
133133

134134
// force keep width to 1 when disabled
135-
parameter S_KEEP_WIDTH_INT = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1;
136-
parameter M_KEEP_WIDTH_INT = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1;
135+
parameter S_BYTE_LANES = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1;
136+
parameter M_BYTE_LANES = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1;
137137

138-
// bus word sizes (must be identical)
139-
parameter S_DATA_WORD_SIZE = S_DATA_WIDTH / S_KEEP_WIDTH_INT;
140-
parameter M_DATA_WORD_SIZE = M_DATA_WIDTH / M_KEEP_WIDTH_INT;
138+
// bus byte sizes (must be identical)
139+
parameter S_BYTE_SIZE = S_DATA_WIDTH / S_BYTE_LANES;
140+
parameter M_BYTE_SIZE = M_DATA_WIDTH / M_BYTE_LANES;
141141
// output bus is wider
142-
parameter EXPAND_BUS = M_KEEP_WIDTH_INT > S_KEEP_WIDTH_INT;
142+
parameter EXPAND_BUS = M_BYTE_LANES > S_BYTE_LANES;
143143
// total data and keep widths
144144
parameter DATA_WIDTH = EXPAND_BUS ? M_DATA_WIDTH : S_DATA_WIDTH;
145-
parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT;
145+
parameter KEEP_WIDTH = EXPAND_BUS ? M_BYTE_LANES : S_BYTE_LANES;
146146

147147
// bus width assertions
148148
initial begin
149-
if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
150-
$error("Error: input data width not evenly divisble (instance %m)");
149+
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_WIDTH) begin
150+
$error("Error: input data width not evenly divisible (instance %m)");
151151
$finish;
152152
end
153153

154-
if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
155-
$error("Error: output data width not evenly divisble (instance %m)");
154+
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_WIDTH) begin
155+
$error("Error: output data width not evenly divisible (instance %m)");
156156
$finish;
157157
end
158158

159-
if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
160-
$error("Error: word size mismatch (instance %m)");
159+
if (S_BYTE_SIZE != M_BYTE_SIZE) begin
160+
$error("Error: byte size mismatch (instance %m)");
161161
$finish;
162162
end
163163
end
@@ -182,30 +182,7 @@ wire [USER_WIDTH-1:0] post_fifo_axis_tuser;
182182

183183
generate
184184

185-
if (M_KEEP_WIDTH == S_KEEP_WIDTH) begin
186-
187-
// same width, no adapter needed
188-
189-
assign pre_fifo_axis_tdata = s_axis_tdata;
190-
assign pre_fifo_axis_tkeep = s_axis_tkeep;
191-
assign pre_fifo_axis_tvalid = s_axis_tvalid;
192-
assign s_axis_tready = pre_fifo_axis_tready;
193-
assign pre_fifo_axis_tlast = s_axis_tlast;
194-
assign pre_fifo_axis_tid = s_axis_tid;
195-
assign pre_fifo_axis_tdest = s_axis_tdest;
196-
assign pre_fifo_axis_tuser = s_axis_tuser;
197-
198-
assign m_axis_tdata = post_fifo_axis_tdata;
199-
assign m_axis_tkeep = post_fifo_axis_tkeep;
200-
assign m_axis_tvalid = post_fifo_axis_tvalid;
201-
assign post_fifo_axis_tready = m_axis_tready;
202-
assign m_axis_tlast = post_fifo_axis_tlast;
203-
assign m_axis_tid = post_fifo_axis_tid;
204-
assign m_axis_tdest = post_fifo_axis_tdest;
205-
assign m_axis_tuser = post_fifo_axis_tuser;
206-
207-
208-
end else if (EXPAND_BUS) begin
185+
if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize_pre
209186

210187
// output wider, adapt width before FIFO
211188

@@ -246,19 +223,8 @@ end else if (EXPAND_BUS) begin
246223
.m_axis_tuser(pre_fifo_axis_tuser)
247224
);
248225

249-
assign m_axis_tdata = post_fifo_axis_tdata;
250-
assign m_axis_tkeep = post_fifo_axis_tkeep;
251-
assign m_axis_tvalid = post_fifo_axis_tvalid;
252-
assign post_fifo_axis_tready = m_axis_tready;
253-
assign m_axis_tlast = post_fifo_axis_tlast;
254-
assign m_axis_tid = post_fifo_axis_tid;
255-
assign m_axis_tdest = post_fifo_axis_tdest;
256-
assign m_axis_tuser = post_fifo_axis_tuser;
257-
258-
end else begin
226+
end else begin : bypass_pre
259227

260-
// input wider, adapt width after FIFO
261-
262228
assign pre_fifo_axis_tdata = s_axis_tdata;
263229
assign pre_fifo_axis_tkeep = s_axis_tkeep;
264230
assign pre_fifo_axis_tvalid = s_axis_tvalid;
@@ -268,47 +234,8 @@ end else begin
268234
assign pre_fifo_axis_tdest = s_axis_tdest;
269235
assign pre_fifo_axis_tuser = s_axis_tuser;
270236

271-
axis_adapter #(
272-
.S_DATA_WIDTH(S_DATA_WIDTH),
273-
.S_KEEP_ENABLE(S_KEEP_ENABLE),
274-
.S_KEEP_WIDTH(S_KEEP_WIDTH),
275-
.M_DATA_WIDTH(M_DATA_WIDTH),
276-
.M_KEEP_ENABLE(M_KEEP_ENABLE),
277-
.M_KEEP_WIDTH(M_KEEP_WIDTH),
278-
.ID_ENABLE(ID_ENABLE),
279-
.ID_WIDTH(ID_WIDTH),
280-
.DEST_ENABLE(DEST_ENABLE),
281-
.DEST_WIDTH(DEST_WIDTH),
282-
.USER_ENABLE(USER_ENABLE),
283-
.USER_WIDTH(USER_WIDTH)
284-
)
285-
adapter_inst (
286-
.clk(m_clk),
287-
.rst(m_rst),
288-
// AXI input
289-
.s_axis_tdata(post_fifo_axis_tdata),
290-
.s_axis_tkeep(post_fifo_axis_tkeep),
291-
.s_axis_tvalid(post_fifo_axis_tvalid),
292-
.s_axis_tready(post_fifo_axis_tready),
293-
.s_axis_tlast(post_fifo_axis_tlast),
294-
.s_axis_tid(post_fifo_axis_tid),
295-
.s_axis_tdest(post_fifo_axis_tdest),
296-
.s_axis_tuser(post_fifo_axis_tuser),
297-
// AXI output
298-
.m_axis_tdata(m_axis_tdata),
299-
.m_axis_tkeep(m_axis_tkeep),
300-
.m_axis_tvalid(m_axis_tvalid),
301-
.m_axis_tready(m_axis_tready),
302-
.m_axis_tlast(m_axis_tlast),
303-
.m_axis_tid(m_axis_tid),
304-
.m_axis_tdest(m_axis_tdest),
305-
.m_axis_tuser(m_axis_tuser)
306-
);
307-
308237
end
309238

310-
endgenerate
311-
312239
axis_async_fifo #(
313240
.DEPTH(DEPTH),
314241
.DATA_WIDTH(DATA_WIDTH),
@@ -366,6 +293,62 @@ fifo_inst (
366293
.m_status_good_frame(m_status_good_frame)
367294
);
368295

296+
if (M_BYTE_LANES < S_BYTE_LANES) begin : downsize_post
297+
298+
// input wider, adapt width after FIFO
299+
300+
axis_adapter #(
301+
.S_DATA_WIDTH(S_DATA_WIDTH),
302+
.S_KEEP_ENABLE(S_KEEP_ENABLE),
303+
.S_KEEP_WIDTH(S_KEEP_WIDTH),
304+
.M_DATA_WIDTH(M_DATA_WIDTH),
305+
.M_KEEP_ENABLE(M_KEEP_ENABLE),
306+
.M_KEEP_WIDTH(M_KEEP_WIDTH),
307+
.ID_ENABLE(ID_ENABLE),
308+
.ID_WIDTH(ID_WIDTH),
309+
.DEST_ENABLE(DEST_ENABLE),
310+
.DEST_WIDTH(DEST_WIDTH),
311+
.USER_ENABLE(USER_ENABLE),
312+
.USER_WIDTH(USER_WIDTH)
313+
)
314+
adapter_inst (
315+
.clk(m_clk),
316+
.rst(m_rst),
317+
// AXI input
318+
.s_axis_tdata(post_fifo_axis_tdata),
319+
.s_axis_tkeep(post_fifo_axis_tkeep),
320+
.s_axis_tvalid(post_fifo_axis_tvalid),
321+
.s_axis_tready(post_fifo_axis_tready),
322+
.s_axis_tlast(post_fifo_axis_tlast),
323+
.s_axis_tid(post_fifo_axis_tid),
324+
.s_axis_tdest(post_fifo_axis_tdest),
325+
.s_axis_tuser(post_fifo_axis_tuser),
326+
// AXI output
327+
.m_axis_tdata(m_axis_tdata),
328+
.m_axis_tkeep(m_axis_tkeep),
329+
.m_axis_tvalid(m_axis_tvalid),
330+
.m_axis_tready(m_axis_tready),
331+
.m_axis_tlast(m_axis_tlast),
332+
.m_axis_tid(m_axis_tid),
333+
.m_axis_tdest(m_axis_tdest),
334+
.m_axis_tuser(m_axis_tuser)
335+
);
336+
337+
end else begin : bypass_post
338+
339+
assign m_axis_tdata = post_fifo_axis_tdata;
340+
assign m_axis_tkeep = post_fifo_axis_tkeep;
341+
assign m_axis_tvalid = post_fifo_axis_tvalid;
342+
assign post_fifo_axis_tready = m_axis_tready;
343+
assign m_axis_tlast = post_fifo_axis_tlast;
344+
assign m_axis_tid = post_fifo_axis_tid;
345+
assign m_axis_tdest = post_fifo_axis_tdest;
346+
assign m_axis_tuser = post_fifo_axis_tuser;
347+
348+
end
349+
350+
endgenerate
351+
369352
endmodule
370353

371354
`resetall

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