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alexforencichalexforencich
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Handle some zero-valued signal width settings
1 parent 907081d commit e4b4762

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4 files changed

+33
-23
lines changed

4 files changed

+33
-23
lines changed

‎rtl/axis_arb_mux.v‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,6 +95,8 @@ module axis_arb_mux #
9595

9696
parameter CL_S_COUNT = $clog2(S_COUNT);
9797

98+
parameter S_ID_WIDTH_INT = S_ID_WIDTH > 0 ? S_ID_WIDTH : 1;
99+
98100
// check configuration
99101
initial begin
100102
if (UPDATE_TID) begin
@@ -135,7 +137,7 @@ wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[grant_encoded*KEEP_WIDTH +
135137
wire current_s_tvalid = s_axis_tvalid[grant_encoded];
136138
wire current_s_tready = s_axis_tready[grant_encoded];
137139
wire current_s_tlast = s_axis_tlast[grant_encoded];
138-
wire [S_ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH];
140+
wire [S_ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH_INT];
139141
wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
140142
wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
141143

‎rtl/axis_demux.v‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,8 @@ module axis_demux #
9696

9797
parameter CL_M_COUNT = $clog2(M_COUNT);
9898

99+
parameter M_DEST_WIDTH_INT = M_DEST_WIDTH > 0 ? M_DEST_WIDTH : 1;
100+
99101
// check configuration
100102
initial begin
101103
if (TDEST_ROUTE) begin
@@ -201,15 +203,15 @@ reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
201203
reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next;
202204
reg m_axis_tlast_reg = 1'b0;
203205
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
204-
reg [M_DEST_WIDTH-1:0] m_axis_tdest_reg = {M_DEST_WIDTH{1'b0}};
206+
reg [M_DEST_WIDTH-1:0] m_axis_tdest_reg = {M_DEST_WIDTH_INT{1'b0}};
205207
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
206208

207209
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
208210
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
209211
reg [M_COUNT-1:0] temp_m_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_tvalid_next;
210212
reg temp_m_axis_tlast_reg = 1'b0;
211213
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
212-
reg [M_DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {M_DEST_WIDTH{1'b0}};
214+
reg [M_DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {M_DEST_WIDTH_INT{1'b0}};
213215
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
214216

215217
// datapath control
@@ -222,7 +224,7 @@ assign m_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_axis_tkeep_reg}} : {M_COUNT*KEEP
222224
assign m_axis_tvalid = m_axis_tvalid_reg;
223225
assign m_axis_tlast = {M_COUNT{m_axis_tlast_reg}};
224226
assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
225-
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*M_DEST_WIDTH{1'b0}};
227+
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*M_DEST_WIDTH_INT{1'b0}};
226228
assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
227229

228230
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)

‎rtl/axis_ram_switch.v‎

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,9 @@ module axis_ram_switch #
144144
parameter CL_S_COUNT = $clog2(S_COUNT);
145145
parameter CL_M_COUNT = $clog2(M_COUNT);
146146

147+
parameter S_ID_WIDTH_INT = S_ID_WIDTH > 0 ? S_ID_WIDTH : 1;
148+
parameter M_DEST_WIDTH_INT = M_DEST_WIDTH > 0 ? M_DEST_WIDTH : 1;
149+
147150
// force keep width to 1 when disabled
148151
parameter S_KEEP_WIDTH_INT = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1;
149152
parameter M_KEEP_WIDTH_INT = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1;
@@ -405,8 +408,8 @@ generate
405408
.M_DATA_WIDTH(DATA_WIDTH),
406409
.M_KEEP_ENABLE(1),
407410
.M_KEEP_WIDTH(KEEP_WIDTH),
408-
.ID_ENABLE(ID_ENABLE),
409-
.ID_WIDTH(S_ID_WIDTH),
411+
.ID_ENABLE(ID_ENABLE && S_ID_WIDTH > 0),
412+
.ID_WIDTH(S_ID_WIDTH_INT),
410413
.DEST_ENABLE(1),
411414
.DEST_WIDTH(S_DEST_WIDTH),
412415
.USER_ENABLE(USER_ENABLE),
@@ -421,7 +424,7 @@ generate
421424
.s_axis_tvalid(s_axis_tvalid[m]),
422425
.s_axis_tready(s_axis_tready[m]),
423426
.s_axis_tlast(s_axis_tlast[m]),
424-
.s_axis_tid(s_axis_tid[S_ID_WIDTH*m +: S_ID_WIDTH]),
427+
.s_axis_tid(s_axis_tid[S_ID_WIDTH*m +: S_ID_WIDTH_INT]),
425428
.s_axis_tdest(s_axis_tdest[S_DEST_WIDTH*m +: S_DEST_WIDTH]),
426429
.s_axis_tuser(s_axis_tuser[USER_WIDTH*m +: USER_WIDTH]),
427430
// AXI output
@@ -585,7 +588,7 @@ generate
585588
reg [ADDR_WIDTH-1:0] cmd_len_reg = {ADDR_WIDTH{1'b0}}, cmd_len_next;
586589
reg [CMD_ADDR_WIDTH-1:0] cmd_id_reg = {CMD_ADDR_WIDTH{1'b0}}, cmd_id_next;
587590
reg [KEEP_WIDTH-1:0] cmd_tkeep_reg = {KEEP_WIDTH{1'b0}}, cmd_tkeep_next;
588-
reg [S_ID_WIDTH-1:0] cmd_tid_reg = {S_ID_WIDTH{1'b0}}, cmd_tid_next;
591+
reg [S_ID_WIDTH-1:0] cmd_tid_reg = {S_ID_WIDTH_INT{1'b0}}, cmd_tid_next;
589592
reg [S_DEST_WIDTH-1:0] cmd_tdest_reg = {S_DEST_WIDTH{1'b0}}, cmd_tdest_next;
590593
reg [USER_WIDTH-1:0] cmd_tuser_reg = {USER_WIDTH{1'b0}}, cmd_tuser_next;
591594
reg [M_COUNT-1:0] cmd_valid_reg = 0, cmd_valid_next;
@@ -608,7 +611,7 @@ generate
608611
assign int_cmd_len[m*ADDR_WIDTH +: ADDR_WIDTH] = cmd_len_reg;
609612
assign int_cmd_id[m*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH] = cmd_id_reg;
610613
assign int_cmd_tkeep[m*KEEP_WIDTH +: KEEP_WIDTH] = cmd_tkeep_reg;
611-
assign int_cmd_tid[m*S_ID_WIDTH +: S_ID_WIDTH] = cmd_tid_reg;
614+
assign int_cmd_tid[m*S_ID_WIDTH +: S_ID_WIDTH_INT] = cmd_tid_reg;
612615
assign int_cmd_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH] = cmd_tdest_reg;
613616
assign int_cmd_tuser[m*USER_WIDTH +: USER_WIDTH] = cmd_tuser_reg;
614617
assign int_cmd_valid[m*M_COUNT +: M_COUNT] = cmd_valid_reg;
@@ -854,7 +857,7 @@ generate
854857
cmd_len_mux = int_cmd_len[grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
855858
cmd_id_mux = int_cmd_id[grant_encoded*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH];
856859
cmd_tkeep_mux = int_cmd_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
857-
cmd_tid_mux = int_cmd_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH];
860+
cmd_tid_mux = int_cmd_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH_INT];
858861
if (UPDATE_TID && S_COUNT > 1) begin
859862
cmd_tid_mux[M_ID_WIDTH-1:M_ID_WIDTH-CL_S_COUNT] = grant_encoded;
860863
end
@@ -879,7 +882,7 @@ generate
879882

880883
reg [KEEP_WIDTH-1:0] last_cycle_tkeep_reg = {KEEP_WIDTH{1'b0}}, last_cycle_tkeep_next;
881884
reg [M_ID_WIDTH-1:0] tid_reg = {M_ID_WIDTH{1'b0}}, tid_next;
882-
reg [M_DEST_WIDTH-1:0] tdest_reg = {M_DEST_WIDTH{1'b0}}, tdest_next;
885+
reg [M_DEST_WIDTH-1:0] tdest_reg = {M_DEST_WIDTH_INT{1'b0}}, tdest_next;
883886
reg [USER_WIDTH-1:0] tuser_reg = {USER_WIDTH{1'b0}}, tuser_next;
884887

885888
reg [DATA_WIDTH-1:0] out_axis_tdata_reg = {DATA_WIDTH{1'b0}}, out_axis_tdata_next;
@@ -888,7 +891,7 @@ generate
888891
wire out_axis_tready;
889892
reg out_axis_tlast_reg = 1'b0, out_axis_tlast_next;
890893
reg [M_ID_WIDTH-1:0] out_axis_tid_reg = {M_ID_WIDTH{1'b0}}, out_axis_tid_next;
891-
reg [M_DEST_WIDTH-1:0] out_axis_tdest_reg = {M_DEST_WIDTH{1'b0}}, out_axis_tdest_next;
894+
reg [M_DEST_WIDTH-1:0] out_axis_tdest_reg = {M_DEST_WIDTH_INT{1'b0}}, out_axis_tdest_next;
892895
reg [USER_WIDTH-1:0] out_axis_tuser_reg = {USER_WIDTH{1'b0}}, out_axis_tuser_next;
893896

894897
reg [RAM_ADDR_WIDTH-1:0] ram_rd_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, ram_rd_addr_next;
@@ -1104,8 +1107,8 @@ generate
11041107
.M_KEEP_WIDTH(M_KEEP_WIDTH),
11051108
.ID_ENABLE(ID_ENABLE),
11061109
.ID_WIDTH(M_ID_WIDTH),
1107-
.DEST_ENABLE(1),
1108-
.DEST_WIDTH(M_DEST_WIDTH),
1110+
.DEST_ENABLE(M_DEST_WIDTH > 0),
1111+
.DEST_WIDTH(M_DEST_WIDTH_INT),
11091112
.USER_ENABLE(USER_ENABLE),
11101113
.USER_WIDTH(USER_WIDTH)
11111114
)
@@ -1128,7 +1131,7 @@ generate
11281131
.m_axis_tready(m_axis_tready[n]),
11291132
.m_axis_tlast(m_axis_tlast[n]),
11301133
.m_axis_tid(m_axis_tid[M_ID_WIDTH*n +: M_ID_WIDTH]),
1131-
.m_axis_tdest(m_axis_tdest[M_DEST_WIDTH*n +: M_DEST_WIDTH]),
1134+
.m_axis_tdest(m_axis_tdest[M_DEST_WIDTH*n +: M_DEST_WIDTH_INT]),
11321135
.m_axis_tuser(m_axis_tuser[USER_WIDTH*n +: USER_WIDTH])
11331136
);
11341137
end // m_ifaces

‎rtl/axis_switch.v‎

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,9 @@ module axis_switch #
116116
parameter CL_S_COUNT = $clog2(S_COUNT);
117117
parameter CL_M_COUNT = $clog2(M_COUNT);
118118

119+
parameter S_ID_WIDTH_INT = S_ID_WIDTH > 0 ? S_ID_WIDTH : 1;
120+
parameter M_DEST_WIDTH_INT = M_DEST_WIDTH > 0 ? M_DEST_WIDTH : 1;
121+
119122
integer i, j;
120123

121124
// check configuration
@@ -275,8 +278,8 @@ generate
275278
.KEEP_ENABLE(KEEP_ENABLE),
276279
.KEEP_WIDTH(KEEP_WIDTH),
277280
.LAST_ENABLE(1),
278-
.ID_ENABLE(ID_ENABLE),
279-
.ID_WIDTH(S_ID_WIDTH),
281+
.ID_ENABLE(ID_ENABLE && S_ID_WIDTH > 0),
282+
.ID_WIDTH(S_ID_WIDTH_INT),
280283
.DEST_ENABLE(1),
281284
.DEST_WIDTH(S_DEST_WIDTH),
282285
.USER_ENABLE(USER_ENABLE),
@@ -292,7 +295,7 @@ generate
292295
.s_axis_tvalid(s_axis_tvalid[m]),
293296
.s_axis_tready(s_axis_tready[m]),
294297
.s_axis_tlast(s_axis_tlast[m]),
295-
.s_axis_tid(s_axis_tid[m*S_ID_WIDTH +: S_ID_WIDTH]),
298+
.s_axis_tid(s_axis_tid[m*S_ID_WIDTH +: S_ID_WIDTH_INT]),
296299
.s_axis_tdest(s_axis_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH]),
297300
.s_axis_tuser(s_axis_tuser[m*USER_WIDTH +: USER_WIDTH]),
298301
// AXI output
@@ -301,7 +304,7 @@ generate
301304
.m_axis_tvalid(int_s_axis_tvalid[m]),
302305
.m_axis_tready(int_s_axis_tready[m]),
303306
.m_axis_tlast(int_s_axis_tlast[m]),
304-
.m_axis_tid(int_s_axis_tid[m*S_ID_WIDTH +: S_ID_WIDTH]),
307+
.m_axis_tid(int_s_axis_tid[m*S_ID_WIDTH +: S_ID_WIDTH_INT]),
305308
.m_axis_tdest(int_s_axis_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH]),
306309
.m_axis_tuser(int_s_axis_tuser[m*USER_WIDTH +: USER_WIDTH])
307310
);
@@ -348,7 +351,7 @@ generate
348351
m_axis_tkeep_mux = int_s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
349352
m_axis_tvalid_mux = int_axis_tvalid[grant_encoded*M_COUNT+n] && grant_valid;
350353
m_axis_tlast_mux = int_s_axis_tlast[grant_encoded];
351-
m_axis_tid_mux = int_s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH];
354+
m_axis_tid_mux = int_s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH_INT];
352355
if (UPDATE_TID && S_COUNT > 1) begin
353356
m_axis_tid_mux[M_ID_WIDTH-1:M_ID_WIDTH-CL_S_COUNT] = grant_encoded;
354357
end
@@ -371,8 +374,8 @@ generate
371374
.LAST_ENABLE(1),
372375
.ID_ENABLE(ID_ENABLE),
373376
.ID_WIDTH(M_ID_WIDTH),
374-
.DEST_ENABLE(1),
375-
.DEST_WIDTH(M_DEST_WIDTH),
377+
.DEST_ENABLE(M_DEST_WIDTH > 0),
378+
.DEST_WIDTH(M_DEST_WIDTH_INT),
376379
.USER_ENABLE(USER_ENABLE),
377380
.USER_WIDTH(USER_WIDTH),
378381
.REG_TYPE(M_REG_TYPE)
@@ -396,7 +399,7 @@ generate
396399
.m_axis_tready(m_axis_tready[n]),
397400
.m_axis_tlast(m_axis_tlast[n]),
398401
.m_axis_tid(m_axis_tid[n*M_ID_WIDTH +: M_ID_WIDTH]),
399-
.m_axis_tdest(m_axis_tdest[n*M_DEST_WIDTH +: M_DEST_WIDTH]),
402+
.m_axis_tdest(m_axis_tdest[n*M_DEST_WIDTH +: M_DEST_WIDTH_INT]),
400403
.m_axis_tuser(m_axis_tuser[n*USER_WIDTH +: USER_WIDTH])
401404
);
402405
end // m_ifaces

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