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Update testbenches to use instances()
1 parent a28eeae commit 17b1f25

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5 files changed

+6
-8
lines changed

5 files changed

+6
-8
lines changed

tb/i2c.py

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -279,8 +279,7 @@ def logic():
279279
# send stop
280280
yield send_stop()
281281

282-
283-
return logic
282+
return instances()
284283

285284

286285
class I2CMem(object):
@@ -506,7 +505,6 @@ def logic():
506505
# no match, wait for start
507506
break
508507

509-
510-
return logic
508+
return instances()
511509

512510

tb/test_i2c_init.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -253,7 +253,7 @@ def check():
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254254
raise StopSimulation
255255

256-
return dut, cmd_sink_logic, data_sink_logic, clkgen, check
256+
return instances()
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258258
def test_bench():
259259
sim = Simulation(bench())

tb/test_i2c_master.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -432,7 +432,7 @@ def check():
432432

433433
raise StopSimulation
434434

435-
return dut, cmd_source_logic, data_source_logic, data_sink_logic, i2c_mem_logic1, i2c_mem_logic2, bus, clkgen, check
435+
return instances()
436436

437437
def test_bench():
438438
sim = Simulation(bench())

tb/test_i2c_master_wbs_16.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -371,7 +371,7 @@ def check():
371371

372372
raise StopSimulation
373373

374-
return dut, wbm_logic, i2c_mem_logic1, i2c_mem_logic2, bus, clkgen, check
374+
return instances()
375375

376376
def test_bench():
377377
sim = Simulation(bench())

tb/test_i2c_master_wbs_8.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -369,7 +369,7 @@ def check():
369369

370370
raise StopSimulation
371371

372-
return dut, wbm_logic, i2c_mem_logic1, i2c_mem_logic2, bus, clkgen, check
372+
return instances()
373373

374374
def test_bench():
375375
sim = Simulation(bench())

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