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Add nonexistent device test
1 parent e2496aa commit 57111a8

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2 files changed

+60
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tb/test_i2c_master.py

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -399,6 +399,37 @@ def check():
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yield delay(100)
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yield clk.posedge
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print("test 5: write to nonexistent device")
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current_test.next = 5
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cmd_source.send([(
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0x52, # address
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0, # start
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0, # read
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0, # write
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1, # write_multiple
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1 # stop
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)])
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data_source.send((b'\x00\x04'+b'\xde\xad\xbe\xef'))
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got_missed_ack = False
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for k in range(1000):
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got_missed_ack |= missed_ack
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yield clk.posedge
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assert got_missed_ack
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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while busy or bus_active or not cmd_source.empty():
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yield clk.posedge
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yield clk.posedge
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yield delay(100)
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raise StopSimulation
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return dut, cmd_source_logic, data_source_logic, data_sink_logic, i2c_mem_logic1, i2c_mem_logic2, bus, clkgen, check

tb/test_i2c_master_wbs_8.py

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -338,6 +338,35 @@ def check():
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yield delay(100)
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yield clk.posedge
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print("test 5: write to nonexistent device")
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current_test.next = 5
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wbm_inst.init_write(2, b'\x52\x04\x00')
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wbm_inst.init_write(3, b'\x04\x04')
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wbm_inst.init_write(3, b'\x04\xde')
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wbm_inst.init_write(3, b'\x04\xad')
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wbm_inst.init_write(3, b'\x04\xbe')
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wbm_inst.init_write(3, b'\x14\xef')
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yield wbm_inst.wait()
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yield clk.posedge
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got_missed_ack = False
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while True:
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wbm_inst.init_read(0, 1)
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yield wbm_inst.wait()
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data = wbm_inst.get_read_data()
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if data[1][0] & 0x08:
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got_missed_ack = True
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if data[1][0] & 0x03 == 0:
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break
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assert got_missed_ack
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yield delay(100)
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raise StopSimulation
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return dut, wbm_logic, i2c_mem_logic1, i2c_mem_logic2, bus, clkgen, check

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