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Update wishbone model
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tb/wb.py

Lines changed: 39 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
"""
22
3-
Copyright (c) 2015-2017 Alex Forencich
3+
Copyright (c) 2015-2016 Alex Forencich
44
55
Permission is hereby granted, free of charge, to any person obtaining a copy
66
of this software and associated documentation files (the "Software"), to deal
@@ -74,7 +74,7 @@ def wait(self):
7474
yield self.clk.posedge
7575

7676
def read_data_ready(self):
77-
return len(self.read_data_queue) > 0
77+
return not self.read_data_queue
7878

7979
def get_read_data(self):
8080
return self.read_data_queue.pop(0)
@@ -116,28 +116,28 @@ def create_logic(self,
116116
if self.has_logic:
117117
raise Exception("Logic already instantiated!")
118118

119+
if dat_i is not None:
120+
assert len(dat_i) % 8 == 0
121+
w = len(dat_i)
122+
if dat_o is not None:
123+
assert len(dat_o) % 8 == 0
124+
w = len(dat_o)
125+
if dat_i is not None and dat_o is not None:
126+
assert len(dat_i) == len(dat_o)
127+
128+
bw = int(w/8) # width of bus in bytes
129+
ww = len(sel_o) # width of bus in words
130+
ws = int(bw/ww) # word size in bytes
131+
132+
assert ww in (1, 2, 4, 8)
133+
assert ws in (1, 2, 4, 8)
134+
119135
self.has_logic = True
120136
self.clk = clk
121137
self.cyc_o = cyc_o
122138

123139
@instance
124140
def logic():
125-
if dat_i is not None:
126-
assert len(dat_i) % 8 == 0
127-
w = len(dat_i)
128-
if dat_o is not None:
129-
assert len(dat_o) % 8 == 0
130-
w = len(dat_o)
131-
if dat_i is not None and dat_o is not None:
132-
assert len(dat_i) == len(dat_o)
133-
134-
bw = int(w/8) # width of bus in bytes
135-
ww = len(sel_o) # width of bus in words
136-
ws = int(bw/ww) # word size in bytes
137-
138-
assert ww in (1, 2, 4, 8)
139-
assert ws in (1, 2, 4, 8)
140-
141141
while True:
142142
yield clk.posedge
143143

@@ -309,7 +309,7 @@ def logic():
309309

310310
self.read_data_queue.append((addr, data))
311311

312-
return logic
312+
return instances()
313313

314314

315315
class WBRam(object):
@@ -371,30 +371,30 @@ def create_port(self,
371371
ack_o=Signal(bool(0)),
372372
cyc_i=Signal(bool(0)),
373373
latency=1,
374-
async=False,
374+
asynchronous=False,
375375
name=None
376376
):
377377

378+
if dat_i is not None:
379+
assert len(dat_i) % 8 == 0
380+
w = len(dat_i)
381+
if dat_o is not None:
382+
assert len(dat_o) % 8 == 0
383+
w = len(dat_o)
384+
if dat_i is not None and dat_o is not None:
385+
assert len(dat_i) == len(dat_o)
386+
387+
bw = int(w/8) # width of bus in bytes
388+
ww = len(sel_i) # width of bus in words
389+
ws = int(bw/ww) # word size in bytes
390+
391+
assert ww in (1, 2, 4, 8)
392+
assert ws in (1, 2, 4, 8)
393+
378394
@instance
379395
def logic():
380-
if dat_i is not None:
381-
assert len(dat_i) % 8 == 0
382-
w = len(dat_i)
383-
if dat_o is not None:
384-
assert len(dat_o) % 8 == 0
385-
w = len(dat_o)
386-
if dat_i is not None and dat_o is not None:
387-
assert len(dat_i) == len(dat_o)
388-
389-
bw = int(w/8) # width of bus in bytes
390-
ww = len(sel_i) # width of bus in words
391-
ws = int(bw/ww) # word size in bytes
392-
393-
assert ww in (1, 2, 4, 8)
394-
assert ws in (1, 2, 4, 8)
395-
396396
while True:
397-
if async:
397+
if asynchronous:
398398
yield adr_i, cyc_i, stb_i
399399
else:
400400
yield clk.posedge
@@ -405,7 +405,7 @@ def logic():
405405
addr = int(int(adr_i)/ww)*ww
406406

407407
if cyc_i & stb_i & ~ack_o:
408-
if async:
408+
if asynchronous:
409409
yield delay(latency)
410410
else:
411411
for i in range(latency):
@@ -437,5 +437,5 @@ def logic():
437437
if name is not None:
438438
print("[%s] Read word a:0x%08x d:%s" % (name, addr, " ".join(("{:02x}".format(c) for c in bytearray(data)))))
439439

440-
return logic
440+
return instances()
441441

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