Rewrite resets

Author: alexforencich

rtl/i2c_init.v

@@ -431,6 +431,30 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    state_reg <= state_next;
+
+    // read init_data ROM
+    init_data_reg <= init_data[address_next];
+
+    address_reg <= address_next;
+    address_ptr_reg <= address_ptr_next;
+    data_ptr_reg <= data_ptr_next;
+
+    cur_address_reg <= cur_address_next;
+
+    cmd_address_reg <= cmd_address_next;
+    cmd_start_reg <= cmd_start_next;
+    cmd_write_reg <= cmd_write_next;
+    cmd_stop_reg <= cmd_stop_next;
+    cmd_valid_reg <= cmd_valid_next;
+
+    data_out_reg <= data_out_next;
+    data_out_valid_reg <= data_out_valid_next;
+
+    start_flag_reg <= start & start_flag_next;
+
+    busy_reg <= (state_reg != STATE_IDLE);
+
     if (rst) begin
         state_reg <= STATE_IDLE;
 
@@ -449,33 +473,7 @@ always @(posedge clk) begin
         start_flag_reg <= 1'b0;
 
         busy_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-
-        // read init_data ROM
-        init_data_reg <= init_data[address_next];
-
-        address_reg <= address_next;
-        address_ptr_reg <= address_ptr_next;
-        data_ptr_reg <= data_ptr_next;
-
-        cur_address_reg <= cur_address_next;
-
-        cmd_valid_reg <= cmd_valid_next;
-
-        data_out_valid_reg <= data_out_valid_next;
-
-        start_flag_reg <= start & start_flag_next;
-
-        busy_reg <= (state_reg != STATE_IDLE);
     end
-
-    cmd_address_reg <= cmd_address_next;
-    cmd_start_reg <= cmd_start_next;
-    cmd_write_reg <= cmd_write_next;
-    cmd_stop_reg <= cmd_stop_next;
-
-    data_out_reg <= data_out_next;
 end
 
 endmodule

rtl/i2c_master.v

@@ -827,49 +827,8 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        state_reg <= STATE_IDLE;
-        phy_state_reg <= PHY_STATE_IDLE;
-        delay_reg <= 16'd0;
-        delay_scl_reg <= 1'b0;
-        delay_sda_reg <= 1'b0;
-        cmd_ready_reg <= 1'b0;
-        data_in_ready_reg <= 1'b0;
-        data_out_valid_reg <= 1'b0;
-        scl_o_reg <= 1'b1;
-        sda_o_reg <= 1'b1;
-        busy_reg <= 1'b0;
-        bus_active_reg <= 1'b0;
-        bus_control_reg <= 1'b0;
-        missed_ack_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-        phy_state_reg <= phy_state_next;
-
-        delay_reg <= delay_next;
-        delay_scl_reg <= delay_scl_next;
-        delay_sda_reg <= delay_sda_next;
-
-        cmd_ready_reg <= cmd_ready_next;
-        data_in_ready_reg <= data_in_ready_next;
-        data_out_valid_reg <= data_out_valid_next;
-
-        scl_o_reg <= scl_o_next;
-        sda_o_reg <= sda_o_next;
-
-        busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE);
-
-        if (start_bit) begin
-            bus_active_reg <= 1'b1;
-        end else if (stop_bit) begin
-            bus_active_reg <= 1'b0;
-        end else begin
-            bus_active_reg <= bus_active_reg;
-        end
-
-        bus_control_reg <= bus_control_next;
-        missed_ack_reg <= missed_ack_next;
-    end
+    state_reg <= state_next;
+    phy_state_reg <= phy_state_next;
 
     phy_rx_data_reg <= phy_rx_data_next;
 
@@ -881,15 +840,58 @@ always @(posedge clk) begin
     mode_write_multiple_reg <= mode_write_multiple_next;
     mode_stop_reg <= mode_stop_next;
 
+    delay_reg <= delay_next;
+    delay_scl_reg <= delay_scl_next;
+    delay_sda_reg <= delay_sda_next;
+
     bit_count_reg <= bit_count_next;
 
+    cmd_ready_reg <= cmd_ready_next;
+
+    data_in_ready_reg <= data_in_ready_next;
+
     data_out_reg <= data_out_next;
     data_out_last_reg <= data_out_last_next;
+    data_out_valid_reg <= data_out_valid_next;
 
     scl_i_reg <= scl_i;
     sda_i_reg <= sda_i;
+
+    scl_o_reg <= scl_o_next;
+    sda_o_reg <= sda_o_next;
+
     last_scl_i_reg <= scl_i_reg;
     last_sda_i_reg <= sda_i_reg;
+
+    busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE);
+
+    if (start_bit) begin
+        bus_active_reg <= 1'b1;
+    end else if (stop_bit) begin
+        bus_active_reg <= 1'b0;
+    end else begin
+        bus_active_reg <= bus_active_reg;
+    end
+
+    bus_control_reg <= bus_control_next;
+    missed_ack_reg <= missed_ack_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        phy_state_reg <= PHY_STATE_IDLE;
+        delay_reg <= 16'd0;
+        delay_scl_reg <= 1'b0;
+        delay_sda_reg <= 1'b0;
+        cmd_ready_reg <= 1'b0;
+        data_in_ready_reg <= 1'b0;
+        data_out_valid_reg <= 1'b0;
+        scl_o_reg <= 1'b1;
+        sda_o_reg <= 1'b1;
+        busy_reg <= 1'b0;
+        bus_active_reg <= 1'b0;
+        bus_control_reg <= 1'b0;
+        missed_ack_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/i2c_master_axil.v

@@ -640,6 +640,34 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    s_axil_awready_reg <= s_axil_awready_next;
+    s_axil_wready_reg <= s_axil_wready_next;
+    s_axil_bvalid_reg <= s_axil_bvalid_next;
+    s_axil_arready_reg <= s_axil_arready_next;
+    s_axil_rdata_reg <= s_axil_rdata_next;
+    s_axil_rvalid_reg <= s_axil_rvalid_next;
+
+    cmd_address_reg <= cmd_address_next;
+    cmd_start_reg <= cmd_start_next;
+    cmd_read_reg <= cmd_read_next;
+    cmd_write_reg <= cmd_write_next;
+    cmd_write_multiple_reg <= cmd_write_multiple_next;
+    cmd_stop_reg <= cmd_stop_next;
+    cmd_valid_reg <= cmd_valid_next;
+
+    data_in_reg <= data_in_next;
+    data_in_valid_reg <= data_in_valid_next;
+    data_in_last_reg <= data_in_last_next;
+
+    data_out_ready_reg <= data_out_ready_next;
+
+    prescale_reg <= prescale_next;
+
+    missed_ack_reg <= missed_ack_next;
+
+    cmd_fifo_overflow_reg <= cmd_fifo_overflow_next;
+    write_fifo_overflow_reg <= write_fifo_overflow_next;
+
     if (rst) begin
         s_axil_awready_reg <= 1'b0;
         s_axil_wready_reg <= 1'b0;
@@ -653,32 +681,7 @@ always @(posedge clk) begin
         missed_ack_reg <= 1'b0;
         cmd_fifo_overflow_reg <= 1'b0;
         write_fifo_overflow_reg <= 1'b0;
-    end else begin
-        s_axil_awready_reg <= s_axil_awready_next;
-        s_axil_wready_reg <= s_axil_wready_next;
-        s_axil_bvalid_reg <= s_axil_bvalid_next;
-        s_axil_arready_reg <= s_axil_arready_next;
-        s_axil_rvalid_reg <= s_axil_rvalid_next;
-        cmd_valid_reg <= cmd_valid_next;
-        data_in_valid_reg <= data_in_valid_next;
-        data_out_ready_reg <= data_out_ready_next;
-        prescale_reg <= prescale_next;
-        missed_ack_reg <= missed_ack_next;
-        cmd_fifo_overflow_reg <= cmd_fifo_overflow_next;
-        write_fifo_overflow_reg <= write_fifo_overflow_next;
     end
-
-    s_axil_rdata_reg <= s_axil_rdata_next;
-
-    cmd_address_reg <= cmd_address_next;
-    cmd_start_reg <= cmd_start_next;
-    cmd_read_reg <= cmd_read_next;
-    cmd_write_reg <= cmd_write_next;
-    cmd_write_multiple_reg <= cmd_write_multiple_next;
-    cmd_stop_reg <= cmd_stop_next;
-    
-    data_in_reg <= data_in_next;
-    data_in_last_reg <= data_in_last_next;
 end
 
 i2c_master

rtl/i2c_master_wbs_16.v

@@ -585,37 +585,40 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        wbs_ack_o_reg <= 1'b0;
-        cmd_valid_reg <= 1'b0;
-        data_in_valid_reg <= 1'b0;
-        data_out_ready_reg <= 1'b0;
-        prescale_reg <= DEFAULT_PRESCALE;
-        missed_ack_reg <= 1'b0;
-        cmd_fifo_overflow_reg <= 0;
-        write_fifo_overflow_reg <= 0;
-    end else begin
-        wbs_ack_o_reg <= wbs_ack_o_next;
-        cmd_valid_reg <= cmd_valid_next;
-        data_in_valid_reg <= data_in_valid_next;
-        data_out_ready_reg <= data_out_ready_next;
-        prescale_reg <= prescale_next;
-        missed_ack_reg <= missed_ack_next;
-        cmd_fifo_overflow_reg <= cmd_fifo_overflow_next;
-        write_fifo_overflow_reg <= write_fifo_overflow_next;
-    end
-
     wbs_dat_o_reg <= wbs_dat_o_next;
+    wbs_ack_o_reg <= wbs_ack_o_next;
 
     cmd_address_reg <= cmd_address_next;
     cmd_start_reg <= cmd_start_next;
     cmd_read_reg <= cmd_read_next;
     cmd_write_reg <= cmd_write_next;
     cmd_write_multiple_reg <= cmd_write_multiple_next;
     cmd_stop_reg <= cmd_stop_next;
-    
+    cmd_valid_reg <= cmd_valid_next;
+
     data_in_reg <= data_in_next;
+    data_in_valid_reg <= data_in_valid_next;
     data_in_last_reg <= data_in_last_next;
+
+    data_out_ready_reg <= data_out_ready_next;
+
+    prescale_reg <= prescale_next;
+
+    missed_ack_reg <= missed_ack_next;
+
+    cmd_fifo_overflow_reg <= cmd_fifo_overflow_next;
+    write_fifo_overflow_reg <= write_fifo_overflow_next;
+
+    if (rst) begin
+        wbs_ack_o_reg <= 1'b0;
+        cmd_valid_reg <= 1'b0;
+        data_in_valid_reg <= 1'b0;
+        data_out_ready_reg <= 1'b0;
+        prescale_reg <= DEFAULT_PRESCALE;
+        missed_ack_reg <= 1'b0;
+        cmd_fifo_overflow_reg <= 0;
+        write_fifo_overflow_reg <= 0;
+    end
 end
 
 i2c_master

rtl/i2c_master_wbs_8.v

@@ -575,37 +575,40 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        wbs_ack_o_reg <= 1'b0;
-        cmd_valid_reg <= 1'b0;
-        data_in_valid_reg <= 1'b0;
-        data_out_ready_reg <= 1'b0;
-        prescale_reg <= DEFAULT_PRESCALE;
-        missed_ack_reg <= 1'b0;
-        cmd_fifo_overflow_reg <= 1'b0;
-        write_fifo_overflow_reg <= 1'b0;
-    end else begin
-        wbs_ack_o_reg <= wbs_ack_o_next;
-        cmd_valid_reg <= cmd_valid_next;
-        data_in_valid_reg <= data_in_valid_next;
-        data_out_ready_reg <= data_out_ready_next;
-        prescale_reg <= prescale_next;
-        missed_ack_reg <= missed_ack_next;
-        cmd_fifo_overflow_reg <= cmd_fifo_overflow_next;
-        write_fifo_overflow_reg <= write_fifo_overflow_next;
-    end
-
     wbs_dat_o_reg <= wbs_dat_o_next;
+    wbs_ack_o_reg <= wbs_ack_o_next;
 
     cmd_address_reg <= cmd_address_next;
     cmd_start_reg <= cmd_start_next;
     cmd_read_reg <= cmd_read_next;
     cmd_write_reg <= cmd_write_next;
     cmd_write_multiple_reg <= cmd_write_multiple_next;
     cmd_stop_reg <= cmd_stop_next;
-    
+    cmd_valid_reg <= cmd_valid_next;
+
     data_in_reg <= data_in_next;
+    data_in_valid_reg <= data_in_valid_next;
     data_in_last_reg <= data_in_last_next;
+
+    data_out_ready_reg <= data_out_ready_next;
+
+    prescale_reg <= prescale_next;
+
+    missed_ack_reg <= missed_ack_next;
+
+    cmd_fifo_overflow_reg <= cmd_fifo_overflow_next;
+    write_fifo_overflow_reg <= write_fifo_overflow_next;
+
+    if (rst) begin
+        wbs_ack_o_reg <= 1'b0;
+        cmd_valid_reg <= 1'b0;
+        data_in_valid_reg <= 1'b0;
+        data_out_ready_reg <= 1'b0;
+        prescale_reg <= DEFAULT_PRESCALE;
+        missed_ack_reg <= 1'b0;
+        cmd_fifo_overflow_reg <= 0;
+        write_fifo_overflow_reg <= 0;
+    end
 end
 
 i2c_master