Add read data valid bit

Author: alexforencich

rtl/i2c_master_wbs_16.v

@@ -140,13 +140,14 @@ Data register:
 
 | Addr  | Name          |   Bit 15  |   Bit 14  |   Bit 13  |   Bit 12  |   Bit 11  |   Bit 10  |   Bit 9   |   Bit 8   |
 |-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|
-| 0x04  | Data          |     -     |     -     |     -     |     -     |     -     |     -     |     -     | data_last |
+| 0x04  | Data          |     -     |     -     |     -     |     -     |     -     |     -     | data_last | data_valid|
 
 | Addr  | Name          |   Bit 7   |   Bit 6   |   Bit 5   |   Bit 4   |   Bit 3   |   Bit 2   |   Bit 1   |   Bit 0   |
 |-------|---------------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|
 | 0x04  | Data          |                                           data[7:0]                                           |
 
 data: I2C data, write to push on write data FIFO, read to pull from read data FIFO
+data_valid: indicates valid read data, must be accessed with atomic 16 bit reads and writes
 data_last: indicate last byte of block write (write_multiple), must be accessed with atomic 16 bit reads and writes
 
 Prescale register:
@@ -498,7 +499,7 @@ always @* begin
 
                         if (wbs_sel_i[1]) begin
                             // only valid with atomic 16 bit write
-                            data_in_last_next = wbs_dat_i[8];
+                            data_in_last_next = wbs_dat_i[9];
                         end else begin
                             data_in_last_next = 1'b0;
                         end
@@ -565,8 +566,9 @@ always @* begin
                 3'h4: begin
                     // data
                     wbs_dat_o_next[7:0] = data_out;
-                    wbs_dat_o_next[8] = data_out_last;
-                    wbs_dat_o_next[15:9] = 7'd0;
+                    wbs_dat_o_next[8] = data_out_valid;
+                    wbs_dat_o_next[9] = data_out_last;
+                    wbs_dat_o_next[15:10] = 6'd0;
 
                     if (wbs_sel_i[0]) begin
                         data_out_ready_next = !wbs_ack_o_reg && data_out_valid;

tb/test_i2c_master_wbs_16.py

@@ -254,16 +254,16 @@ def check():
         yield clk.posedge
 
         data = wbm_inst.get_read_data()
-        assert data[1] == b'\x11\x00'
+        assert data[1] == b'\x11\x01'
 
         data = wbm_inst.get_read_data()
-        assert data[1] == b'\x22\x00'
+        assert data[1] == b'\x22\x01'
 
         data = wbm_inst.get_read_data()
-        assert data[1] == b'\x33\x00'
+        assert data[1] == b'\x33\x01'
 
         data = wbm_inst.get_read_data()
-        assert data[1] == b'\x44\x01'
+        assert data[1] == b'\x44\x03'
 
         yield delay(100)
 
@@ -276,7 +276,7 @@ def check():
         wbm_inst.init_write(4, b'\x44\x00')
         wbm_inst.init_write(4, b'\x33\x00')
         wbm_inst.init_write(4, b'\x22\x00')
-        wbm_inst.init_write(4, b'\x11\x01')
+        wbm_inst.init_write(4, b'\x11\x02')
         wbm_inst.init_write(3, b'\x10')
 
         yield wbm_inst.wait()
@@ -327,16 +327,16 @@ def check():
         yield clk.posedge
 
         data = wbm_inst.get_read_data()
-        assert data[1] == b'\x44\x00'
+        assert data[1] == b'\x44\x01'
 
         data = wbm_inst.get_read_data()
-        assert data[1] == b'\x33\x00'
+        assert data[1] == b'\x33\x01'
 
         data = wbm_inst.get_read_data()
-        assert data[1] == b'\x22\x00'
+        assert data[1] == b'\x22\x01'
 
         data = wbm_inst.get_read_data()
-        assert data[1] == b'\x11\x01'
+        assert data[1] == b'\x11\x03'
 
         yield delay(100)