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README.md

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Template module for peripheral initialization via I2C. For use when one or
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more peripheral devices (i.e. PLL chips, jitter attenuators, clock muxes,
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etc.) need to be initialized on power-up without the use of a general-purpose
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processor.
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processor.
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### i2c_master module
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I2C master module with AXI stream interfaces to control logic.
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I2C master module with AXI stream interfaces to control logic.
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### i2c_master_axil module
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I2C master module with 32-bit AXI lite slave interface.
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### i2c_master_wbs_8 module
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I2C master module with 8-bit Wishbone slave interface.
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### i2c_master_wbs_16 module
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I2C master module with 16-bit Wishbone slave interface.
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### i2c_slave module
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I2C slave module with AXI stream interfaces to control logic.
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### i2c_slave_axil_master module
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I2C slave module with parametrizable AXI lite master interface.
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### i2c_slave_wbm module
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I2C slave module with parametrizable Wishbone master interface.
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### Source Files
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axis_fifo.v : AXI stream FIFO
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i2c_init.v : Template I2C bus init state machine module
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i2c_master.v : I2C master module
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i2c_master_axil.v : I2C master module (32-bit AXI lite slave)
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i2c_master_wbs_8.v : I2C master module (8-bit Wishbone slave)
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i2c_master_wbs_16.v : I2C master module (16-bit Wishbone slave)
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i2c_slave.v : I2C slave module
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i2c_slave_axil_master.v : I2C slave module (parametrizable AXI lite master)
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i2c_slave_wbm.v : I2C slave module (parametrizable Wishbone master)
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## Testing
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### Testbench Files
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tb/axil.py : MyHDL AXI4 lite master and memory BFM
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tb/axis_ep.py : MyHDL AXI Stream endpoints
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tb/i2c.py : MyHDL I2C master and slave models
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tb/wb.py : MyHDL Wishbone master model and RAM model

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