@@ -16,22 +16,48 @@ cosimulation endpoints.
1616Template module for peripheral initialization via I2C. For use when one or
1717more peripheral devices (i.e. PLL chips, jitter attenuators, clock muxes,
1818etc.) need to be initialized on power-up without the use of a general-purpose
19- processor.
19+ processor.
2020
2121### i2c_master module
2222
23- I2C master module with AXI stream interfaces to control logic.
23+ I2C master module with AXI stream interfaces to control logic.
24+
25+ ### i2c_master_axil module
26+
27+ I2C master module with 32-bit AXI lite slave interface.
2428
2529### i2c_master_wbs_8 module
2630
2731I2C master module with 8-bit Wishbone slave interface.
2832
33+ ### i2c_master_wbs_16 module
34+
35+ I2C master module with 16-bit Wishbone slave interface.
36+
37+ ### i2c_slave module
38+
39+ I2C slave module with AXI stream interfaces to control logic.
40+
41+ ### i2c_slave_axil_master module
42+
43+ I2C slave module with parametrizable AXI lite master interface.
44+
45+ ### i2c_slave_wbm module
46+
47+ I2C slave module with parametrizable Wishbone master interface.
48+
49+
2950### Source Files
3051
3152 axis_fifo.v : AXI stream FIFO
3253 i2c_init.v : Template I2C bus init state machine module
3354 i2c_master.v : I2C master module
55+ i2c_master_axil.v : I2C master module (32-bit AXI lite slave)
3456 i2c_master_wbs_8.v : I2C master module (8-bit Wishbone slave)
57+ i2c_master_wbs_16.v : I2C master module (16-bit Wishbone slave)
58+ i2c_slave.v : I2C slave module
59+ i2c_slave_axil_master.v : I2C slave module (parametrizable AXI lite master)
60+ i2c_slave_wbm.v : I2C slave module (parametrizable Wishbone master)
3561
3662## Testing
3763
@@ -42,6 +68,7 @@ individual test scripts can be run with python directly.
4268
4369### Testbench Files
4470
71+ tb/axil.py : MyHDL AXI4 lite master and memory BFM
4572 tb/axis_ep.py : MyHDL AXI Stream endpoints
4673 tb/i2c.py : MyHDL I2C master and slave models
4774 tb/wb.py : MyHDL Wishbone master model and RAM model
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