Add AXI stream FIFO

Author: alexforencich

rtl/axis_fifo.v

@@ -0,0 +1,184 @@
+/*
+
+Copyright (c) 2013-2016 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`timescale 1ns / 1ps
+
+/*
+ * AXI4-Stream FIFO
+ */
+module axis_fifo #
+(
+    parameter ADDR_WIDTH = 12,
+    parameter DATA_WIDTH = 8
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+    
+    /*
+     * AXI input
+     */
+    input  wire [DATA_WIDTH-1:0]  input_axis_tdata,
+    input  wire                   input_axis_tvalid,
+    output wire                   input_axis_tready,
+    input  wire                   input_axis_tlast,
+    input  wire                   input_axis_tuser,
+    
+    /*
+     * AXI output
+     */
+    output wire [DATA_WIDTH-1:0]  output_axis_tdata,
+    output wire                   output_axis_tvalid,
+    input  wire                   output_axis_tready,
+    output wire                   output_axis_tlast,
+    output wire                   output_axis_tuser
+);
+
+reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
+reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
+reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
+reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
+
+reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
+reg [DATA_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
+reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
+wire [DATA_WIDTH+2-1:0] mem_write_data;
+
+reg [DATA_WIDTH+2-1:0] output_data_reg = {DATA_WIDTH+2{1'b0}};
+
+reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
+
+// full when first MSB different but rest same
+wire full = ((wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
+             (wr_ptr_reg[ADDR_WIDTH-1:0] == rd_ptr_reg[ADDR_WIDTH-1:0]));
+// empty when pointers match exactly
+wire empty = wr_ptr_reg == rd_ptr_reg;
+
+// control signals
+reg write;
+reg read;
+reg store_output;
+
+assign input_axis_tready = ~full;
+
+assign output_axis_tvalid = output_axis_tvalid_reg;
+
+assign mem_write_data = {input_axis_tlast, input_axis_tuser, input_axis_tdata};
+assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = output_data_reg;
+
+// Write logic
+always @* begin
+    write = 1'b0;
+
+    wr_ptr_next = wr_ptr_reg;
+
+    if (input_axis_tvalid) begin
+        // input data valid
+        if (~full) begin
+            // not full, perform write
+            write = 1'b1;
+            wr_ptr_next = wr_ptr_reg + 1;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
+    end else begin
+        wr_ptr_reg <= wr_ptr_next;
+    end
+
+    wr_addr_reg <= wr_ptr_next;
+
+    if (write) begin
+        mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
+    end
+end
+
+// Read logic
+always @* begin
+    read = 1'b0;
+
+    rd_ptr_next = rd_ptr_reg;
+
+    mem_read_data_valid_next = mem_read_data_valid_reg;
+
+    if (store_output | ~mem_read_data_valid_reg) begin
+        // output data not valid OR currently being transferred
+        if (~empty) begin
+            // not empty, perform read
+            read = 1'b1;
+            mem_read_data_valid_next = 1'b1;
+            rd_ptr_next = rd_ptr_reg + 1;
+        end else begin
+            // empty, invalidate
+            mem_read_data_valid_next = 1'b0;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
+        mem_read_data_valid_reg <= 1'b0;
+    end else begin
+        rd_ptr_reg <= rd_ptr_next;
+        mem_read_data_valid_reg <= mem_read_data_valid_next;
+    end
+
+    rd_addr_reg <= rd_ptr_next;
+
+    if (read) begin
+        mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
+    end
+end
+
+// Output register
+always @* begin
+    store_output = 1'b0;
+
+    output_axis_tvalid_next = output_axis_tvalid_reg;
+
+    if (output_axis_tready | ~output_axis_tvalid) begin
+        store_output = 1'b1;
+        output_axis_tvalid_next = mem_read_data_valid_reg;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        output_axis_tvalid_reg <= 1'b0;
+    end else begin
+        output_axis_tvalid_reg <= output_axis_tvalid_next;
+    end
+
+    if (store_output) begin
+        output_data_reg <= mem_read_data_reg;
+    end
+end
+
+endmodule