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alexforencichalexforencich
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Fix FIFO-related parameters to use DEPTH instead of ADDR_WIDTH
Signed-off-by: Alex Forencich <[email protected]>
1 parent 4a41d47 commit e7a2681

9 files changed

+45
-45
lines changed

‎rtl/i2c_master_axil.v‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -34,11 +34,11 @@ module i2c_master_axil #
3434
parameter DEFAULT_PRESCALE = 1,
3535
parameter FIXED_PRESCALE = 0,
3636
parameter CMD_FIFO = 1,
37-
parameter CMD_FIFO_ADDR_WIDTH = 5,
37+
parameter CMD_FIFO_DEPTH = 32,
3838
parameter WRITE_FIFO = 1,
39-
parameter WRITE_FIFO_ADDR_WIDTH = 5,
39+
parameter WRITE_FIFO_DEPTH = 32,
4040
parameter READ_FIFO = 1,
41-
parameter READ_FIFO_ADDR_WIDTH = 5
41+
parameter READ_FIFO_DEPTH = 32
4242
)
4343
(
4444
input wire clk,
@@ -372,7 +372,7 @@ generate
372372

373373
if (CMD_FIFO) begin
374374
axis_fifo #(
375-
.ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
375+
.DEPTH(CMD_FIFO_DEPTH),
376376
.DATA_WIDTH(7+5),
377377
.KEEP_ENABLE(0),
378378
.LAST_ENABLE(0),
@@ -416,7 +416,7 @@ end
416416

417417
if (WRITE_FIFO) begin
418418
axis_fifo #(
419-
.ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
419+
.DEPTH(WRITE_FIFO_DEPTH),
420420
.DATA_WIDTH(8),
421421
.KEEP_ENABLE(0),
422422
.LAST_ENABLE(1),
@@ -456,7 +456,7 @@ end
456456

457457
if (READ_FIFO) begin
458458
axis_fifo #(
459-
.ADDR_WIDTH(READ_FIFO_ADDR_WIDTH),
459+
.DEPTH(READ_FIFO_DEPTH),
460460
.DATA_WIDTH(8),
461461
.KEEP_ENABLE(0),
462462
.LAST_ENABLE(1),

‎rtl/i2c_master_wbs_16.v‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -34,11 +34,11 @@ module i2c_master_wbs_16 #
3434
parameter DEFAULT_PRESCALE = 1,
3535
parameter FIXED_PRESCALE = 0,
3636
parameter CMD_FIFO = 1,
37-
parameter CMD_FIFO_ADDR_WIDTH = 5,
37+
parameter CMD_FIFO_DEPTH = 32,
3838
parameter WRITE_FIFO = 1,
39-
parameter WRITE_FIFO_ADDR_WIDTH = 5,
39+
parameter WRITE_FIFO_DEPTH = 32,
4040
parameter READ_FIFO = 1,
41-
parameter READ_FIFO_ADDR_WIDTH = 5
41+
parameter READ_FIFO_DEPTH = 32
4242
)
4343
(
4444
input wire clk,
@@ -319,7 +319,7 @@ generate
319319

320320
if (CMD_FIFO) begin
321321
axis_fifo #(
322-
.ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
322+
.DEPTH(CMD_FIFO_DEPTH),
323323
.DATA_WIDTH(7+5),
324324
.KEEP_ENABLE(0),
325325
.LAST_ENABLE(0),
@@ -363,7 +363,7 @@ end
363363

364364
if (WRITE_FIFO) begin
365365
axis_fifo #(
366-
.ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
366+
.DEPTH(WRITE_FIFO_DEPTH),
367367
.DATA_WIDTH(8),
368368
.KEEP_ENABLE(0),
369369
.LAST_ENABLE(1),
@@ -403,7 +403,7 @@ end
403403

404404
if (READ_FIFO) begin
405405
axis_fifo #(
406-
.ADDR_WIDTH(READ_FIFO_ADDR_WIDTH),
406+
.DEPTH(READ_FIFO_DEPTH),
407407
.DATA_WIDTH(8),
408408
.KEEP_ENABLE(0),
409409
.LAST_ENABLE(1),

‎rtl/i2c_master_wbs_8.v‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -34,11 +34,11 @@ module i2c_master_wbs_8 #
3434
parameter DEFAULT_PRESCALE = 1,
3535
parameter FIXED_PRESCALE = 0,
3636
parameter CMD_FIFO = 1,
37-
parameter CMD_FIFO_ADDR_WIDTH = 5,
37+
parameter CMD_FIFO_DEPTH = 32,
3838
parameter WRITE_FIFO = 1,
39-
parameter WRITE_FIFO_ADDR_WIDTH = 5,
39+
parameter WRITE_FIFO_DEPTH = 32,
4040
parameter READ_FIFO = 1,
41-
parameter READ_FIFO_ADDR_WIDTH = 5
41+
parameter READ_FIFO_DEPTH = 32
4242
)
4343
(
4444
input wire clk,
@@ -307,7 +307,7 @@ generate
307307

308308
if (CMD_FIFO) begin
309309
axis_fifo #(
310-
.ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
310+
.DEPTH(CMD_FIFO_DEPTH),
311311
.DATA_WIDTH(7+5),
312312
.KEEP_ENABLE(0),
313313
.LAST_ENABLE(0),
@@ -351,7 +351,7 @@ end
351351

352352
if (WRITE_FIFO) begin
353353
axis_fifo #(
354-
.ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
354+
.DEPTH(WRITE_FIFO_DEPTH),
355355
.DATA_WIDTH(8),
356356
.KEEP_ENABLE(0),
357357
.LAST_ENABLE(1),
@@ -391,7 +391,7 @@ end
391391

392392
if (READ_FIFO) begin
393393
axis_fifo #(
394-
.ADDR_WIDTH(READ_FIFO_ADDR_WIDTH),
394+
.DEPTH(READ_FIFO_DEPTH),
395395
.DATA_WIDTH(8),
396396
.KEEP_ENABLE(0),
397397
.LAST_ENABLE(1),

‎tb/test_i2c_master_axil.py‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,11 +49,11 @@ def bench():
4949
DEFAULT_PRESCALE = 1
5050
FIXED_PRESCALE = 0
5151
CMD_FIFO = 1
52-
CMD_FIFO_ADDR_WIDTH = 5
52+
CMD_FIFO_DEPTH = 32
5353
WRITE_FIFO = 1
54-
WRITE_FIFO_ADDR_WIDTH = 5
54+
WRITE_FIFO_DEPTH = 32
5555
READ_FIFO = 1
56-
READ_FIFO_ADDR_WIDTH = 5
56+
READ_FIFO_DEPTH = 32
5757

5858
# Inputs
5959
clk = Signal(bool(0))

‎tb/test_i2c_master_axil.v‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -35,11 +35,11 @@ module test_i2c_master_axil;
3535
parameter DEFAULT_PRESCALE = 1;
3636
parameter FIXED_PRESCALE = 0;
3737
parameter CMD_FIFO = 1;
38-
parameter CMD_FIFO_ADDR_WIDTH = 5;
38+
parameter CMD_FIFO_DEPTH = 32;
3939
parameter WRITE_FIFO = 1;
40-
parameter WRITE_FIFO_ADDR_WIDTH = 5;
40+
parameter WRITE_FIFO_DEPTH = 32;
4141
parameter READ_FIFO = 1;
42-
parameter READ_FIFO_ADDR_WIDTH = 5;
42+
parameter READ_FIFO_DEPTH = 32;
4343

4444
// Inputs
4545
reg clk = 0;
@@ -118,11 +118,11 @@ i2c_master_axil #(
118118
.DEFAULT_PRESCALE(DEFAULT_PRESCALE),
119119
.FIXED_PRESCALE(FIXED_PRESCALE),
120120
.CMD_FIFO(CMD_FIFO),
121-
.CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
121+
.CMD_FIFO_DEPTH(CMD_FIFO_DEPTH),
122122
.WRITE_FIFO(WRITE_FIFO),
123-
.WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
123+
.WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
124124
.READ_FIFO(READ_FIFO),
125-
.READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
125+
.READ_FIFO_DEPTH(READ_FIFO_DEPTH)
126126
)
127127
UUT (
128128
.clk(clk),

‎tb/test_i2c_master_wbs_16.py‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,11 +49,11 @@ def bench():
4949
DEFAULT_PRESCALE = 1
5050
FIXED_PRESCALE = 0
5151
CMD_FIFO = 1
52-
CMD_FIFO_ADDR_WIDTH = 5
52+
CMD_FIFO_DEPTH = 32
5353
WRITE_FIFO = 1
54-
WRITE_FIFO_ADDR_WIDTH = 5
54+
WRITE_FIFO_DEPTH = 32
5555
READ_FIFO = 1
56-
READ_FIFO_ADDR_WIDTH = 5
56+
READ_FIFO_DEPTH = 32
5757

5858
# Inputs
5959
clk = Signal(bool(0))

‎tb/test_i2c_master_wbs_16.v‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -35,11 +35,11 @@ module test_i2c_master_wbs_16;
3535
parameter DEFAULT_PRESCALE = 1;
3636
parameter FIXED_PRESCALE = 0;
3737
parameter CMD_FIFO = 1;
38-
parameter CMD_FIFO_ADDR_WIDTH = 5;
38+
parameter CMD_FIFO_DEPTH = 32;
3939
parameter WRITE_FIFO = 1;
40-
parameter WRITE_FIFO_ADDR_WIDTH = 5;
40+
parameter WRITE_FIFO_DEPTH = 32;
4141
parameter READ_FIFO = 1;
42-
parameter READ_FIFO_ADDR_WIDTH = 5;
42+
parameter READ_FIFO_DEPTH = 32;
4343

4444
// Inputs
4545
reg clk = 0;
@@ -96,11 +96,11 @@ i2c_master_wbs_16 #(
9696
.DEFAULT_PRESCALE(DEFAULT_PRESCALE),
9797
.FIXED_PRESCALE(FIXED_PRESCALE),
9898
.CMD_FIFO(CMD_FIFO),
99-
.CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
99+
.CMD_FIFO_DEPTH(CMD_FIFO_DEPTH),
100100
.WRITE_FIFO(WRITE_FIFO),
101-
.WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
101+
.WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
102102
.READ_FIFO(READ_FIFO),
103-
.READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
103+
.READ_FIFO_DEPTH(READ_FIFO_DEPTH)
104104
)
105105
UUT (
106106
.clk(clk),

‎tb/test_i2c_master_wbs_8.py‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,11 +49,11 @@ def bench():
4949
DEFAULT_PRESCALE = 1
5050
FIXED_PRESCALE = 0
5151
CMD_FIFO = 1
52-
CMD_FIFO_ADDR_WIDTH = 5
52+
CMD_FIFO_DEPTH = 32
5353
WRITE_FIFO = 1
54-
WRITE_FIFO_ADDR_WIDTH = 5
54+
WRITE_FIFO_DEPTH = 32
5555
READ_FIFO = 1
56-
READ_FIFO_ADDR_WIDTH = 5
56+
READ_FIFO_DEPTH = 32
5757

5858
# Inputs
5959
clk = Signal(bool(0))

‎tb/test_i2c_master_wbs_8.v‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -35,11 +35,11 @@ module test_i2c_master_wbs_8;
3535
parameter DEFAULT_PRESCALE = 1;
3636
parameter FIXED_PRESCALE = 0;
3737
parameter CMD_FIFO = 1;
38-
parameter CMD_FIFO_ADDR_WIDTH = 5;
38+
parameter CMD_FIFO_DEPTH = 32;
3939
parameter WRITE_FIFO = 1;
40-
parameter WRITE_FIFO_ADDR_WIDTH = 5;
40+
parameter WRITE_FIFO_DEPTH = 32;
4141
parameter READ_FIFO = 1;
42-
parameter READ_FIFO_ADDR_WIDTH = 5;
42+
parameter READ_FIFO_DEPTH = 32;
4343

4444
// Inputs
4545
reg clk = 0;
@@ -94,11 +94,11 @@ i2c_master_wbs_8 #(
9494
.DEFAULT_PRESCALE(DEFAULT_PRESCALE),
9595
.FIXED_PRESCALE(FIXED_PRESCALE),
9696
.CMD_FIFO(CMD_FIFO),
97-
.CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
97+
.CMD_FIFO_DEPTH(CMD_FIFO_DEPTH),
9898
.WRITE_FIFO(WRITE_FIFO),
99-
.WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
99+
.WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
100100
.READ_FIFO(READ_FIFO),
101-
.READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
101+
.READ_FIFO_DEPTH(READ_FIFO_DEPTH)
102102
)
103103
UUT (
104104
.clk(clk),

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