I2C block read not working

[abunimeh]

Some I2C devices support reading multiple data bytes from a register which contains more than one byte of data. Current implantation only supports a single byte read. Example device is PAC1931

[alexforencich]

This is supported; simply issue as many read commands as you like and the core will perform back-to-back read operations without releasing the bus or issuing a start or repeated start.

[abunimeh]

The image above shows a block read for that device. Using i2c driver I perform the following multi-byte read:

1. cmd_write + cmd_start
2. cmd_read + cmd_start
3. cmd_read + cmd_stop

The values readback are not correct and the status bits 'bus_act' and 'bus_cont' are still high after (3). I believe after the stop these should be low.

if I do a single byte read e.g.

1. cmd_write + cmd_start
2. cmd_read + cmd_start + cmd_stop

it works fine and status bits 'bus_act' and 'bus_cont' are low after (2)

[alexforencich]

OK, maybe there is a bug of some sort, because that should be the correct set of commands for a block read. There is a test in the testbench for exactly this scenario, write a byte or two then turn the interface around and read several bytes. You actually shouldn't even have to indicate cmd_start in this case at all, a command when at idle implies start, and a change in address or a change between read and write also implies start. But if the bus is still active after an explicit stop, something odd is going on. Can you get an ILA capture (or equivalent) of the I2C master signals to debug this further? And how did you connect the core to the FPGA pins?

[abunimeh]

i2c_master core signals, mainly, sda and scl are connected to Xilinx's IOBUF. I will try to get the ILA in a couple of days. The i2c_master works flawlessly in single write/read and multi_write modes. I only had this issue during block read.

[aloksmp]

What could be the reason i am seeing this SyntaxError:

python test_i2c_slave.py
File "test_i2c_slave.py", line 30, in
import i2c
File "/projects/i2c_alex_forencich/verilog-i2c-master/tb/i2c.py", line 365
yield from send_bit(b & (1 << 7-i))
^
SyntaxError: invalid syntax