drivers: sdhc: Add synopsys dwc sdhc driver

Added initial version of synopsys dwc sdhc driver.
Supports 3.3v and 1.8v operation.
Supports SD/SDIO modes at 1, 4 bit bus, 400khz, 25mhz, 50mhz speed.

Signed-off-by: Deepak Kumar <deepak@alifsemi.com>

Author: Deepak-AlifSemi

drivers/sdhc/CMakeLists.txt

@@ -14,4 +14,5 @@ zephyr_library_sources_ifdef(CONFIG_CDNS_SDHC sdhc_cdns_ll.c sdhc_cdns.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_ESP32 sdhc_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_RENESAS_RA sdhc_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_MAX32 sdhc_max32.c)
+zephyr_library_sources_ifdef(CONFIG_SDHC_DWC sdhc_dwc.c)
 endif()

drivers/sdhc/Kconfig

@@ -19,6 +19,7 @@ source "drivers/sdhc/Kconfig.sdhc_cdns"
 source "drivers/sdhc/Kconfig.esp32"
 source "drivers/sdhc/Kconfig.renesas_ra"
 source "drivers/sdhc/Kconfig.max32"
+source "drivers/sdhc/Kconfig.dwc"
 
 config SDHC_INIT_PRIORITY
 	int "SDHC driver init priority"

drivers/sdhc/Kconfig.dwc

@@ -0,0 +1,50 @@
+# Copyright (c) 2026 Alif Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+config SDHC_DWC
+	bool "Synopsys DesignWare Core SDHC driver"
+	default y
+	depends on DT_HAS_SNPS_DWC_SDHC_ENABLED
+	select SDHC_SUPPORTS_NATIVE_MODE
+	select EVENTS
+	help
+	  Enable Synopsys DesignWare Core SDHC driver.
+
+if SDHC_DWC
+
+config SDHC_BUFFER_ALIGNMENT
+	int "SDHC buffer alignment"
+	default 512
+
+config SDHC_DESCRIPTOR_SECTION
+	string
+	default ".alif.ns"
+	help
+	  Linker section for SDHC driver data including DMA descriptors.
+	  On Alif SoCs this is overridden to a non-secure region by the
+	  SoC Kconfig defconfig.
+
+config SDHC_DWC_SDMA
+	bool "Use SDMA mode"
+	help
+	  Use Single-operation DMA (SDMA) for data transfers. SDMA uses
+	  the SDMA System Address register and requires handling DMA
+	  boundary interrupts for transfers crossing 4 KB pages.
+
+config SDHC_DWC_ADMA
+	bool "Use ADMA2 mode"
+	default y
+	depends on !SDHC_DWC_SDMA
+	help
+	  Use Advanced DMA 2 (ADMA2) for data transfers. ADMA2 uses a
+	  descriptor table that allows scatter-gather transfers without
+	  boundary interrupt handling. This is the recommended DMA mode.
+
+config SDHC_DWC_ADMA_MAX_DESC
+	int "SDHC DWC ADMA Maximum Descriptor count"
+	depends on SDHC_DWC_ADMA
+	default 32
+	help
+	  SDHC DWC ADMA Maximum Descriptor count.
+
+endif # SDHC_DWC