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Tanay-AlifSemiRupeshKumar-AlifSemi
Tanay-AlifSemi
authored and
RupeshKumar-AlifSemi
committed
soc: alif: ensemble/balletto: common: mpu_regions: update mpu regions
- Add a dedicated MPU region as "Device" for the MRAM storage partition - Reduce the Flash MPU region to avoid region overlap - Add an ITCM region and replace CONFIG_SRAM region with DTCM. Signed-off-by: Tanay Rami <tanay@alifsemi.com>
1 parent b11ca85 commit ccf5f43

2 files changed

Lines changed: 47 additions & 15 deletions

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‎soc/alif/balletto/common/mpu_regions.c‎

Lines changed: 22 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -24,24 +24,40 @@
2424
.r_limit = REGION_LIMIT_ADDR(base, size), \
2525
}
2626

27+
#define MRAM_BOOT_PARTITION_ADDR DT_FIXED_PARTITION_ADDR(DT_NODELABEL(boot_partition))
28+
#define MRAM_STORAGE_PARTITION_ADDR DT_FIXED_PARTITION_ADDR(DT_NODELABEL(storage_partition))
29+
#define MRAM_STORAGE_PARTITION_SIZE DT_REG_SIZE(DT_NODELABEL(storage_partition))
30+
31+
#define FLASH_MRAM_BASE_ADDR MRAM_BOOT_PARTITION_ADDR
32+
#define FLASH_MRAM_SIZE (MRAM_STORAGE_PARTITION_ADDR - MRAM_BOOT_PARTITION_ADDR)
33+
2734
static const struct arm_mpu_region mpu_regions[] = {
2835
/* Region 0 */
29-
MPU_REGION_ENTRY("FLASH_0", CONFIG_FLASH_BASE_ADDRESS,
30-
REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)),
36+
MPU_REGION_ENTRY("FLASH_MRAM", FLASH_MRAM_BASE_ADDR,
37+
REGION_FLASH_ATTR(FLASH_MRAM_BASE_ADDR, FLASH_MRAM_SIZE)),
3138
/* Region 1 */
32-
MPU_REGION_ENTRY("SRAM_0", CONFIG_SRAM_BASE_ADDRESS,
33-
REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)),
39+
MPU_REGION_ENTRY("ITCM", DT_REG_ADDR(DT_NODELABEL(itcm)),
40+
REGION_FLASH_ATTR(DT_REG_ADDR(DT_NODELABEL(itcm)),
41+
DT_REG_SIZE(DT_NODELABEL(itcm)))),
3442
/* Region 2 */
43+
MPU_REGION_ENTRY("DTCM", DT_REG_ADDR(DT_NODELABEL(dtcm)),
44+
REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(dtcm)),
45+
DT_REG_SIZE(DT_NODELABEL(dtcm)))),
46+
/* Region 3 */
3547
MPU_REGION_ENTRY("OSPI_CTRL", ALIF_HOST_OSPI_REG,
3648
REGION_DEVICE_ATTR(ALIF_HOST_OSPI_REG, ALIF_HOST_OSPI_SIZE)),
37-
/* Region 3 */
49+
/* Region 4 */
3850
MPU_REGION_ENTRY("PERIPHERALS", ALIF_HOST_PERIPHERAL_BASE,
3951
REGION_DEVICE_ATTR(ALIF_HOST_PERIPHERAL_BASE,
4052
ALIF_HOST_PERIPHERAL_SIZE)),
41-
/* Region 4 */
53+
/* Region 5 */
4254
MPU_REGION_ENTRY("OSPI0_XIP", ALIF_HOST_OSPI0_XIP_BASE,
4355
REGION_OSPI_FLASH_ATTR(ALIF_HOST_OSPI0_XIP_BASE,
4456
ALIF_HOST_OSPI0_XIP_SIZE)),
57+
/* Region 6 */
58+
MPU_REGION_ENTRY("MRAM_STORAGE", MRAM_STORAGE_PARTITION_ADDR,
59+
REGION_DEVICE_ATTR(MRAM_STORAGE_PARTITION_ADDR,
60+
MRAM_STORAGE_PARTITION_SIZE)),
4561
};
4662

4763
const struct arm_mpu_config mpu_config = {

‎soc/alif/ensemble/common/mpu_regions.c‎

Lines changed: 25 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -24,37 +24,53 @@
2424
.r_limit = REGION_LIMIT_ADDR(base, size), \
2525
}
2626

27+
#define MRAM_BOOT_PARTITION_ADDR DT_FIXED_PARTITION_ADDR(DT_NODELABEL(boot_partition))
28+
#define MRAM_STORAGE_PARTITION_ADDR DT_FIXED_PARTITION_ADDR(DT_NODELABEL(storage_partition))
29+
#define MRAM_STORAGE_PARTITION_SIZE DT_REG_SIZE(DT_NODELABEL(storage_partition))
30+
31+
#define FLASH_MRAM_BASE_ADDR MRAM_BOOT_PARTITION_ADDR
32+
#define FLASH_MRAM_SIZE (MRAM_STORAGE_PARTITION_ADDR - MRAM_BOOT_PARTITION_ADDR)
33+
2734
static const struct arm_mpu_region mpu_regions[] = {
2835
/* Region 0 */
29-
MPU_REGION_ENTRY("FLASH_0", CONFIG_FLASH_BASE_ADDRESS,
30-
REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)),
36+
MPU_REGION_ENTRY("FLASH_MRAM", FLASH_MRAM_BASE_ADDR,
37+
REGION_FLASH_ATTR(FLASH_MRAM_BASE_ADDR, FLASH_MRAM_SIZE)),
3138
/* Region 1 */
32-
MPU_REGION_ENTRY("SRAM_0", CONFIG_SRAM_BASE_ADDRESS,
33-
REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)),
39+
MPU_REGION_ENTRY("ITCM", DT_REG_ADDR(DT_NODELABEL(itcm)),
40+
REGION_FLASH_ATTR(DT_REG_ADDR(DT_NODELABEL(itcm)),
41+
DT_REG_SIZE(DT_NODELABEL(itcm)))),
3442
/* Region 2 */
43+
MPU_REGION_ENTRY("DTCM", DT_REG_ADDR(DT_NODELABEL(dtcm)),
44+
REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(dtcm)),
45+
DT_REG_SIZE(DT_NODELABEL(dtcm)))),
46+
/* Region 3 */
3547
MPU_REGION_ENTRY("SRAM0", DT_REG_ADDR(DT_NODELABEL(sram0)),
3648
REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(sram0)), DT_REG_SIZE(DT_NODELABEL(sram0)))),
37-
/* Region 3 */
49+
/* Region 4 */
3850
MPU_REGION_ENTRY("SRAM1", DT_REG_ADDR(DT_NODELABEL(sram1)),
3951
REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(sram1)), DT_REG_SIZE(DT_NODELABEL(sram1)))),
40-
/* Region 4 */
52+
/* Region 5 */
4153
MPU_REGION_ENTRY("PERIPHERALS", DT_REG_ADDR(DT_NODELABEL(host_peripheral)),
4254
REGION_DEVICE_ATTR(DT_REG_ADDR(DT_NODELABEL(host_peripheral)), DT_REG_SIZE(DT_NODELABEL(host_peripheral)))),
43-
/* Region 5 */
55+
/* Region 6 */
4456
MPU_REGION_ENTRY("OSPI_CTRL", ALIF_ENSEMBLE_OSPI_REG,
4557
REGION_DEVICE_ATTR(ALIF_ENSEMBLE_OSPI_REG, ALIF_ENSEMBLE_OSPI_SIZE)),
4658

4759
#ifdef CONFIG_SOC_SERIES_E1C
48-
/* Region 6 */
60+
/* Region 7 */
4961
MPU_REGION_ENTRY("OSPI0_XIP", ALIF_ENSEMBLE_OSPI0_XIP_BASE,
5062
REGION_OSPI_FLASH_ATTR(ALIF_ENSEMBLE_OSPI0_XIP_BASE,
5163
ALIF_ENSEMBLE_OSPI0_XIP_SIZE)),
5264
#else
53-
/* Region 6 */
65+
/* Region 7 */
5466
MPU_REGION_ENTRY("OSPI1_XIP", ALIF_ENSEMBLE_OSPI1_XIP_BASE,
5567
REGION_OSPI_FLASH_ATTR(ALIF_ENSEMBLE_OSPI1_XIP_BASE,
5668
ALIF_ENSEMBLE_OSPI1_XIP_SIZE)),
5769
#endif
70+
/* Region 8 */
71+
MPU_REGION_ENTRY("MRAM_STORAGE", MRAM_STORAGE_PARTITION_ADDR,
72+
REGION_DEVICE_ATTR(MRAM_STORAGE_PARTITION_ADDR,
73+
MRAM_STORAGE_PARTITION_SIZE)),
5874
};
5975

6076
const struct arm_mpu_config mpu_config = {

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