Remove altera-innersource from Yocto meta-custom README files (#5)

1. Removed altera-innersource link and updated with public altera-fpga link
2. Removed parallel thread limits in kas.yml

Author: gohshunjing

a5ed065es-premium-devkit-oobe/baseline/software/yocto_linux/kas.yml

@@ -48,8 +48,6 @@ local_conf_header:
     VIRTUAL-RUNTIME_init_manager = "systemd"
     KERNEL_MODULE_PROBECONF = "cfg80211"
     module_conf_cfg80211 = "blacklist cfg80211"
-    PARALLEL_MAKE = "-j 8"
-    BB_NUMBER_THREADS = "8"
   boot-source: |
     SSBL_BOOT_SOURCE ?= "mmc0"
     KERNEL_BOOTARGS_SD_MMC ?= ""

a5ed065es-premium-devkit-oobe/baseline/software/yocto_linux/meta-custom/recipes-bsp/device-tree/README.md

@@ -3,7 +3,7 @@
 ## FPGA design specific custom Linux device tree
 ### a. Full custom device tree (When FPGA_ENABLE_CORE_PGM=1, CUSTOM_LINUX_DEVICE_TREE=1)
 **CUSTOM LINUX DEVICE TREE**
-- Refer to the official base device tree source https://github.com/altera-innersource/applications.fpga.soc.linux-socfpga-dev/blob/socfpga-6.12.19-lts/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts and create custom device tree with same name or different name.
+- Refer to the official base device tree source https://github.com/altera-fpga/linux-socfpga.git - arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts and create custom device tree with same name or different name.
 
 - Ensure your custom .dts includes `socfpga_agilex5.dtsi` similar to how it's done in the reference .dts.
 

a5ed065es-premium-devkit-oobe/baseline/software/yocto_linux/meta-custom/recipes-bsp/u-boot/README.md

@@ -7,7 +7,7 @@
 - No additional Yocto configuration is required, by default `CUSTOM_UBOOT_DEVICE_TREE` variable is disabled in `kas.yml`.
 
 ### Custom device tree
-- Create the custom device tree by referring to https://github.com/altera-innersource/applications.fpga.soc.uboot-socfpga/blob/socfpga_v2025.04/arch/arm/dts/socfpga_agilex5_socdk.dts.
+- Create the custom device tree by referring to https://github.com/altera-fpga/u-boot-socfpga.git - arch/arm/dts/socfpga_agilex5_socdk.dts.
 - Ensure required .dtsi file (e.g., socfpga_agilex5.dtsi) included in your custom .dts, similar to how it's done in the reference .dts.
 - Copy the complete custom .dts file in `meta-custom/recipes-bsp/u-boot/files/dts/`
 - Enable the `CUSTOM_UBOOT_DEVICE_TREE` variable in `kas.yml` to instruct the Yocto build system to build your custom .dts instead of the default in-tree one.
@@ -57,8 +57,8 @@ Follow below steps to create the patch, apply & build the U-Boot.
 
 ### Clone U-Boot source repo
 ```
-$ git clone  https://github.com/altera-innersource/applications.fpga.soc.uboot-socfpga.git
-$ cd applications.fpga.soc.uboot-socfpga
+$ git clone https://github.com/altera-fpga/u-boot-socfpga.git
+$ cd u-boot-socfpga
 $ git checkout <branch>
 ```
 Do your source code changes.

a5ed065es-premium-devkit-oobe/baseline/software/yocto_linux/meta-custom/recipes-kernel/linux/README.md

@@ -40,8 +40,8 @@ Follow below steps to create the patch & build Linux Kernel.
 
 ### Clone Linux Kernel repo
 ```
-$ git clone https://github.com/altera-innersource/applications.fpga.soc.linux-socfpga-dev.git
-$ cd applications.fpga.soc.linux-socfpga-dev
+$ git clone https://github.com/altera-fpga/linux-socfpga.git
+$ cd linux-socfpga
 $ git checkout <branch>
 ```