Release Notes for **GHRD for Agilex 5 FPGA E-Series 25.1.1** (#3)

## Release Information:
Quartus Version: 25.1.1 Build 125 07/31/2025 SC Pro Edition
Tag: QPDS25.1.1_REL_GSRD_PR
Build: socfpga_ghrd_a5e_base/25.1.1/1354

## New Features and Enhancements
- EMIF ECC is enabled for all designs.
- Premium Development Kit with Out of Box Experience (OOBE) daughter card designs support USB3.1.

## Issues Resolved
- Corrected usb31_phy_refclk_p_clk and usb31_phy_refclk_p_clk(n) pin for Agilex 5 FPGA E-Series 065B Modular Development Kit.
- Fixed wrong value in agilex_hps.ip file, that creates wrong handoff to powerdown the SDMMC controller.

## Latest Known Issues
- Remove support for HPS NAND board due to ECC issue.

Author: gohshunjing

.clang-format

@@ -0,0 +1,126 @@
+# Linux Coding Style, but with 4-space indent
+# Source: https://github.com/torvalds/linux/blob/master/.clang-format
+# Guide: https://github.com/torvalds/linux/blob/master/Documentation/process/coding-style.rst
+#
+# clang-format configuration file. Intended for clang-format >= 11.
+#
+# For more information, see:
+#
+#   Documentation/process/clang-format.rst
+#   https://clang.llvm.org/docs/ClangFormat.html
+#   https://clang.llvm.org/docs/ClangFormatStyleOptions.html
+#
+---
+AccessModifierOffset: -4
+AlignAfterOpenBracket: Align
+AlignConsecutiveAssignments: false
+AlignConsecutiveDeclarations: false
+AlignEscapedNewlines: Left
+AlignOperands: true
+AlignTrailingComments: false
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortBlocksOnASingleLine: false
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: None
+AllowShortIfStatementsOnASingleLine: false
+AllowShortLoopsOnASingleLine: false
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AlwaysBreakTemplateDeclarations: false
+BinPackArguments: true
+BinPackParameters: true
+BraceWrapping:
+  AfterClass: false
+  AfterControlStatement: false
+  AfterEnum: false
+  AfterFunction: true
+  AfterNamespace: true
+  AfterObjCDeclaration: false
+  AfterStruct: false
+  AfterUnion: false
+  AfterExternBlock: false
+  BeforeCatch: false
+  BeforeElse: false
+  IndentBraces: false
+  SplitEmptyFunction: true
+  SplitEmptyRecord: true
+  SplitEmptyNamespace: true
+BreakBeforeBinaryOperators: None
+BreakBeforeBraces: Custom
+BreakBeforeInheritanceComma: false
+BreakBeforeTernaryOperators: false
+BreakConstructorInitializersBeforeComma: false
+BreakConstructorInitializers: BeforeComma
+BreakAfterJavaFieldAnnotations: false
+BreakStringLiterals: false
+ColumnLimit: 120
+CommentPragmas: '^ IWYU pragma:'
+CompactNamespaces: false
+ConstructorInitializerAllOnOneLineOrOnePerLine: false
+ConstructorInitializerIndentWidth: 4
+ContinuationIndentWidth: 4
+Cpp11BracedListStyle: false
+DerivePointerAlignment: false
+DisableFormat: false
+ExperimentalAutoDetectBinPacking: false
+FixNamespaceComments: false
+
+# Taken from:
+#   git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ tools/ \
+#   | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$,  - '\1'," \
+#   | LC_ALL=C sort -u
+# ForEachMacros:
+
+IncludeBlocks: Preserve
+IncludeCategories:
+  - Regex: '.*'
+    Priority: 1
+IncludeIsMainRegex: '(Test)?$'
+IndentCaseLabels: false
+IndentGotoLabels: false
+IndentPPDirectives: None
+IndentWidth: 4
+IndentWrappedFunctionNames: false
+JavaScriptQuotes: Leave
+JavaScriptWrapImports: true
+KeepEmptyLinesAtTheStartOfBlocks: false
+MacroBlockBegin: ''
+MacroBlockEnd: ''
+MaxEmptyLinesToKeep: 1
+NamespaceIndentation: None
+ObjCBinPackProtocolList: Auto
+ObjCBlockIndentWidth: 4
+ObjCSpaceAfterProperty: true
+ObjCSpaceBeforeProtocolList: true
+
+# Taken from git's rules
+PenaltyBreakAssignment: 10
+PenaltyBreakBeforeFirstCallParameter: 30
+PenaltyBreakComment: 10
+PenaltyBreakFirstLessLess: 0
+PenaltyBreakString: 10
+PenaltyExcessCharacter: 100
+PenaltyReturnTypeOnItsOwnLine: 60
+
+PointerAlignment: Right
+ReflowComments: false
+SortIncludes: false
+SortUsingDeclarations: false
+SpaceAfterCStyleCast: false
+SpaceAfterTemplateKeyword: true
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeParens: ControlStatementsExceptForEachMacros
+SpaceBeforeRangeBasedForLoopColon: true
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 1
+SpacesInAngles: false
+SpacesInContainerLiterals: false
+SpacesInCStyleCastParentheses: false
+SpacesInParentheses: false
+SpacesInSquareBrackets: false
+Standard: Cpp03
+TabWidth: 4
+UseTab:   Never

Makefile

@@ -128,7 +128,6 @@ endef
 # Create rules for subdirs
 TARGET_SUBDIR := \
 	a5ed065es-premium-devkit-oobe \
-	a5ed065es-premium-devkit-nand \
 	a5ed065es-premium-devkit-emmc \
 	a5ed065es-premium-devkit-debug2 \
 	a5ed065es-modular-devkit-som
@@ -175,6 +174,7 @@ venv-freeze:
 prepare-tools : venv
 
 # Include not_shipped Makefile if present
+# Should be included before Toplevel Targets to get all not_shipped dependency targets.
 -include not_shipped/Makefile.mk
 
 ###############################################################################
@@ -205,7 +205,7 @@ sw-build: $(ALL_SW_BUILD_TARGETS)
 
 # Run all tests
 .PHONY: test
-test : build
+test : $(ALL_TEST_TARGETS)
 
 .PHONY: install-sof
 install-sof: $(ALL_INSTALL_SOF_TARGETS)
@@ -220,11 +220,12 @@ all: $(ALL_TARGET_ALL_NAMES)
 help:
 	$(info GHRD Build)
 	$(info ----------------)
+	$(info    all         : Run and "all" target on each of the target designs)
+	$(info ----------------)
 	$(info    All Targets             : $(ALL_TARGET_ALL_NAMES))
 	$(info    Stem names              : $(ALL_TARGET_STEM_NAMES))
 	$(info    Pre-Prep Targets        : $(ALL_PRE_PREP_TARGETS))
 	$(info    Prep Targets            : $(ALL_PREP_TARGETS))
 	$(info    Build Targets           : $(ALL_BUILD_TARGETS))
 	$(info    Test Targets            : $(ALL_TEST_TARGETS))
 	$(info    Package Targets 	      : $(ALL_PACKAGE_DESIGN_TARGETS))
-

README.md

@@ -1,4 +1,4 @@
-# Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series
+# Agilex 5 E-Series Golden Hardware Reference Design (GHRD)
 
 This repository contains Golden Hardware Reference Design (GHRD) for Agilex 5 E-Series System On Chip (SoC) FPGA.
 The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.
@@ -16,7 +16,7 @@ This is applicable to all designs.
   - HPS Peripheral and I/O. eg, NAND, SD/MMC, EMAC, USB, SPI, I2C, UART, and GPIO. (depends on the daughter card).
   - HPS Clock and Reset
   - HPS FPGA Bridge and Interrupt
-- HPS EMIF configuration
+- HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)
 - System integration with FPGA IPs
   - Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs.
   - Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG
@@ -32,27 +32,27 @@ This is only applicable if the feature is enabled.
 3. modify and compile the [designs](#designs) with Quartus Prime.
 
 ## Dependency
-* Altera Quartus Prime 25.1
+* Altera Quartus Prime 25.1.1
 * Supported Board
   - Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1
   ![Agilex 5 E-Series Premium Development Kit](images/agilex5-premium-devkit-es.png)
   - Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1
   ![Agilex 5 E-Series Modular Development Kit](images/agilex5-modular-devkit-es.png)
 
 ## Tested Platform for the GHRD Build Flow
-* SUSE Linux Enterprise Server 12 SP5
+* SUSE Linux Enterprise Server 15 SP4
 
 ## Setup
 
 Several tools are required to be in the path.
 
-* Altera Quartus Prime 25.1
+* Altera Quartus Prime 25.1.1
 * Python 3.11.5 (only required when using command line to build)
 
 ### Example Setup for Altera Quartus Prime tools
 This is recommended, when using command line to build.
 ```bash
-export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.1/quartus
+export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.1.1/quartus
 ```
 Note: Adapt the path above to where Quartus Prime is installed.
 
@@ -62,6 +62,10 @@ export PATH="$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/../qsys/bin:$QUARTUS_ROOTDIR/
 
 ## Quick start
 
+### Notes
+- Command line and Quartus GUI should not be used intertwined.
+- Mixing both might not generate some fileset correctly and fail the build.
+
 ### using command line
 Copy and run the desired make command from [designs](#designs) in the root directory.
 After build, the design files (zip, sof and rbf) can be found in install/designs folder.
@@ -102,12 +106,6 @@ make a5ed065es-premium-devkit-debug2-legacy-baseline-legacy_baseline-all
 make a5ed065es-premium-devkit-emmc-legacy-baseline-legacy_baseline-all
 ```
 
-* [a5ed065es-premium-devkit-nand/legacy-baseline](a5ed065es-premium-devkit-nand/legacy-baseline/README.md) :
-  Legacy baseline GHRD for the A5ED065 ES Premium Devkit with HPS NAND Board.
-```bash
-make a5ed065es-premium-devkit-nand-legacy-baseline-legacy_baseline-all
-```
-
 ### Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1
 
 * [a5ed065es-modular-devkit-som/legacy-baseline](a5ed065es-modular-devkit-som/legacy-baseline/README.md) :

a5ed065es-modular-devkit-som/Makefile

@@ -117,5 +117,3 @@ help:
 	$(info    Prep Targets            : $(ALL_PREP_TARGETS))
 	$(info    Build Targets           : $(ALL_BUILD_TARGETS))
 	$(info    Test Targets           : $(ALL_TEST_TARGETS))
-
-

a5ed065es-modular-devkit-som/legacy-baseline/Makefile

@@ -41,6 +41,7 @@ endif
 # Set defaults
 INSTALL_ROOT ?= $(THIS_MK_DIR)
 ARCHIVE_NAME ?= $(PROJECT_NAME)
+
 ##############################################################################
 # Set default goal before any targets. The default goal here is "test"
 ##############################################################################
@@ -76,8 +77,12 @@ ALL_INSTALL_SOF_TARGETS += $(addsuffix -install-sof,$(strip $(1)))
 
 $(strip $(1))-prep : output_files/prep-$(strip $(1)).done
 
+$(strip $(1))-qsys-ip-file-upgrade: pre-prep
+	$(MAKE) --no-print-directory ip-upgrade-helper
+	quartus_sh --ip_upgrade $(PROJECT_NAME) -revision $(strip $(1)) -mode all
+
 $(strip $(1))-ip-upgrade: pre-prep | output_files
-	flock --verbose output_files/ipupgrade.lock quartus_sh --ip_upgrade $(PROJECT_NAME) -revision $(strip $(1))
+	flock --verbose output_files/ipupgrade.lock $(MAKE) $(strip $(1))-qsys-ip-file-upgrade
 
 $(strip $(1))-generate-design :
 
@@ -109,8 +114,8 @@ output_files/pre-prep.done: | output_files
 
 output_files/prep-%.done: output_files/pre-prep.done | output_files
 	chmod a-w $(PROJECT_NAME).qpf
-	flock --verbose output_files/ipgenerate.lock quartus_ipgenerate top -c $* --simulation=verilog --synthesis=verilog
-	ip-setup-simulation --quartus-project=top --revision=$* --output-directory=sim_setup_$*
+	flock --verbose output_files/ipgenerate.lock quartus_ipgenerate top -c $* --simulation=verilog --synthesis=verilog --simulator=modelsim,vcsmx,riviera,xcelium |& tee output_files/$*.ipgen.rpt
+	ip-setup-simulation --quartus-project=top --revision=$* --output-directory=sim_setup_$* --simulator=modelsim,vcsmx,riviera,xcelium |& tee -a output_files/$*.ipgen.rpt
 	touch $@
 
 .PHONY: pre-prep
@@ -164,6 +169,9 @@ test : $(ALL_TEST_TARGETS)
 print-targets:
 	$(info $(ALL_TARGET_STEM_NAMES))
 
+# run script to upgrade IP and QSYS files
+ip-upgrade-helper:
+	qsys-script --qpf=top --script=qsys_update.tcl --system-file=qsys_top.qsys --search-path="custom_ip/**/*, $$"
 
 ###############################################################################
 #                           SW Build Targets

a5ed065es-modular-devkit-som/legacy-baseline/README.md

@@ -18,7 +18,7 @@ This reference design demonstrates the following system integration between Hard
   - Enable dual core Arm Cortex-A55 processor
   - HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I2C, JTAG, UART, and GPIO)  - HPS Clock and Reset
   - HPS FPGA Bridge and Interrupt
-- HPS EMIF configuration
+- HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)
 - System integration with FPGA IPs
   - Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs
   - Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG
@@ -27,13 +27,14 @@ This reference design demonstrates the following system integration between Hard
 ## Project Details
 
 - **Family**: Agilex 5 E-Series
-- **Quartus Version**: 25.1
+- **Quartus Version**: 25.1.1
 - **Development Kit**: Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1
 - **Device Part**: A5ED065BB32AE6SR0
 - **Category**: Golden Hardware Reference Design (GHRD)
 - **Source**: Quartus Prime Pro
 - **URL**: https://www.github.com/altera-fpga/agilex5e-ed-gsrd
 - **Design Package**: a5ed065es-modular-devkit-som-legacy-baseline.zip
+- **Documentations**: https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/
 
 ## GHRD Overview
 ![GHRD_overview](/images/agilex5_ghrd_overview.svg)