updating README.md files

Author: nithinkumark94

README.md

@@ -4,13 +4,23 @@ This repository contains the Nios V Example designs based on Agilex™ 5 FPGA E-
 
 Development Kit product page- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-premium.html 
 
-Following are the NiosV cores:
+There are three variants of the NiosV core:
 
-    a. Nios V/m core
+    a. Nios V/m core - Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
 
-    b. Nios V/g core
+    b. Nios V/g core - General-Purpose Processor- High Performance (For interrupt driven baremetal and RTOS code)
 
-    c. Nios V/c core
+    c. Nios V/c core - Compact Microcontroller- Smallest (For non-interrupt driven baremetal code)
+
+
+The following table contains the list of Acronyms that the user may come across in the design details
+
+| Acronym | Expansion |
+| --- | ------ |
+| DMA | Direct Memory Access |
+| OCM | On-Chip Memory |
+| PIO | Parallel I/O |
+| RTOS | Real Time Operating System |
 
 
 The following table contains the list of the designs on Agilex 5 FPGA E-Series 065B Premium Development Kit
@@ -25,14 +35,4 @@ The following table contains the list of the designs on Agilex 5 FPGA E-Series 0
 | 6 | Nios V/c | Nios V/c Helloworld OCM Memory test Design | Nios® V/c Processor-based Helloworld and OCM memory test example design<br>[Design details](niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Agilex™_5_FPGA_Helloworld_and_OCM_test_design_on_Nios®V_c_Processor.pdf) |
 
 
-
-The following table contains the list of Acronyms that the user may come across in the design details
-
-| Acronym | Expansion |
-| --- | ------ |
-| DMA | Direct Memory Access |
-| OCM | On-Chip Memory |
-| PIO | Parallel I/O |
-
-
 Refer to the documents in the following link for More information on the Nios V Processor core - [https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/nios-v-support.html ](https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/nios-v-support.html#introtext_1506028531_1693475107)

niosv_m/niosv_m_dma_ocm/sources/README.md

@@ -40,14 +40,14 @@ a. Required directory structure
 b. Using build_sof.py to compile the design
     - Invoke the quartus_py shell in the terminal
     - Run the following command in the terminal from top level project directory:
-        > quartus_py build_sof.py
+        > quartus_py ./scripts/build_sof.py
     - The quartus tool will compile the design and generate the output files
 
 c. Creating the bsp, build software sources and download elf
     - To create software app, run the following commands in the terminal:
     Note:clean the app build project before regenerating elf
 
-	> niosv-bsp -c --quartus-project=hw/<>.qpf --qsys=hw/<>.qsys --type=hal sw/bsp/settings.bsp
+	> niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
 
 	> niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
 
@@ -65,11 +65,11 @@ command: jtagconfig --setparam 1 JtagClock 6M
 d. Hardware Validation
     - Program the generated sof and then download the elf file on the board
 
-	> quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/<top_level_entity_name>.sof'
+	> quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
 
     - Download the elf file on the board 
 
-	> niosv-download -g ready_to_test/<>.elf -c 1
+	> niosv-download -g ready_to_test/app.elf -c 1
 
     - Verify the output on the terminal by using the following command in the terminal:
 
@@ -81,9 +81,9 @@ Simulation is enabled for this design where the memory is initialized with the a
 
    	> Generate Testbench from Platform Designer. Generate -> Generate Testbench System 
 
- 	> cd hw/*_tb/*_tb/sim/mentor/
-	
- 	> cp ./sw/app/build/onchip_mem.hex ./*_tb/*_tb/sim/mentor 
+ 	> cp ./sw/app/build/onchip_mem.hex ./qsys_top_tb/qsys_top_tb/sim/mentor 
+
+    > cd hw/qsys_top_tb/qsys_top_tb/sim/mentor/
 
  	> vsim &
 

niosv_m/niosv_m_helloworld_ocm_mem_test/sources/README.md

@@ -38,14 +38,14 @@ a. Required directory structure
 b. Using build_sof.py to compile the design
     - Invoke the quartus_py shell in the terminal
     - Run the following command in the terminal from top level project directory:
-        > quartus_py build_sof.py
+        > quartus_py ./scripts/build_sof.py
     - The quartus tool will compile the design and generate the output files
 
 c. Creating the bsp, build software sources and download elf
     - To create software app, run the following commands in the terminal:
     Note:clean the app build project before regenerating elf
 
-	> niosv-bsp -c --quartus-project=hw/<>.qpf --qsys=hw/<>.qsys --type=hal sw/bsp/settings.bsp
+	> niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
 
 	> niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
 
@@ -63,11 +63,11 @@ command: jtagconfig --setparam 1 JtagClock 6M
 d. Hardware Validation
     - Program the generated sof and then download the elf file on the board
 
-	> quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/<top_level_entity_name>.sof'
+	> quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
 
     - Download the elf file on the board 
 
-	> niosv-download -g ready_to_test/<>.elf -c 1
+	> niosv-download -g ready_to_test/app.elf -c 1
 
     - Verify the output on the terminal by using the following command in the terminal:
 
@@ -79,9 +79,9 @@ Simulation is enabled for this design where the memory is initialized with the a
 
    	> Generate Testbench from Platform Designer. Generate -> Generate Testbench System 
 
- 	> cd hw/*_tb/*_tb/sim/mentor/
-	
- 	> cp ./sw/app/build/onchip_mem.hex ./*_tb/*_tb/sim/mentor 
+ 	> cp ./sw/app/build/onchip_mem.hex ./qsys_top_tb/qsys_top_tb/sim/mentor 
+
+ 	> cd hw/qsys_top_tb/qsys_top_tb/sim/mentor/
 
  	> vsim &
 

niosv_m/niosv_m_pio/sources/README.md

@@ -38,14 +38,14 @@ a. Required directory structure
 b. Using build_sof.py to compile the design
     - Invoke the quartus_py shell in the terminal
     - Run the following command in the terminal from top level project directory:
-        > quartus_py build_sof.py
+        > quartus_py ./scripts/build_sof.py
     - The quartus tool will compile the design and generate the output files
 
 c. Creating the bsp, build software sources and download elf
     - To create software app, run the following commands in the terminal:
     Note:clean the app build project before regenerating elf
 
-	> niosv-bsp -c --quartus-project=hw/<>.qpf --qsys=hw/<>.qsys --type=hal sw/bsp/settings.bsp
+	> niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
 
 	> niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
 
@@ -63,11 +63,11 @@ command: jtagconfig --setparam 1 JtagClock 6M
 d. Hardware Validation
     - Program the generated sof and then download the elf file on the board
 
-	> quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/<top_level_entity_name>.sof'
+	> quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
 
     - Download the elf file on the board 
 
-	> niosv-download -g ready_to_test/<>.elf -c 1
+	> niosv-download -g ready_to_test/niosv_app.elf -c 1
 
     - Verify the output on the terminal by using the following command in the terminal:
 
@@ -79,9 +79,9 @@ Simulation is enabled for this design where the memory is initialized with the a
 
     > Generate Testbench from Platform Designer. Generate -> Generate Testbench System 
 
- 	> cd hw/*_tb/*_tb/sim/mentor/
-	
- 	> cp ./sw/app/build/onchip_mem.hex ./*_tb/*_tb/sim/mentor 
+ 	> cp ./sw/app/build/onchip_mem.hex ./qsys_top_tb/qsys_top_tb/sim/mentor 
+
+    > cd hw/qsys_top_tb/qsys_top_tb/sim/mentor/
 
  	> vsim &