Readme update

Author: paddy3696

niosv_c/niosv_c_helloworld_ocm_mem_test/sources/README.md

@@ -16,78 +16,72 @@
 
 The directory structure is explained below:
 
-> hw- necessary hardware files (.qpf, .qsf, .sv, .v, .ip) of the design
+- hw - necessary hardware files (.qpf, .qsf, .sv, .v, .ip) of the design
 
-> sw- This folder contains software application files
+- sw - This folder contains software application files
 
-> scripts- This folder consists of scripts to build the design
+- scripts - This folder consists of scripts to build the design
 
 
 ### 2. Using existing files to run the design on hardware
 
-> The sof and elf files required to run the design can be found in "ready_to_test" folder 
+- The sof and elf files required to run the design can be found in "ready_to_test" folder 
 
-> Refer the Hardware validation section (3.d) for the steps   
+- Refer the Hardware validation section (3.d) for the steps   
 
 ### 3. Building the design from scratch
 
 The steps to build the project from scratch are mentioned below:
 
 a. Required directory structure
-    - The top-level project folder should have directory structure as mentioned in Section 1 (Directory Structure).
+- The top-level project folder should have directory structure as mentioned in Section 1 (Directory Structure).
 
 b. Using build_sof.py to compile the design
-    - Invoke the quartus_py shell in the terminal
-    - Run the following command in the terminal from top level project directory:     
-	
-    > quartus_py ./scripts/build_sof.py
+- Invoke the quartus_py shell in the terminal
 
-    - The quartus tool will compile the design and generate the output files
+- Run the following command in the terminal from top level project directory:     
+```    
+ quartus_py ./scripts/build_sof.py
+```
+- The quartus tool will compile the design and generate the output files
 
 c. Creating the bsp, build software sources and download elf
-    - To create software app, run the following commands in the terminal:
-	
-        > clean the app build project before regenerating elf
-	
-        > niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal --script=sw/bsp-update-small-driver.tcl sw/bsp/settings.bsp
-	
-        > niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
-	
-        > niosv-shell
-	
-        > cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
-	
-        > make -C sw/app/build
+- To create software app, run the following commands in the terminal:
 
-        > elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0x9ffff sw/app/build/onchip_mem.hex -r4
-
-Note: Reduce the JTAG clock frequency to 6MHz before programming the application .elf file on the board.
-command: jtagconfig --setparam 1 JtagClock 6M
-
+- Clean the app build project before regenerating elf
+```	
+niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal --script=sw/bsp-update-small-driver.tcl sw/bsp/settings.bsp
+niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
+niosv-shell
+cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
+make -C sw/app/build
+elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0x9ffff sw/app/build/onchip_mem.hex -r4
+```
 
 d. Hardware Validation
-    - Program the generated sof file on the board
-
-        >  quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
-
-    - Verify the output on the terminal by using the following command in the terminal:
-        
-	    > juart-terminal -d 1 -c 1 -i 0
+- Program the generated sof file on the board
+```
+quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
+```
+- Reduce the JTAG clock frequency to 6MHz before programming the application .elf file on the board.
+```
+jtagconfig --setparam 1 JtagClock 6M
+```
+- Verify the output on the terminal by using the following command in the terminal:
+```        
+juart-terminal -d 1 -c 1 -i 0
+```
 
 ### 4. Running simulation
 
 Simulation is enabled for this design where the memory is initialized with the application hex. Use the following commands to run the simulation:
-    
-	> Generate Testbench from Platform Designer. Generate -> Generate Testbench System
-	  
-	> cp ./sw/app/build/onchip_mem.hex ./*_tb/*_tb/sim/mentor
- 
- 	> cd hw/*_tb/*_tb/sim/mentor/
-
-	> vsim &
- 
-	> source msim_setup.tcl
- 
-	> ld_debug
- 
-	> run -all
+
+- Generate Testbench from Platform Designer. Generate -> Generate Testbench System
+```
+cp ./sw/app/build/onchip_mem.hex ./qsys_top_tb/qsys_top_tb/sim/mentor
+cd hw/qsys_top_tb/qsys_top_tb/sim/mentor/
+vsim &
+source msim_setup.tcl
+ld_debug
+run -all
+```

niosv_g/niosv_g_helloworld/sources/README.md

@@ -16,78 +16,76 @@
 
 The directory structure is explained below:
 
-> hw- necessary hardware files (.qpf, .qsf, .sv, .v, .ip) of the design
+- hw - necessary hardware files (.qpf, .qsf, .sv, .v, .ip) of the design
 
-> sw- This folder contains software application files
+- sw - This folder contains software application files
 
-> scripts- This folder consists of scripts to build the design
+- scripts - This folder consists of scripts to build the design
 
 ### 2. Using existing files to run the design on hardware
 
-> The sof and elf files required to run the design can be found in "ready_to_test" folder 
+- The sof and elf files required to run the design can be found in "ready_to_test" folder 
 
-> Refer the Hardware validation section (3.d) for the steps  
+- Refer the Hardware validation section (3.d) for the steps  
 
 ### 3. Building the design from scratch
 
 The steps to build the project from scratch are mentioned below:
 
 a. Required directory structure
-    - The top-level project folder should have directory structure as mentioned in Section 1 (Directory Structure).
+- The top-level project folder should have directory structure as mentioned in Section 1 (Directory Structure).
 
 b. Using build_sof.py to compile the design
-    - Invoke the quartus_py shell in the terminal
-    - Run the following command in the terminal from top level project directory:
-        > quartus_py ./scripts/build_sof.py
-    - The quartus tool will compile the design and generate the output files
+- Invoke the quartus_py shell in the terminal
+
+- Run the following command in the terminal from top level project directory:
+quartus_py ./scripts/build_sof.py
+
+- The quartus tool will compile the design and generate the output files
 
 c. Creating the bsp, build software sources and download elf
-    - To create software app, run the following commands in the terminal:
-	Note: clean the app build project before regenerating elf
- 
-        > niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
-	
-        > niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
-	
-        > niosv-shell
-	
-        > cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
-	
-        > make -C sw/app/build
-	
- 	    > elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0x9ffff sw/app/build/onchip_mem.hex -r4
-       
-
-Note: Reduce the JTAG clock frequency to 6MHz before programming the application .elf file on the board.
-command: jtagconfig --setparam 1 JtagClock 6M
+- To create software app, run the following commands in the terminal:
+
+- Clean the app build project before regenerating elf
+```
+niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
+niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
+niosv-shell
+cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
+make -C sw/app/build
+elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0x9ffff sw/app/build/onchip_mem.hex -r4
+```   
+
 
 d. Hardware Validation
-    - Program the generated sof and then download the elf file on the board
-    
-        > quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
-    
-    - Download the elf file on the board 
-    
-    	> niosv-download -g ready_to_test/app.elf -c 1
-    
-    - Verify the output on the terminal by using the following command in the terminal:
-    
-        > juart-terminal -d 1 -c 1 -i 0 
+- Program the generated sof and then download the elf file on the board
+```
+quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
+```
+- Reduce the JTAG clock frequency to 6MHz before programming the application .elf file on the board.
+```
+jtagconfig --setparam 1 JtagClock 6M
+```
+- Download the elf file on the board 
+```
+niosv-download -g ready_to_test/app.elf -c 1
+```
+- Verify the output on the terminal by using the following command in the terminal:
+```
+juart-terminal -d 1 -c 1 -i 0 
+```
 
 ### 4. Running simulation
 
 Simulation is enabled for this design where the memory is initialized with the application hex. Use the following commands to run the simulation:
-    
-	> Generate Testbench from Platform Designer. Generate -> Generate Testbench System
-	  
-	> cp ./sw/app/build/onchip_mem.hex ./*_tb/*_tb/sim/mentor
-    
- 	> cd hw/*_tb/*_tb/sim/mentor/
- 
-	> vsim &
- 
-	> source msim_setup.tcl
- 
-	> ld_debug
- 
-	> run -all
+
+- Generate Testbench from Platform Designer. Generate -> Generate Testbench System
+
+```	  
+cp ./sw/app/build/onchip_mem.hex ./qsys_top_tb/qsys_top_tb/sim/mentor
+cd hw/qsys_top_tb/qsys_top_tb/sim/mentor/
+vsim &
+source msim_setup.tcl
+ld_debug
+run -all
+```

niosv_g/niosv_g_ocm_mem_test/sources/README.md

@@ -16,80 +16,76 @@
 
 The directory structure is explained below:
 
-> hw- necessary hardware files (.qpf, .qsf, .sv, .v, .ip) of the design
+- hw- necessary hardware files (.qpf, .qsf, .sv, .v, .ip) of the design
 
-> sw- This folder contains software application files
+- sw- This folder contains software application files
 
-> scripts- This folder consists of scripts to build the design
+- scripts- This folder consists of scripts to build the design
 
 ### 2. Using existing files to run the design on hardware
 
-> The sof and elf files required to run the design can be found in "ready_to_test" folder 
+- The sof and elf files required to run the design can be found in "ready_to_test" folder 
 
-> Refer the Hardware validation section (3.d) for the steps  
+- Refer the Hardware validation section (3.d) for the steps  
 
 
 ### 3. Building the design from scratch
 
 The steps to build the project from scratch are mentioned below:
 
 a. Required directory structure
-    - The top-level project folder should have directory structure as mentioned in Section 1 (Directory Structure).
+- The top-level project folder should have directory structure as mentioned in Section 1 (Directory Structure).
 
 b. Using build_sof.py to compile the design
-    - Invoke the quartus_py shell in the terminal
-    - Run the following command in the terminal from top level project directory:
-    
-        > quartus_py ./scripts/build_sof.py
-	
-    - The quartus tool will compile the design and generate the output files
+- Invoke the quartus_py shell in the terminal
+
+- Run the following command in the terminal from top level project directory:
+```
+quartus_py ./scripts/build_sof.py
+```
+- The quartus tool will compile the design and generate the output files
 
 c. Creating the bsp, build software sources and download elf
-    - To create software app, run the following commands in the terminal:
-    Note:clean the app build project before regenerating elf
-        
-	> niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
-        
-	> niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
-        
-	> niosv-shell
-        
-	> cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
-        
-	> make -C sw/app/build
-	
-    > elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0x9ffff sw/app/build/onchip_mem.hex -r4
-
- Note: Reduce the JTAG clock frequency to 6MHz before programming the application .elf file on the board.
-command: jtagconfig --setparam 1 JtagClock 6M
+- To create software app, run the following commands in the terminal:
+
+- Clean the app build project before regenerating elf
+```        
+niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
+niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
+niosv-shell
+cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
+make -C sw/app/build
+elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0x9ffff sw/app/build/onchip_mem.hex -r4
+```
 
 d. Hardware Validation
-    - Program the generated sof and then download the elf file on the board
-        
-	> quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
-    
-    - Download the elf file on the board 
-    
-	> niosv-download -g ready_to_test/app.elf -c 1
-    
-    - Verify the output on the terminal by using the following command in the terminal:
-    
-	> juart-terminal -d 1 -c 1 -i 0 
+- Program the generated sof and then download the elf file on the board
+```  
+quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
+```
+- Reduce the JTAG clock frequency to 6MHz before programming the application .elf file on the board.
+``` 
+jtagconfig --setparam 1 JtagClock 6M
+```
+- Download the elf file on the board 
+```
+niosv-download -g ready_to_test/app.elf -c 1
+```
+- Verify the output on the terminal by using the following command in the terminal:
+``` 
+juart-terminal -d 1 -c 1 -i 0 
+```
 
 ### 4. Running simulation
 
 Simulation is enabled for this design where the memory is initialized with the application hex. Use the following commands to run the simulation:
 
-   	> Generate Testbench from Platform Designer. Generate -> Generate Testbench System 
-		
- 	> cp ./sw/app/build/onchip_mem.hex ./*_tb/*_tb/sim/mentor 
-	
- 	> cd hw/*_tb/*_tb/sim/mentor/
-
- 	> vsim &
-	
- 	> source msim_setup.tcl
-	
- 	> ld_debug
-	
- 	> run -all
+- Generate Testbench from Platform Designer. Generate -> Generate Testbench System 
+```	
+cp ./sw/app/build/onchip_mem.hex ./qsys_top_tb/qsys_top_tb/sim/mentor 
+cd hw/qsys_top_tb/qsys_top_tb/sim/mentor/
+vsim &
+source msim_setup.tcl
+ld_debug
+run -all
+```