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‎README.md‎

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@@ -36,9 +36,7 @@ The following table contains the list of the designs on Agilex 5 FPGA E-Series 0
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| No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
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| - | --- | ------ | ----------- |
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| 1 | Nios V/m | Nios V/m DMA OCM Design | This design demonstrates the transaction between the Nios® V processor with DMA and OCM core<br>[Design details](niosv_m/niosv_m_dma_ocm/docs/NiosV_m_Processor_DMA_OCM_Design_on_Agilex_5_FPGA.md) |
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| 1 | Nios V/m | Nios V/m Webserver Ping Design | This design demonstrates the transaction between the Nios® V processor with DMA and OCM core<br>[Design details](niosv_m/niosv_m_dma_ocm/docs/NiosV_m_Processor_DMA_OCM_Design_on_Agilex_5_FPGA.md) |
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| 2 | Nios V/g | Nios V/g TinyML LiteRT | This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor<br>[Design details](niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_5_FPGA.md) |
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| 3 | Nios V/g | Nios V/g Helloworld Design | Nios® V/g Processor-based Helloworld example design<br>[Design details](niosv_g/niosv_g_helloworld/docs/Nios_Vg_Processor_Hello_World_Design_on_Agilex_5_FPGA.md) |
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| 4 | Nios V/g | Nios V/g OCM Memory Tese Design | Nios® V/g Processor-based OCM memory test example design<br>[Design details](niosv_g/niosv_g_ocm_mem_test/docs/Nios_Vg_Processor_OCM_Mem_Test_Design_on_Agilex_5_FPGA.md) |
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| 5 | Nios V/c | Nios V/c Helloworld OCM Memory test Design | Nios® V/c Processor-based Helloworld and OCM memory test example design<br>[Design details](niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md) |
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| 6 | Nios V/m | Nios V/m Baseline Golden Hardware Reference Design (GHRD) | This design demonstrates the baseline Golden Hardware Reference Design (GHRD) for a Nios V/m processor with basic bare minimum peripherals required for any application execution <br>[Design details](niosv_m/niosv_m_baseline_ghrd/docs/NiosV_m_Processor_baseline_ghrd_on_Agilex_5_FPGA.md)|
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| 3 | Nios V/c | Nios V/c Helloworld OCM Memory test Design | Nios® V/c Processor-based Helloworld and OCM memory test example design<br>[Design details](niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md) |
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| 4 | Nios V/m | Nios V/m Full Feature Golden Hardware Reference Design (GHRD) | This design demonstrates the baseline Golden Hardware Reference Design (GHRD) for a Nios V/m processor with basic bare minimum peripherals required for any application execution <br>[Design details](niosv_m/niosv_m_baseline_ghrd/docs/NiosV_m_Processor_baseline_ghrd_on_Agilex_5_FPGA.md)|

‎niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md‎

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### Release Contents
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#### Binaries
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- Prebuilt binaries are located [here](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test).
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- Prebuilt binaries are located [here](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test).
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- The sof and elf files required to run the design can be found in "ready_to_test" folder
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- Program the sof and download the elf file on board
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### Nios® V/c Helloworld OCM Memory test Design Architecture
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This example design includes a Nios® V/c processor connected to the On Chip RAM-II, JTAG UART IP, Parallel-IO and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.
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![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
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![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
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#### Nios® V/c Processor
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- Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
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#### Tools Download and Installation
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1. Quartus Prime Pro
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- Download the Quartus® Prime Pro Edition software version 25.1.1 from the FPGA Software Download Center webpage of the Intel website. Follow the on-screen instructions to complete the installation process. Choose an installation directory that is relative to the Quartus® Prime Pro Edition software installation directory.
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- Download the Quartus® Prime Pro Edition software version 25.3 from the FPGA Software Download Center webpage of the Intel website. Follow the on-screen instructions to complete the installation process. Choose an installation directory that is relative to the Quartus® Prime Pro Edition software installation directory.
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- Set up the Quartus tools in the PATH, so they are accessible without full path.
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```console
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export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.1.1/quartus/
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export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.3/quartus/
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export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH
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```
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‎niosv_c/niosv_c_helloworld_ocm_mem_test/sources/README.md‎

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Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1
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![image](https://github.com/altera-fpga/niosv-ed/blob/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
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![image](https://github.com/altera-fpga/niosv-ed/blob/rel/25.3/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
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## Project Details
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- **Source**: Github
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- **Design Support**: SCTH
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- **Family**: Agilex 5
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- **Quartus Version**: 25.1.1
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- **Quartus Version**: 25.3.0
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- **Development Kit**: Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1
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- **Device Part**: A5ED065BB32AE6SR0
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- **Design Package**: agilex5_niosv_c_helloworld_ocm_mem_test.zip
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- **Category**: Memory
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- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test
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- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3/niosv_c/niosv_c_helloworld_ocm_mem_test
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- **download URL**: https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.1.1-v1.0/agilex5_niosv_c_helloworld_ocm_mem_test.zip
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## Documentation

‎niosv_g/README.md‎

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a. Hello World
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b. OCM Memory Test
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c. TinyML LiteRT Example Design
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d. Webserver - Ping operation

niosv_m/niosv_m_baseline_ghrd/README.md renamed to niosv_g/niosv_g_webserver_ping/README.md

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‎niosv_g/niosv_g_webserver_ping/docs/Nios_Vg_Processor_Webserver_Ping_Design_on_Agilex_5_FPGA.md‎

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# Nios® V/g Ping Design
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This design demonstrates the Ping application on a Nios® V/g processor using the Triple Speed Ethernet IP for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.
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## Description
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The example design demonstrates ping application. The Nios V/g acts as the core. The Triple Speed Ethernet (TSE) IP is configured in RGMII mode and connectes to the onboard 88E1512 PHY via RGMII interface.
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The design has 2 MSGDMA IPs configured in Memory Mapped to Stream (MM2S) mode for Transmission and Stream to Memory Mapped (S2MM) mode for Reception.
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To test the application, connect the RGMII Interface of the Agilex 5 Development Kit to the Link Partner using RJ-45 cable.
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Ensure that the IP addresses are modified accordingly in the application code under the following location - sw/app_freertos/main.c
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Once the application binaries are downloaded (See section 3.d below for the steps), the board starts pinging the link partner automatically.
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Observe the Ping Request and Response prints on the terminal.
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![image](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_g/niosv_g_webserver_ping/img/web_server_block_diagram.png)
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## Project Details
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- **Title**: Nios® V/g Ping Design
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- **Source**: Github
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- **Design Support**: CTH
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- **Family**: Agilex 5
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- **Quartus Version**: 25.3
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- **Development Kit**: Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1
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- **Device Part**: A5ED065BB32AE6SR0
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- **Design Package**: agilex5_niosv_g_webserver_ping.zip
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- **Category**: Web Server
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- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_g/niosv_g_webserver_ping
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- **download URL**: https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.3-v1.0/agilex5_niosv_g_webserver_ping.zip
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## Documentation
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- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_g/niosv_g_webserver_ping/docs/NiosV_g_Processor_ping_on_Agilex_5_FPGA.md
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# Getting Started
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Vendor: Altera
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1. Directory structure
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2. Using existing files (sof and elf) to run on hardware
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3. Building the design from scratch
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a. Required directory structure
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b. Use of build_sof.py to compile the design
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c. Steps to create the bsp and build software sources
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d. Hardware Validation
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### 1. Directory Structure:
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The directory structure is explained below:
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- hw- necessary hardware files (.qpf, .qsf, .sv, .v, .ip) of the design
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- sw- This folder contains software application files
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- scripts- This folder consists of scripts to build the design
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### 2. Using existing files to run the design on hardware
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- The sof and elf files required to run the design can be found in "ready_to_test" folder
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- Refer the Hardware validation section (3.d) for the steps
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### 3. Building the design from scratch
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The steps to build the project from scratch are mentioned below:
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a. Required directory structure
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- The top-level project folder should have directory structure as mentioned in Section 1 (Directory Structure).
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b. Using build_sof.py to compile the design
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- Invoke the quartus_py shell in the terminal
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- Run the following command in the terminal from top level project directory:
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```
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quartus_py ./scripts/build_sof.py
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```
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- The quartus tool will compile the design and generate the output files
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c. Creating the bsp, build software sources and download elf
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- To create software app, run the following commands in the terminal:
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- Clean the app build project before regenerating elf
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```
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niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=freertos --cmd="enable_sw_package altera_freertos_tcpip" sw/bsp_freertos/settings.bsp
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niosv-app --bsp-dir=sw/bsp_freertos --app-dir=sw/app_freertos --srcs=sw/app_freertos/main.c
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cmake -S ./sw/app_freertos -B sw/app_freertos/build
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make -C sw/app_freertos/build
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```
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Note:The software can be compiled using the Ashling Visual Studio Code Extension for Altera FPGAs
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For information on the build process, please refer to the following document- [Ashling VSCode Extension](https://www.intel.com/content/www/us/en/docs/programmable/730783/current/ashling-visual-studio-code-extension.html)
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d. Hardware Validation
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- Program the generated sof and then download the elf file on the board
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```
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quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
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```
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- Reduce the JTAG clock frequency to 6MHz before programming the application .elf file on the board.
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```
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jtagconfig --setparam 1 JtagClock 6M
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```
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- Toggle the In-System-Sources and Probe (ISSP) IP to initialize PHY and set it to 1G.
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```
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quartus_stp -t ready_to_test/toggle_issp.tcl
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```
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- Download the elf file on the board
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```
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niosv-download -g ready_to_test/app.elf -c 1
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```
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- Verify the output on the terminal by using the following command in the terminal:
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```
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juart-terminal -d 1 -c 1 -i 0
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```

‎niosv_g/niosv_g_webserver_ping/img/web_server_block_diagram.png‎

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‎niosv_g/niosv_g_webserver_ping/ready_to_test/tflite_app.elf‎

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‎niosv_g/niosv_g_webserver_ping/ready_to_test/top.sof‎

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niosv_m/niosv_m_baseline_ghrd/sources/README.md renamed to niosv_g/niosv_g_webserver_ping/sources/README.md

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# Nios® V/m Baseline Golden Hardware Reference Design (GHRD)
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# Nios® V/g Ping Design
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This design demonstrates the baseline Golden Hardware Reference Design (GHRD) for a Nios® V/m processor with basic bare minimum peripherals required for any application execution for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.
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This design demonstrates the Ping application on a Nios® V/g processor using the Triple Speed Ethernet IP for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.
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## Description
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This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel-IO and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.
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The example design demonstrates ping application. The Nios V/g acts as the core. The Triple Speed Ethernet (TSE) IP is configured in RGMII mode and connectes to the onboard 88E1512 PHY via RGMII interface.
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The design has 2 MSGDMA IPs configured in Memory Mapped to Stream (MM2S) mode for Transmission and Stream to Memory Mapped (S2MM) mode for Reception.
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![image](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_m/niosv_m_baseline_ghrd/img/baseling_ghrd_block_design.png)
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To test the application, connect the RGMII Interface of the Agilex 5 Development Kit to the Link Partner using RJ-45 cable.
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Ensure that the IP addresses are modified accordingly in the application code under the following location - sw/app_freertos/main.c
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Once the application binaries are downloaded (See section 3.d below for the steps), the board starts pinging the link partner automatically.
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Observe the Ping Request and Response prints on the terminal.
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![image](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_g/niosv_g_webserver_ping/img/web_server_block_diagram.png)
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## Project Details
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- **Title**: Nios® V/m Baseline Golden Hardware Reference Design (GHRD)
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- **Title**: Nios® V/g Ping Design
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- **Source**: Github
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- **Design Support**: SCTH
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- **Design Support**: CTH
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- **Family**: Agilex 5
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- **Quartus Version**: 25.1.1
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- **Quartus Version**: 25.3
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- **Development Kit**: Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1
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- **Device Part**: A5ED065BB32AE6SR0
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- **Design Package**: agilex5_niosv_m_baseline_ghrd.zip
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- **Category**: GHRD
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- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_m/niosv_m_baseline_ghrd
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- **download URL**: https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.1.1-v1.0/agilex5_niosv_m_baseline_ghrd.zip
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- **Design Package**: agilex5_niosv_g_webserver_ping.zip
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- **Category**: Web Server
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- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_g/niosv_g_webserver_ping
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- **download URL**: https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.3-v1.0/agilex5_niosv_g_webserver_ping.zip
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## Documentation
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- **Title**: Design Document
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- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_m/niosv_m_baseline_ghrd/docs/NiosV_m_Processor_baseline_ghrd_on_Agilex_5_FPGA.md
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- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3/niosv_g/niosv_g_webserver_ping/docs/NiosV_g_Processor_ping_on_Agilex_5_FPGA.md
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# Getting Started
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c. Steps to create the bsp and build software sources
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d. Hardware Validation
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4. Running simulation
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### 1. Directory Structure:
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- Clean the app build project before regenerating elf
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```
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niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
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niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
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niosv-shell
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cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
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make -C sw/app/build
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elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0xfffff sw/app/build/onchip_mem.hex -r4
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niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=freertos --cmd="enable_sw_package altera_freertos_tcpip" sw/bsp_freertos/settings.bsp
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niosv-app --bsp-dir=sw/bsp_freertos --app-dir=sw/app_freertos --srcs=sw/app_freertos/main.c
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cmake -S ./sw/app_freertos -B sw/app_freertos/build
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make -C sw/app_freertos/build
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```
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Note:The software can be compiled using the Ashling Visual Studio Code Extension for Altera FPGAs
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```
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jtagconfig --setparam 1 JtagClock 6M
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```
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- Toggle the In-System-Sources and Probe (ISSP) IP to initialize PHY and set it to 1G.
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```
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quartus_stp -t ready_to_test/toggle_issp.tcl
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```
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- Download the elf file on the board
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```
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niosv-download -g ready_to_test/app.elf -c 1
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```
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- Verify the output on the terminal by using the following command in the terminal:
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```
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juart-terminal -d 1 -c 1 -i 0
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```
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### 4. Running simulation
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Simulation is enabled for this design where the memory is initialized with the application hex. Use the following commands to run the simulation:
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- Generate Testbench from Platform Designer. Generate -> Generate Testbench System
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```
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cp ./sw/app/build/onchip_mem.hex ./qsys_top_tb/qsys_top_tb/sim/mentor
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cd hw/qsys_top_tb/qsys_top_tb/sim/mentor/
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vsim &
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source msim_setup.tcl
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ld_debug
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run -all
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```

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