Updated Readme

Author: paddy3696

niosv_c/niosv_c_helloworld_ocm_mem_test/sources/README.md

@@ -49,7 +49,7 @@ c. Creating the bsp, build software sources and download elf
 
         > clean the app build project before regenerating elf
 
-        > niosv-bsp -c --quartus-project=hw/<>.qpf --qsys=hw/<>.qsys --type=hal --script=sw/bsp-update-small-driver.tcl sw/bsp/settings.bsp
+        > niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal --script=sw/bsp-update-small-driver.tcl sw/bsp/settings.bsp
 
         > niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
 
@@ -68,7 +68,7 @@ command: jtagconfig --setparam 1 JtagClock 6M
 d. Hardware Validation
     - Program the generated sof file on the board
 
-        >  quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/<top_level_entity_name>.sof'
+        >  quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
 
     - Verify the output on the terminal by using the following command in the terminal:
         
@@ -79,11 +79,11 @@ d. Hardware Validation
 Simulation is enabled for this design where the memory is initialized with the application hex. Use the following commands to run the simulation:
 
 	> Generate Testbench from Platform Designer. Generate -> Generate Testbench System
-	
- 	> cd hw/*_tb/*_tb/sim/mentor/
-  
+	  
 	> cp ./sw/app/build/onchip_mem.hex ./*_tb/*_tb/sim/mentor
 
+ 	> cd hw/*_tb/*_tb/sim/mentor/
+
 	> vsim &
 
 	> source msim_setup.tcl

niosv_g/niosv_g_helloworld/sources/README.md

@@ -45,7 +45,7 @@ c. Creating the bsp, build software sources and download elf
     - To create software app, run the following commands in the terminal:
 	Note: clean the app build project before regenerating elf
 
-        > niosv-bsp -c --quartus-project=hw/<>.qpf --qsys=hw/<>.qsys --type=hal sw/bsp/settings.bsp
+        > niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
 
         > niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
 
@@ -64,11 +64,11 @@ command: jtagconfig --setparam 1 JtagClock 6M
 d. Hardware Validation
     - Program the generated sof and then download the elf file on the board
 
-        > quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/<top_level_entity_name>.sof'
+        > quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
 
     - Download the elf file on the board 
 
-    	> niosv-download -g ready_to_test/<>.elf -c 1
+    	> niosv-download -g ready_to_test/app.elf -c 1
 
     - Verify the output on the terminal by using the following command in the terminal:
 
@@ -79,10 +79,10 @@ d. Hardware Validation
 Simulation is enabled for this design where the memory is initialized with the application hex. Use the following commands to run the simulation:
 
 	> Generate Testbench from Platform Designer. Generate -> Generate Testbench System
-	
- 	> cd hw/*_tb/*_tb/sim/mentor/
-  
+	  
 	> cp ./sw/app/build/onchip_mem.hex ./*_tb/*_tb/sim/mentor
+    
+ 	> cd hw/*_tb/*_tb/sim/mentor/
 
 	> vsim &
 

niosv_g/niosv_g_ocm_mem_test/sources/README.md

@@ -48,7 +48,7 @@ c. Creating the bsp, build software sources and download elf
     - To create software app, run the following commands in the terminal:
     Note:clean the app build project before regenerating elf
 
-	> niosv-bsp -c --quartus-project=hw/<>.qpf --qsys=hw/<>.qsys --type=hal sw/bsp/settings.bsp
+	> niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal sw/bsp/settings.bsp
 
 	> niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
 
@@ -66,11 +66,11 @@ command: jtagconfig --setparam 1 JtagClock 6M
 d. Hardware Validation
     - Program the generated sof and then download the elf file on the board
 
-	> quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/<top_level_entity_name>.sof'
+	> quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
 
     - Download the elf file on the board 
 
-	> niosv-download -g ready_to_test/<>.elf -c 1
+	> niosv-download -g ready_to_test/app.elf -c 1
 
     - Verify the output on the terminal by using the following command in the terminal:
 
@@ -81,11 +81,11 @@ d. Hardware Validation
 Simulation is enabled for this design where the memory is initialized with the application hex. Use the following commands to run the simulation:
 
    	> Generate Testbench from Platform Designer. Generate -> Generate Testbench System 
-	
- 	> cd hw/*_tb/*_tb/sim/mentor/
-	
+		
  	> cp ./sw/app/build/onchip_mem.hex ./*_tb/*_tb/sim/mentor 
 
+ 	> cd hw/*_tb/*_tb/sim/mentor/
+
  	> vsim &
 
  	> source msim_setup.tcl