updating README.md

Author: nithinkumark94

niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_5_FPGA.md

@@ -19,7 +19,7 @@ This design demonstrates the TinyML application using LiteRT for microcontroller
 ### Nios® V/g TinyML LiteRT Design Archiecture
  This example design includes a Nios® V processor connected to the On Chip RAM-II, JTAG UART IP and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.
 
- ![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_g/tinyml_liteRT/img/block_diagram.png)
+ ![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_g/tinyml_liteRT/img/block_diagram.png?raw=true)
 
 #### Nios® V/g Processor 
 - Balanced (For interrupt driven baremetal and RTOS code)

niosv_m/niosv_m_baseline_ghrd/docs/NiosV_m_Processor_baseline_ghrd_on_Agilex_5_FPGA.md

@@ -20,7 +20,7 @@
 ### Nios® V/m Baseline Golden Hardware Reference Design (GHRD) Archiecture
  This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel-IO and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.
 
- ![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_m/niosv_m_baseline_ghrd/img/baseling_ghrd_block_design.png)
+ ![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_m/niosv_m_baseline_ghrd/img/baseling_ghrd_block_design.png?raw=true)
 
 #### Nios® V/m Processor
 - Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)