Update Agilex 7 PCIe Root Port Design with Quartus 25.1.1

Update Agilex™ 7 PCIe Root Port System Example Design of Mseries, Iseries and
Fseries with Quartus 25.1.1

Signed-off-by: Mahesh Vaidya <[email protected]>

Author: maheshv1203

.gitmodules

@@ -1,20 +1,24 @@
-[submodule "poky"]
+[submodule "src/sw/poky"]
 	path = src/sw/poky
 	url = https://git.yoctoproject.org/git/poky
-	branch = scarthgap
-[submodule "meta-intel-fpga"]
-	path = src/sw/meta-intel-fpga
-	url = https://git.yoctoproject.org/git/meta-intel-fpga
-	branch = scarthgap
-[submodule "meta-intel-fpga-refdes"]
+	branch = walnascar
+[submodule "src/sw/meta-intel-fpga"]
+        path = src/sw/meta-intel-fpga
+	url = https://git.yoctoproject.org/meta-intel-fpga/
+	branch = walnascar
+[submodule "src/sw/meta-intel-fpga-refdes"]
 	path = src/sw/meta-intel-fpga-refdes
-	url = https://github.com/altera-opensource/meta-intel-fpga-refdes.git
-	branch = scarthgap
-[submodule "meta-openembedded"]
-	path = src/sw/meta-openembedded
+	url = https://github.com/altera-fpga/meta-intel-fpga-refdes 
+	branch = walnascar
+[submodule "src/sw/meta-openembedded"]
+        path = src/sw/meta-openembedded
 	url = https://git.openembedded.org/meta-openembedded
-	branch = scarthgap
-[submodule "meta-clang"]
-	path = src/sw/meta-clang
+	branch = walnascar
+[submodule "src/sw/meta-clang"]
+        path = src/sw/meta-clang
 	url = https://github.com/kraj/meta-clang.git
-	branch = scarthgap
+	branch = walnascar
+[submodule "src/sw/meta-virtualization"]
+	path = src/sw/meta-virtualization
+	url = https://git.yoctoproject.org/git/meta-virtualization
+	branch = walnascar

src/sw/README.md

@@ -8,21 +8,30 @@ The following targets are currently supported:
 
 |    Board                                         |   OPN            |
 | ------------------------------------------------ | ---------------- |
+| Intel® Agilex™ 7 FPGA F-Series Development Kit   | DK-DEV-AGF014EB  |
+| ------------------------------------------------ | ---------------- |
+| Intel® Agilex™ 7 FPGA I-Series Development Kit   | DK-DEV-AGI027FC  |
+| ------------------------------------------------ | ---------------- |
 | Intel® Agilex™ 7 FPGA M-Series Development Kit   | DK-DEV-AGM039FES |
 
+
 ## Yocto Build Instructions
 
  1. Clone the repository:
 
     ```
-    git clone https://github.com/altera-fpga/agilex7-ed-pcie-rp
+    git clone https://github.com/altera-fpga/agilex7-ed-pcie-rp.git
     cd agilex7-ed-pcie-rp/src/sw/
     ```
 
  2. Source the script to set component versions (Linux, U-Boot, ATF, Machine, Image):
 
     |    Board                                         |   Command                                  |
     | ------------------------------------------------ | ------------------------------------------ |
+    | Intel® Agilex™ 7 FPGA F-Series Development Kit   | `. agilex7_dk_si_agf014eb-gsrd-build.sh`   |
+    | ------------------------------------------------ | ------------------------------------------ |
+    | Intel® Agilex™ 7 FPGA I-Series Development Kit   | `. agilex7_dk_si_agi027fc-gsrd-build.sh`   |
+    | ------------------------------------------------ | ------------------------------------------ |
     | Intel® Agilex™ 7 FPGA M-Series Development Kit   | `. agilex7_dk_dev_agm039fes-rped-build.sh` |
 
  3. Setup the build environment:
@@ -31,13 +40,38 @@ The following targets are currently supported:
     build_setup
     ```
 
- 4. Perform Yocto bitbake to generate binaries:
+ 4. OPTIONAL:  CUSTOM GHRD:
+
+              a. Add custom GHRD design in the below path:
+                   $WORKSPACE/src/sw/meta-altera-pcie-rp/recipes-bsp/ghrd/files/
+                   NOTE: Update/Replace the GHRD core rbf file with the same naming convention given below
+                            For Agilex7 DK-DEV-AGF014EB:-
+                                          agilex7_dk_si_agf014eb_gsrd_ghrd.core.rbf
+                            For Agilex7 DK-DEV-AGI027FC:-
+                                          agilex7_dk_si_agi027fc_gsrd_ghrd.core.rbf
+                            For Agilex7 DK-DEV-AGM039FES:-
+                                          agilex7_dk_dev_agm039fes_rped_ghrd.core.rbf
+
+              b. Update sha256sum of the above updated in the below recipe:
+                    $WORKSPACE/src/sw/meta-altera-pcie-rp/recipes-bsp/ghrd/hw-ref-design.bbappend
+                        Example:-
+
+                        For Agilex7 DK-DEV-AGF014EB:-
+                        SRC_URI[agilex7_dk_si_agf014eb_gsrd_core.sha256sum] = "xxxxxx"
+
+                        For Agilex7 DK-DEV-AGI027FC:-
+                        SRC_URI[agilex7_dk_si_agi027fc_gsrd_core.sha256sum] = "xxxxxx"
+
+                        For Agilex7 DK-DEV-AGM039FES:-
+                        SRC_URI[agilex7_dk_dev_agm039fes_rped_core.sha256sum] = "xxxxxx"
+
+ 5. Perform Yocto bitbake to generate binaries:
 
     ```
     bitbake_image
     ```
 
- 5. Package binaries into build folder:
+ 6. Package binaries into build folder:
 
     ```
     package

src/sw/agilex7_dk_si_agf014eb-gsrd-build.sh

@@ -0,0 +1 @@
+build.sh

src/sw/agilex7_dk_si_agi027fc-gsrd-build.sh

@@ -0,0 +1 @@
+build.sh