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Girisha Dengigdengi
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HSD#15017037436 arm64: dts: agilex5: add DTS support to enable ATF NAND boot
Add new DTS file to update the boot args and flash partition details to accommodate the new FIP partition for ATF direct NAND boot method. Signed-off-by: Girisha Dengi <[email protected]>
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arch/arm64/boot/dts/intel/Makefile

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@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
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socfpga_agilex5_socdk_emmc.dtb \
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socfpga_agilex5_socdk_nand.dtb \
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socfpga_agilex5_socdk_nand_b0.dtb \
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socfpga_agilex5_socdk_nand_b0_atfboot.dtb \
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socfpga_agilex5_socdk_swvp_b0.dtb \
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socfpga_agilex5_socdk_tsn_cfg2.dtb \
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socfpga_agilex5_socdk_tsn_cfg2_b0.dtb \
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2025, Altera Corporation. All rights reserved.
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*/
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#include "socfpga_agilex5_socdk_nand_b0.dts"
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/ {
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model = "SoCFPGA Agilex5 SoCDK";
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compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "console=uart8250,mmio32,0x10c02000,115200n8 \
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earlycon=uart8250,mmio32,0x10c02000,115200n8 \
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panic=-1 \
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root=ubi0:rootfs rw rootwait rootfstype=ubifs ubi.mtd=2";
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};
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};
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&nand {
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status = "okay";
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/delete-node/ flash@0;
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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nand-bus-width = <8>;
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partition@0 {
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label = "u-boot";
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reg = <0 0x200000>;
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};
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partition@200000 {
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label = "fip";
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reg = <0x200000 0x03200000>;
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};
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partition@3400000 {
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label = "root";
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reg = <0x03400000 0xfcc00000>;
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};
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};
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};

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