list.json

{
    "num": 93,
    "designs": [
        {
            "id": "-",
            "title": "Agilex 7 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/img/block_diagram.png\"/></p>",
            "category": "AI",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1-v1.0/agilex7_niosv_g_tinyml_liteRT.zip",
            "downloadUrl": "agilex7_niosv_g_tinyml_liteRT.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_7_FPGA.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/344658973",
            "Q_GITHUB_RELEASE": "25.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Nios V/m Transceiver Loopback design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF027F1ES",
            "device_part": "AGFD023R24C2E1VC",
            "description": "F-Tile Transceiver loopback design on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)",
            "rich_description": "<p>This design demonstrates the serial loopback via QSFPDD on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/img/niosv_xcver.png\"/></p>",
            "category": "Transceiver",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1-v1.0/agilex7_xcver_loopback.zip",
            "downloadUrl": "agilex7_xcver_loopback.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/docs/Nios_Vm_Processor_PAM4_8x53Gbps_with_QSFPDD_Serial_loopback_design.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/344685849",
            "Q_GITHUB_RELEASE": "25.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Lockstep Example Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based Lockstep example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>This design demonstrates the working of NiosV/g lockstep feature through the standard fail safe control mechanism using by injecting root faults and reading alarms with Nios® V/m as the system supervisor on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.1/agf014ea-dev-devkit/niosv_g/lockstep/img/block_diagram.png\"/></p>",
            "category": "Nios V",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1-v1.0/agilex7_niosv_g_lockstep.zip",
            "downloadUrl": "agilex7_niosv_g_lockstep.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.1/agf014ea-dev-devkit/niosv_g/lockstep/docs/Nios_Vg_Processor_Lockstep_Design_on_Agilex_7_FPGA.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/348032378",
            "Q_GITHUB_RELEASE": "25.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Lockstep Example Design Example on Nios V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.3.0",
            "patch_number": "Unknown",
            "devkit": "Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios V/g Processor-based Lockstep example design on the Agilex 7 FPGA.",
            "rich_description": "<p>This design demonstrates the working of NiosV/g lockstep feature through the standard fail safe control mechanism using by injecting root faults and reading alarms with Nios V/m as the system supervisor on Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.0/agf014ea-dev-devkit/niosv_g/lockstep/img/block_diagram.png\"/></p>",
            "category": "Nios V",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.3.0/agf014ea-dev-devkit/niosv_g/lockstep",
            "downloadUrl": "agilex7_niosv_g_lockstep.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.0/agf014ea-dev-devkit/niosv_g/lockstep/docs/Nios_Vg_Processor_Lockstep_Design_on_Agilex_7_FPGA.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/303653381",
            "Q_GITHUB_RELEASE": "25.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Processor Transceiver Loopback design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.3.0",
            "patch_number": "Unknown",
            "devkit": "Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF027F1ES",
            "device_part": "AGFD023R24C2E1VC",
            "description": "F-Tile Transceiver loopback design on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)",
            "rich_description": "<p>This design demonstrates the serial loopback via QSFPDD on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.0/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/img/niosv_xcver.png\"/></p>",
            "category": "Transceiver",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.3.0/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/",
            "downloadUrl": "agilex7_xcver_loopback.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.0/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/docs/Nios_Vm_Processor_PAM4_8x53Gbps_with_QSFPDD_Serial_loopback_design.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/303653851",
            "Q_GITHUB_RELEASE": "25.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/c Processor PIO & OCM Test Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1 Pro",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "This design demonstrates the transaction between the Nios® V processor and the PIO core along with OCM Memory test.",
            "rich_description": "<p>The PIO core is configured for output ports only and the outputs are connected to the LED on the development kit. The application, which runs atop this design, toggles these output registers of the PIO core. The application writes and reads back the content from the IP location. Additionally, the OCM memory tests are performed.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_c/pio_ocm/img/pio.png\"/></p>",
            "category": "PIO LED Toggle",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_c/pio_ocm/docs/Nios_Vc_Processor_PIO_OCM_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_c_pio_ocm.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291413003",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Custom Instruction CRC Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based custom instruction Cyclic Redundancy Check (CRC) example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>A Processing Engine (PE) that performs the Cyclic Redundancy Check (CRC) algorithm is connected to the Nios® V/g processor using the custom instruction interface</p><p>The current version of the Nios® V/g processor custom instruction interface supports operations up-to 32-Bit. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_crc/img/niosv_ci_example.png\"/></p>",
            "category": "Custom Instruction",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_crc/docs/Nios_Vg_Processor_CI_CRC_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_g_ci_crc.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291405074",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Custom Instruction Basic Operations Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based custom instruction example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>A Processing Engine (PE) that performs basic arithmetic and logical computations is connected to the Nios® V/g processor using the custom instruction interface. </p><p>The current version of the Nios® V/g processor custom instruction interface supports operations up-to 32-Bit. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_basic_operations/img/niosv_ci_example.png\"/></p>",
            "category": "",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_basic_operations/docs/Nios_Vg_Processor_CI_Basic_Operations_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_ci_basic_operations.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291397552",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/g Processor ECC Lite test Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Agilex 7 FPGA - ECC Lite Design Example on Nios® V/g Processor",
            "rich_description": "<p>This design demonstrates the ECC Lite feature of the Nios® V/g core by injecting an error on the General-Purpose Register (GPR) via simulation.</p><p>The ECC status and ECC source is observed for both correctable and uncorrectable errors on the General-Purpose Registers (GPR).</p><p>The Error is injected on the OCM (M20k) GPR through the ECC parity flip feature. The parity value in the GPR is flipped using the force command in the test bench file (sys_tb.v). </p><p>The ECC Status and ECC Source signals are probed and observed using Questa Simulation</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ecc_lite/img/ecc_lite.png\"/></p>",
            "category": "ECC",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ecc_lite/docs/NiosV_g_Processor_ECC_Lite_test_Example_design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_ecc_lite.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290940866",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/g Processor Floating Point Unit (FPU) Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios V/g Processor-based design example with Floating Point Unit (FPU) on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)",
            "rich_description": "<p>This example design is about applying the floating point unit in Nios V/g processor. The example application evaluates the floating point rate of Nios V/g processor by using Linpack benchmark.\n More information on the Linpack Benchmark can be found here- https://top500.org/project/linpack/</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014eb-si-devkit/niosv_g/fpu_test/img/block_diagram.png\"/></p>",
            "category": "FPU",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014eb-si-devkit/niosv_g/fpu_test/docs/NiosV_g_Processor_Floating_Point_Unit_Example_design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_g_fpu_test.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290947492",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Tightly Coupled Memory (TCM) Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based TCM example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>This example design is about how to use tightly coupled memory in Nios® V/g processor. The example application measures the memory access speed of different memories connected to the processor, such as TCM, on-chip memory and external memory interface (EMIF). In addition to that, the application showcases the speedup between cached and un-cached memories.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014eb-si-devkit/niosv_g/tcm_mem_test/img/niosv_tcm.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014eb-si-devkit/niosv_g/tcm_mem_test/docs/Nios_Vg_Processor_Tightly_Coupled_Memory_Test_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_tcm.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291236753",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/img/block_diagram.png\"/></p>",
            "category": "Machine Learning",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/25.1.1-v1.0/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_g_tinyml_liteRT.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291414938",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Hello World Example Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based Hello World example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>Nios® V/g Processor-based Helloworld example design on the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_g/hello_world/img/hello_world.png\"/></p>",
            "category": "Hello World",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_g/hello_world/docs/Nios_Vg_Processor_Hello_World_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_g_hello_world.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290930424",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Hello World Example Design Example on Nios® V/m Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/m Processor-based Hello World example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>Nios® V/m Processor-based Helloworld example design on the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/hello_world/img/hello_world.png\"/></p>",
            "category": "Hello World",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_m/hello_world/docs/Nios_Vm_Processor_Hello_World_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_m_hello_world.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290925870",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Processor DMA - OCM Memory test Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios V/m Processor-based Direct Memory Access (DMA) and On-Chip Memory (OCM) Test design Example on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the DMA, On Chip RAM and JTAG UART IP. \nThe objective of the design is to accomplish a data transfer between the 2 On Chip RAM using a DMA (MSGDMA) IP. \nDMA facilitates the data transfer which is then read back by the processor.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/dma_ocm_mem_test/img/dma_ocm.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_m/dma_ocm_mem_test/docs/Nios_Vm_Processor_DMA_OCM_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_m_dma_ocm_mem_test.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290951914",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Processor OCM to OCM Memory test Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios V/m Processor-based On-Chip Memory (OCM) Test design Example on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the OCM and JTAG UART IP. \nThe objective of the design is to write and read into specific locations of On Chip RAM. This implementation of On Chip RAM uses the Avalon interface.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/ocm_mem_test/img/ocm_mem_test.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_m/ocm_mem_test/docs/NiosV_m_Processor_OCM_Memory_test_Example_design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_m_ocm_mem_test.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290944187",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Processor PIO LED toggle Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "This design demonstrates the transaction between the Nios® V processor and the PIO core.",
            "rich_description": "<p>The PIO core is configured for output ports only and the outputs are connected to the LED on the development kit. The application, which runs atop this design, toggles these output registers of the PIO core. The application writes and reads back the content from the IP location. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/pio_test/img/pio.png\"/></p>",
            "category": "PIO LED Toggle",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_m/pio_test/docs/NiosV_m_Processor_PIO_test_Example_design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_m_pio_led_toggle.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290937863",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Processor Timer Interval Interrupt Test Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios V/m Processor-based Timer Interrupt design Example on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the Interval Timer IP to issue alarm-based interrupt to the NIOSV/m core. \nThe objective of the design is to demonstrate the interrupt behavior and handling by the Nios V embedded processor. Once the interrupt is issued; the Nios V prints the system ID of the SYS ID peripheral core.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/isr_test/img/isr_test.png\"/></p>",
            "category": "Timer",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_m/isr_test/docs/NiosV_m_Processor_Timer_Interval_Interrupt_Test_Example_design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_m_isr_test.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290854574",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Iperf Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)",
            "device_part": "AGFB014R24B2E2V",
            "description": "Perf 2 is a benchmarking tool for measuring performance between two systems, and it can be used as a server or a client.",
            "rich_description": "<p>An iPerf server receives an iPerf request sent over a TCP/IP connection from any iPerf clients and runs the iPerf test according to the provided arguments.\n Each test reports the bandwidth, loss, and other parameters. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_iperf/img/agilex7_iperf.png\"/></p>",
            "category": "Web Server",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_iperf/docs/NiosV_m_Processor_Iperf_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_sisoc_iperf.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290881313",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m SSS Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)",
            "device_part": "AGFB014R24B2E2V",
            "description": "Simple Socket Server design on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)",
            "rich_description": "<p>The telnet client offers a convenient way of issuing commands over a TCP/IP socket to the Ethernet-connected μC/TCP-IP running on the development board with a simple TCP/IP socket server example. \n The socket server example receives commands sent over a TCP/IP connection and turns LEDs on and off according to the commands. \n The example consists of a socket server task that listens for commands on a TCP/IP port and dispatches those commands to a set of LED management tasks.  </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_sss/img/agilex7_sss.png\"/></p>",
            "category": "Web Server",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_sss/docs/NiosV_m_Processor_SSS_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_sisoc_sss.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290922946",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Processor Transceiver Loopback design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF027F1ES",
            "device_part": "AGFB027R24C2E2VR2",
            "description": "F-Tile Transceiver loopback design on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)",
            "rich_description": "<p>This design demonstrates the serial loopback via QSFPDD on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/img/niosv_xcver.png\"/></p>",
            "category": "Transceiver",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/docs/Nios_Vm_Processor_PAM4_8x53Gbps_with_QSFPDD_Serial_loopback_design.md",
            "downloadUrl": "agilex7_xcver_loopback.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/290924003",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Processor EMIF data mover Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios V/m Processor-based External Memory Interface (EMIF) data mover example design on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the External Memory Interface (EMIF), DMA, On Chip RAM and JTAG UART IP. \nThe objective of the design is to accomplish a data transfer between the On Chip RAM and the DDR (EMIF) using a DMA (MSGDMA) IP. \nDMA facilitates the data transfer which is then read back by the processor.</p><p>This design uses the Nios V processor hosted on the fabric to communicate with the external memory-DDR micron module. \nThe code is booted from the on-chip memory, whereas the Nios V processor carries out certain transactions to and from the DDR using the EMIF controller.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/emif_mem_test/img/emif.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_m/emif_mem_test/docs/Nios_Vm_Processor_EMIF_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_m_emif_mem_test.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291294615",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Processor DDR,DMA and OCM Memory test Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios V/m Processor-based Memory Test design Example on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "rich_description": "<p>This example design includes a NIOS V/m embedded processor connected to the External Memory Interface (EMIF), DMA, On Chip RAM and JTAG UART IP. \nThe objective of the design is to accomplish a data transfer between the On Chip RAM and the DDR (EMIF) using a DMA (MSGDMA) IP. \nDMA facilitates the data transfer which is then read back by the processor.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_m/ddr_dma_ocm_mem_test/img/ddr_dma.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_m/ddr_dma_ocm_mem_test/docs/Nios_Vm_Processor_DDR_DMA_Design_on_Agilex_7_FPGA.md",
            "downloadUrl": "agilex7_niosv_m_ddr_dma_ocm_mem_test.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/291294306",
            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/g Processor Floating Point Unit (FPU) Design",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.0",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios V/g Processor-based design example with Floating Point Unit (FPU) on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit (P-Tile and E-Tile)",
            "rich_description": "<p>This example design is about applying the floating point unit in Nios V/g processor. The example application evaluates the floating point rate of Nios V/g processor by using Linpack benchmark.\n More information on the Linpack Benchmark can be found here- https://top500.org/project/linpack/</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.0/agf014eb-si-devkit/niosv_g/fpu_test/img/block_diagram.png\"/></p>",
            "category": "FPU",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.1.0-v1.0/agilex7_niosv_g_fpu_test.zip",
            "downloadUrl": "agilex7_niosv_g_fpu_test.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/247498881",
            "Q_GITHUB_RELEASE": "25.1.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "25.1.0",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.0/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/img/block_diagram.png\"/></p>",
            "category": "Machine Learning",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.1.0-v1.0/agilex7_niosv_g_tinyml_liteRT.zip",
            "downloadUrl": "agilex7_niosv_g_tinyml_liteRT.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/247502695",
            "Q_GITHUB_RELEASE": "25.1.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Iperf Design Example on Nios® V/m Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.1 Pro",
            "devkit": "Agilex 7 FPGA F-Series Transceiver-SoC Development Kit P-Tile and E-Tile DK-SI-AGF014EB",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/m Processor-based Iperf example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>Perf 2 is a benchmarking tool for measuring performance between two systems, and it can be used as a server or a client.</p><p>An iPerf server receives an iPerf request sent over a TCP/IP connection from any iPerf clients and runs the iPerf test according to the provided arguments. </p><p>Each test reports the bandwidth, loss, and other parameters.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_iperf/img/agilex7_iperf.png\"/></p>",
            "category": "Web Server",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/24.3.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_iperf",
            "downloadUrl": "agilex7_sisoc_iperf.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/227789862",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Simple Socket Server (SSS) Design Example on Nios® V/m Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.1 Pro",
            "devkit": "Agilex 7 FPGA F-Series Transceiver-SoC Development Kit P-Tile and E-Tile DK-SI-AGF014EB",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/m Processor-based SSS example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>This example design demonstrates communication with a telnet client on a development host PC.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_sss/img/agilex7_sss.png\"/></p>",
            "category": "Web Server",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/24.3.1/agf014eb-si-devkit/niosv_m/agilex7_sisoc_sss/",
            "downloadUrl": "agilex7_sisoc_sss.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/227789872",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Transceiver loopback Design Example on Nios® V/m Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.1 Pro",
            "devkit": "Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF027F1ES",
            "device_part": "AGFB027R24C2E2VR2",
            "description": "",
            "rich_description": "<p>This design demonstrates the serial loopback via QSFPDD on Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF027F1ES</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/img/niosv_xcver.png\"/></p>",
            "category": "Transceiver Loopback",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/24.3.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp",
            "downloadUrl": "agilex7_xcver_loopback_design.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/227795504",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Custom Instruction Basic Operations Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.1 Pro",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based custom instruction example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>A Processing Engine (PE) that performs basic arithmetic and logical computations is connected to the Nios® V/g processor using the custom instruction interface. </p><p>The current version of the Nios® V/g processor custom instruction interface supports operations up-to 32-Bit. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3.1/agf014ea-dev-devkit/niosv_g/ci_basic_operations/img/niosv_ci_example.png\"/></p>",
            "category": "Custom Instruction",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/24.3.1/agf014ea-dev-devkit/niosv_g/ci_basic_operations",
            "downloadUrl": "agilex7_ci_basic_operations.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/230247565",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Custom Instruction CRC Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.1 Pro",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based custom instruction Cyclic Redundancy Check (CRC) example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>A Processing Engine (PE) that performs the Cyclic Redundancy Check (CRC) algorithm is connected to the Nios® V/g processor using the custom instruction interface</p><p>The current version of the Nios® V/g processor custom instruction interface supports operations up-to 32-Bit. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3.1/agf014ea-dev-devkit/niosv_g/ci_crc/img/niosv_ci_example.png\"/></p>",
            "category": "Custom Instruction",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/24.3.1/agf014ea-dev-devkit/niosv_g/ci_crc",
            "downloadUrl": "agilex7_ci_crc.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/230247575",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - ECC Lite Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.1 Pro",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based ECC Lite example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>This design demonstrates the ECC Lite feature of the Nios® V/g core by injecting an error on the General-Purpose Register (GPR) via simulation.</p><p>The ECC status and ECC source is observed for both correctable and uncorrectable errors on the General-Purpose Registers (GPR).</p><p>The Error is injected on the OCM (M20k) GPR through the ECC parity flip feature. The parity value in the GPR is flipped using the force command in the test bench file (sys_tb.v). </p><p>The ECC Status and ECC Source signals are probed and observed using Questa Simulation</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3.1/agf014ea-dev-devkit/niosv_g/ecc_lite/img/ecc_lite.png\"/></p>",
            "category": "ECC",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/24.3.1/agf014ea-dev-devkit/niosv_g/ecc_lite",
            "downloadUrl": "agilex7_ecc_lite.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/230251292",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - PIO and OCM test Design Example on Nios® V/c Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.1 Pro",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/c Processor-based PIO and OCM test example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>Nios® V/c processor-based PIO and OCM memory test example design on the Agilex® 7 FPGA</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3.1/agf014ea-dev-devkit/niosv_c/pio_ocm/img/niosv_compact_core_pio.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/24.3.1/agf014ea-dev-devkit/niosv_c/pio_ocm",
            "downloadUrl": "agilex7_niosv_c_pio_ocm.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/230251382",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Tightly Coupled Memory (TCM) Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.1 Pro",
            "devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/g Processor-based TCM example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>This example design is about how to use tightly coupled memory in Nios® V/g processor. The example application measures the memory access speed of different memories connected to the processor, such as TCM, on-chip memory and external memory interface (EMIF). In addition to that, the application showcases the speedup between cached and un-cached memories.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3.1/agf014eb-si-devkit/niosv_g/tcm_mem_test/img/niosv_tcm.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/24.3.1/agf014eb-si-devkit/niosv_g/tcm_mem_test",
            "downloadUrl": "agilex7_tcm_design.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/230255618",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Iperf Design Example on Nios® V/m Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.0 Pro",
            "devkit": "Agilex 7 FPGA F-Series Transceiver-SoC Development Kit P-Tile and E-Tile DK-SI-AGF014EB",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/m Processor-based Iperf example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>Perf 2 is a benchmarking tool for measuring performance between two systems, and it can be used as a server or a client.</p><p>An iPerf server receives an iPerf request sent over a TCP/IP connection from any iPerf clients and runs the iPerf test according to the provided arguments. </p><p>Each test reports the bandwidth, loss, and other parameters.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3/niosv_m/agilex7_sisoc_iperf/img/agilex7_iperf.png\"/></p>",
            "category": "Web Server",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/24.3/niosv_m/agilex7_sisoc_iperf",
            "downloadUrl": "agilex7_sisoc_iperf.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/220575358",
            "Q_GITHUB_RELEASE": "24.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 7 FPGA - Simple Socket Server (SSS) Design Example on Nios® V/m Processor",
            "source": "GitHub",
            "family": "Agilex 7",
            "quartus_version": "24.3.0 Pro",
            "devkit": "Agilex 7 FPGA F-Series Transceiver-SoC Development Kit P-Tile and E-Tile DK-SI-AGF014EB",
            "device_part": "AGFB014R24B2E2V",
            "description": "Nios® V/m Processor-based SSS example design on the Agilex® 7 FPGA.",
            "rich_description": "<p>This example design demonstrates communication with a telnet client on a development host PC.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/24.3/niosv_m/agilex7_sisoc_sss/img/agilex7_sss.png\"/></p>",
            "category": "Web Server",
            "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/24.3/niosv_m/agilex7_sisoc_sss/",
            "downloadUrl": "agilex7_sisoc_sss.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/220575932",
            "Q_GITHUB_RELEASE": "24.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA ESeries 065B Premium Development Kit DKA5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 5 FPGA.",
            "rich_description": "<p>This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) DK-A5E065BB32AES1. </p><p><img alt=\"image\" src=\"https://github.com/intel-innersource/applications.fpga.niosv-example-designs.niosv-example-designs/blob/rel/25.3.1/a5e065b-prem-devkit/niosv_g/tinyml_liteRT/img/block_diagram.png\"/></p>",
            "category": "AI",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.3.1-v1.0/agilex5_niosv_g_tinyml_liteRT.zip",
            "downloadUrl": "agilex5_niosv_g_tinyml_liteRT.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/intel-innersource/applications.fpga.niosv-example-designs.niosv-example-designs/blob/rel/25.3.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/img/block_diagram.png"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/349981796",
            "Q_GITHUB_RELEASE": "25.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Full Feature Golden Hardware Reference Design (GHRD) Overview",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This design demonstrates the Full Feature Golden Hardware Reference Design (GHRD) that showcases the connectivity to multiple peripherals with Nios® V/m processor as the core on Agilex™ 5 FPGA E-Series 065B Premium Development Kit.",
            "rich_description": "<p>This example design includes a Nios® V/m processor connected to various on-board peripherals.\nThe objective of the design is to accomplish data transfer between the processor and soft IP peripherals. Each peripheral has a dedicated application which demonstrates it's basic use.</p><p><img alt=\"Block Diagram\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.3.1/niosv_m/niosv_m_full_feature_ghrd/img/full_feature_ghrd_block_design.png\"/></p>",
            "category": "GHRD",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.1.1-v1.0/agilex5_niosv_m_full_feature_ghrd.zip",
            "downloadUrl": "agilex5_niosv_m_full_feature_ghrd.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.1/niosv_m/niosv_m_full_feature_ghrd/docs/NiosV_m_Processor_full_feature_ghrd_on_Agilex_5_FPGA.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/350402266",
            "Q_GITHUB_RELEASE": "25.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/g Ping Design",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This design demonstrates the Ping application on a Nios® V/g processor using the Triple Speed Ethernet IP for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.",
            "rich_description": "<p>The example design demonstrates ping application. The Nios V/g acts as the core. The Triple Speed Ethernet (TSE) IP is configured in RGMII mode and connectes to the onboard 88E1512 PHY via RGMII interface. </p><p>The design has 2 MSGDMA IPs configured in Memory Mapped to Stream (MM2S) mode for Transmission and Stream to Memory Mapped (S2MM) mode for Reception.</p><p>To test the application, connect the RGMII Interface of the Agilex 5 Development Kit to the Link Partner using RJ-45 cable.</p><p>Ensure that the IP addresses are modified accordingly in the application code under the following location - sw/app_freertos/main.c</p><p>Once the application binaries are downloaded (See section 3.d below for the steps), the board starts pinging the link partner automatically.</p><p>Observe the Ping Request and Response prints on the terminal.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.3.1/niosv_g/niosv_g_webserver_ping/img/web_server_block_diagram.png\"/></p><h2>Fix for the packet drop issue observed in 25.3</h2><p>To fix the packet drops that were observed when the board and link partner ping each other in 25.3, make the changes described below:</p><p>File to be modified- msgdma_driver.c</p><p>File path - sw/bsp_freertos/FreeRTOS_TCP_IP/source/portable/NetworkInterface/AlteraTSE/msgdma_driver.c</p><p>Function to be modified- msgdma_InitRxDescList()</p><p>Modification- Add the highlighted lines as shown in the figure below</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.3.1/niosv_g/niosv_g_webserver_ping/img/msgdma_driver_update.png\"/></p><p>Note: The default BSP generated using niosv-bsp command will not have the above changes. Ensure these changes are done manually.</p><p>Once done, run niosv-app, cmake and make commands as mentioned in section 3.c below.</p>",
            "category": "Networking",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.3.1-v1.0/agilex5_niosv_g_webserver_ping.zip",
            "downloadUrl": "agilex5_niosv_g_webserver_ping.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.1/niosv_g/niosv_g_webserver_ping/docs/NiosV_g_Processor_ping_on_Agilex_5_FPGA.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/350434978",
            "Q_GITHUB_RELEASE": "25.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/c Helloworld OCM Memory Test Design",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.3.0",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "rich_description": "<p>Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.3.0/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3.0/niosv_c/niosv_c_helloworld_ocm_mem_test",
            "downloadUrl": "agilex5_niosv_c_helloworld_ocm_mem_test.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3.0/niosv_m/niosv_m_dma_ocm/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/303625312",
            "Q_GITHUB_RELEASE": "25.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/g Ping Design",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.3.0",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This design demonstrates the Ping application on a Nios® V/g processor using the Triple Speed Ethernet IP for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.",
            "rich_description": "<p>The example design demonstrates ping application. The Nios V/g acts as the core. The Triple Speed Ethernet (TSE) IP is configured in RGMII mode and connectes to the onboard 88E1512 PHY via RGMII interface. \nThe design has 2 MSGDMA IPs configured in Memory Mapped to Stream (MM2S) mode for Transmission and Stream to Memory Mapped (S2MM) mode for Reception.</p><p>To test the application, connect the RGMII Interface of the Agilex 5 Development Kit to the Link Partner using RJ-45 cable.\nEnsure that the IP addresses are modified accordingly in the application code under the following location - sw/app_freertos/main.c\nOnce the application binaries are downloaded (See section 3.d below for the steps), the board starts pinging the link partner automatically.\nObserve the Ping Request and Response prints on the terminal.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.3.0/niosv_g/niosv_g_webserver_ping/img/web_server_block_diagram.png\"/></p>",
            "category": "Networking",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_g/niosv_g_webserver_ping",
            "downloadUrl": "agilex5_niosv_g_webserver_ping.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_g/niosv_g_webserver_ping/docs/NiosV_g_Processor_ping_on_Agilex_5_FPGA.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/307673766",
            "Q_GITHUB_RELEASE": "25.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.3.0",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 5 FPGA.",
            "rich_description": "<p>This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) DK-A5E065BB32AES1. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.3.0/niosv_g/tinyml_liteRT/img/block_diagram.png\"/></p>",
            "category": "AI",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.3.0/niosv_g/tinyml_liteRT",
            "downloadUrl": "agilex5_niosv_g_tinyml_liteRT.zip",
            "documentations": [
                {
                    "title": "Design Document",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.3.0/niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_5_FPGA.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/303624448",
            "Q_GITHUB_RELEASE": "25.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Nios® V/m Full Feature Golden Hardware Reference Design (GHRD)",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.3.0",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This design demonstrates the Full Feature Golden Hardware Reference Design (GHRD) that showcases the connectivity to multiple peripherals with Nios® V/m processor as the core on Agilex™ 5 FPGA E-Series 065B Premium Development Kit.",
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            "family": "Agilex 5",
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            "quartus_version": "25.1.1",
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            "quartus_version": "25.1.0",
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            "quartus_version": "25.1.0",
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            "family": "Agilex 5",
            "quartus_version": "25.1.0",
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            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "24.3.1 Pro",
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            "quartus_version": "24.3.1 Pro",
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            "quartus_version": "24.3.1 Pro",
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            "downloadUrl": "agilex5_niosv_m_helloworld_ocm.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/227780100",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 FPGA- Nios® V/m Processor PIO LED Toggle Design",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "24.3.1 Pro",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This design demonstrates the transaction between the Nios® V processor and the PIO core.",
            "rich_description": "<p>The PIO core is configured for output ports only and the outputs are connected to the LED on the development kit. The application, which runs atop this design, toggles these output registers of the PIO core. The application writes and reads back the content from the IP location. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/24.3.1/niosv_m/niosv_m_pio/img/pio.png\"/></p>",
            "category": "PIO LED Toggle",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/24.3.1/niosv_m/niosv_m_pio/",
            "downloadUrl": "agilex5_niosv_m_pio.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/227780104",
            "Q_GITHUB_RELEASE": "24.3.1-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 FPGA - Hello World on Nios® V/g Processor Design Example",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "24.3.0 Pro",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Nios® V/g Processor-based Helloworld example design on the Agilex® 5 FPGA.",
            "rich_description": "<p>Nios® V/g Processor-based Helloworld example design on the Agilex® 5 FPGA E-Series 065B Premium Development Kit (ES1) DKA5E065BB32AES1</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/24.3/niosv_g/niosv_g_helloworld/img/hello_world.png\"/></p>",
            "category": "Helloworld",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/24.3/niosv_g/niosv_g_helloworld",
            "downloadUrl": "agilex5_niosv_g_helloworld.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/220628301",
            "Q_GITHUB_RELEASE": "24.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 FPGA - Hello World and OCM test Design Example on Nios® V/c Processor",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "24.3.0 Pro",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Nios® V/c Processor-based Helloworld example design on the Agilex® 5 FPGA.",
            "rich_description": "<p>Nios® V/c processor-based Helloworld and OCM memory test example design on the Agilex® 5 FPGA</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/24.3/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png\"/></p>",
            "category": "Helloworld",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/24.3/niosv_c/niosv_c_helloworld_ocm_mem_test",
            "downloadUrl": "agilex5_niosv_c_helloworld_ocm_mem_test.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/220623935",
            "Q_GITHUB_RELEASE": "24.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 FPGA - Hello World on Nios® V/g Processor Design Example",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "24.3.0 Pro",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Nios® V/g Processor-based OCM test example design on the Agilex® 5 FPGA.",
            "rich_description": "<p>Nios® V/g Processor-based OCM test example design on the Agilex® 5 FPGA E-Series 065B Premium Development Kit (ES1) DKA5E065BB32AES1</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/24.3/niosv_g/niosv_g_ocm_mem_test/img/hello_world_ocm.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/24.3/niosv_g/niosv_g_ocm_mem_test/",
            "downloadUrl": "agilex5_niosv_g_ocm_mem_test.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/220622642",
            "Q_GITHUB_RELEASE": "24.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 FPGA - Nios® V/m Processor with DMA and OCM Design Example",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "24.3.0 Pro",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This design demonstrates the transaction between the Nios® V/m processor with DMA and OCM core for the Agilex 5 FPGA E-Series 065B Premium Development Kit (ES1)DK-A5E065BB32AES1.",
            "rich_description": "<p>This example design includes a Nios® V processor connected to the DMA, On Chip RAM-II and JTAG UART IP. \nThe objective of the design is to accomplish a data transfer between the 2 On Chip RAM-II using a DMA (MSGDMA) IP. \nDMA facilitates the data transfer which is then read back by the processor.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/24.3/niosv_m/niosv_m_dma_ocm/img/dma_ocm.png\"/></p>",
            "category": "Memory",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/24.3/niosv_m/niosv_m_dma_ocm",
            "downloadUrl": "agilex5_niosv_m_dma_ocm.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/220622773",
            "Q_GITHUB_RELEASE": "24.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 FPGA - Nios® V/m Processor Helloworld and OCM test design",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "24.3.0 Pro",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Nios® V/m Processor-based Helloworld and OCM memory test example design on the Agilex 5 FPGA.",
            "rich_description": "<p>Nios® V/m Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit (ES1) DK-A5E065BB32AES1. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/24.3/niosv_m/niosv_m_helloworld_ocm_mem_test/img/hello_world_ocm.png\"/></p>",
            "category": "Helloworld",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/24.3/niosv_m/niosv_m_helloworld_ocm_mem_test",
            "downloadUrl": "agilex5_niosv_m_helloworld_ocm.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/220622815",
            "Q_GITHUB_RELEASE": "24.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 FPGA- Nios® V/m Processor PIO LED Toggle Design",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "24.3.0 Pro",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This design demonstrates the transaction between the Nios® V processor and the PIO core.",
            "rich_description": "<p>The PIO core is configured for output ports only and the outputs are connected to the LED on the development kit. The application, which runs atop this design, toggles these output registers of the PIO core. The application writes and reads back the content from the IP location. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/24.3/niosv_m/niosv_m_pio/img/pio.png\"/></p>",
            "category": "PIO LED Toggle",
            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/24.3/niosv_m/niosv_m_pio/",
            "downloadUrl": "agilex5_niosv_m_pio.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/220617185",
            "Q_GITHUB_RELEASE": "24.3.0-v1.0",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "HPS with Multi-rate Ethernet PHY System Example Design for Agilex 5 Modular Development Kit\"",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This design which is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) is part of the Golden System Reference Design (GSRD), adds a new subsystem with Multi-rate Ethernet Phy which covers all Hardware features specific to TSN-SGMII XCVR.",
            "rich_description": "<p>This design demonstrate 3x2.5G ports to HPS\n- Enable the Data path between HPS &lt;-&gt; XGMAC &lt;-&gt;MR PHY (Direct mode) &lt;-&gt; Marvell PHY running at 2.5G rate.\n- This ED showcases 2.5G data rate.\n- Enable the Deterministic Latency (DL) feature of MR PHY IP which precisely determines the delay between the PCS elastic FIFO (EFIFO) and the PMA pins for TSN usecases. Also enable the CSR interface with HPS Light weight bridge to convey these delays (Soft PCS, Hard PCS   and PMA delays) for both RX and TX directions.\n- GMII (8-bit) interface for TSN enabled ethernet data transfers to and from XGMAC to external PHY. Tranceiever’s reference clocks are used to derive the required frequency for running this parallel interface as the expectation is to have zero ppm difference between these clocks.  </p><p><img alt=\"Agilex™ 5 3xMulti-rate Ethernet PHY block diagram\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5-ed-tsn-sgmii/rel/25.1.1/images/SM_TSN.png\"/></p><h2>Repository Structure</h2><ul>\n<li>Directory Structure used in this example design\n <code>bash\n    |--- doc  \n    |--- src\n    |   |--- hw \n    |   |--- sw</code></li>\n</ul>",
            "category": "HPS, Ethernet",
            "url": "https://github.com/altera-fpga/agilex5-ed-tsn-sgmii",
            "downloadUrl": "source_code.zip",
            "documentations": [],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5-ed-tsn-sgmii/releases/assets/305555276",
            "Q_GITHUB_RELEASE": "25.1.1-1",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "Agilex 5 System On Chip (SoC) FPGA Example Design with Multi-rate Ethernet PHY Intel® FPGA IP Core",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "24.3.0 Pro Edition",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), adds a new subsystem with Multi-rate Ethernet Phy which covers all Hardware features specific to Config-3 TSN.",
            "rich_description": "<p>This design is based on base GHRD with the following feature additions: \n- Enable the Data path between HPS &lt;-&gt; XGMAC &lt;-&gt;MR PHY (Direct mode) &lt;-&gt; Marvell PHY running at 2.5G rate.\n- This ED showcases 2.5G data rate.\n- Enable the Deterministic Latency (DL) feature of MR PHY IP which precisely determines the delay between the PCS elastic FIFO (EFIFO) and the PMA pins for TSN usecases. Also enable the CSR interface with HPS Light weight bridge to convey these delays (Soft PCS, Hard PCS   and PMA delays) for both RX and TX directions.\n- GMII (8-bit) interface for TSN enabled ethernet data transfers to and from XGMAC to external PHY. Tranceiever’s reference clocks are used to derive the required frequency for running this parallel interface as the expectation is to have zero ppm difference between these clocks.  </p><h2>Repository Structure</h2><ul>\n<li>Directory Structure used in this example design\n <code>bash\n    |--- doc  \n    |--- src\n    |   |--- hw \n    |   |--- sw</code></li>\n</ul>",
            "category": "Unknown",
            "url": "https://github.com/altera-fpga/agilex5-ed-tsn-sgmii",
            "downloadUrl": "source_code.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5-ed-tsn-sgmii/releases/assets/209677369",
            "Q_GITHUB_RELEASE": "24.3-1",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "HPS Baseline System Example Design for Modular Development Kit for Agilex 5 FPGA E-Series 065B Modular Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Modular Development Kit.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.\n\n</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\\nRefer to the <a href='\\\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/\\\"'>Agilex 5 E-Series Modular Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.\n\n</p><h2>Baseline feature\n\n</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n<ul><li>Hard Processor System (HPS) enablement and configuration\n<ul><li>Enable dual core Arm Cortex-A76 processor\n</li><li>Enable dual core Arm Cortex-A55 processor\n</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I2C, JTAG, UART, and GPIO)\n</li><li>HPS Clock and Reset\n</li><li>HPS FPGA Bridge and Interrupt\n</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n</li><li>System integration with FPGA IPs\n<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs\n</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n</li><li>256KB of FPGA On-Chip Memory</li></ul></li></li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-modular-devkit-som-legacy-baseline.zip",
            "documentations": [
                {
                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Modular Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/"
                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Modular Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-modular-devkit-som/legacy-baseline/README.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/339305876",
            "Q_GITHUB_RELEASE": "QPDS25.3.1_REL_GSRD_PR",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "HPS Baseline-A55 System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "HPS Baseline-A55 System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.\n\n</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\\n\nRefer to the <a href='\\\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\\\"'>Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.\n\n</p><p>The design uses HPS First configuration mode and boots from Arm Cortex-A55 core 0 processor.\n\n</p><h2>Baseline-A55 feature\n</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n<ul><li>Hard Processor System (HPS) enablement and configuration\n<ul><li>Enable dual core Arm Cortex-A76 processor\n</li><li>Enable dual core Arm Cortex-A55 processor\n</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)\n</li><li>HPS Clock and Reset\n</li><li>HPS FPGA Bridge and Interrupt\n</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n</li><li>System integration with FPGA IPs\n<ul><li>Core subsystem that consists of NiosV subsystem, 256KB of FPGA On-Chip Memory, System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs.\n</li><li>NiosV subsystem that consists of JTAG Avalon Master Bridge IP and Address Span Extender IP to allow System-Console debug activity and FPGA content access through JTAG.\n\n</li></ul></li></li></ul></p><h3>USB modes\n</h3><p>This design supports USB 3.1 in both host and device mode.<br/>Once power up, the USB mode will remain and cannot be changed during runtime.\n\n</p><p>The linux device tree (dts) needs to be configured.<br/>The dts can be set with \"dr_mode\".\n\n</p><table border='\\\"1\\\"' cellpadding='\\\"10\\\"'><tr><th>dr_mode value</th><th>Equivalent USB mode</th></tr>\n<tr><td>host</td><td>Host</td></tr>\n<tr><td>peripheral</td><td>Device</td></tr></table>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-oobe-baseline-a55.zip",
            "documentations": [
                {
                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/baseline-a55/README.md"
                }
            ],
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/339305877",
            "Q_GITHUB_RELEASE": "QPDS25.3.1_REL_GSRD_PR",
            "Q_VALIDATED": true
        },
        {
            "id": "-",
            "title": "HPS Baseline System Example Design with HPS Test Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS Test Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.\n\n</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\\nRefer to the <a href='\\\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\\\"'>Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.\n\n</p><p>The design uses HPS First configuration mode.\n\n</p><h2>Baseline feature\n\n</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n<ul><li>Hard Processor System (HPS) enablement and configuration\n<ul><li>Enable dual core Arm Cortex-A76 processor\n</li><li>Enable dual core Arm Cortex-A55 processor\n</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I3C, JTAG, UART, TRACE, and GPIO)\n</li><li>HPS Clock and Reset\n</li><li>HPS FPGA Bridge and Interrupt\n</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n</li><li>System integration with FPGA IPs\n<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs\n</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n</li><li>256KB of FPGA On-Chip Memory</li></ul></li></li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-debug2-legacy-baseline.zip",
            "documentations": [
                {
                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-debug2/legacy-baseline/README.md"
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            "id": "-",
            "title": "HPS Baseline-A76 System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "HPS Baseline-A76 System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.\n\n</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\\n\nRefer to the <a href='\\\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\\\"'>Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.\n\n</p><p>The design uses HPS First configuration mode and boots from Arm Cortex-A76 core 2 processor.\n\n</p><h2>Baseline-A76 feature\n</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n<ul><li>Hard Processor System (HPS) enablement and configuration\n<ul><li>Enable dual core Arm Cortex-A76 processor\n</li><li>Enable dual core Arm Cortex-A55 processor\n</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)\n</li><li>HPS Clock and Reset\n</li><li>HPS FPGA Bridge and Interrupt\n</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n</li><li>System integration with FPGA IPs\n<ul><li>Core subsystem that consists of NiosV subsystem, 256KB of FPGA On-Chip Memory, System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs.\n</li><li>NiosV subsystem that consists of JTAG Avalon Master Bridge IP and Address Span Extender IP to allow System-Console debug activity and FPGA content access through JTAG.\n\n</li></ul></li></li></ul></p><h3>USB modes\n</h3><p>This design supports USB 3.1 in both host and device mode.<br/>Once power up, the USB mode will remain and cannot be changed during runtime.\n\n</p><p>The linux device tree (dts) needs to be configured.<br/>The dts can be set with \"dr_mode\".\n\n</p><table border='\\\"1\\\"' cellpadding='\\\"10\\\"'><tr><th>dr_mode value</th><th>Equivalent USB mode</th></tr>\n<tr><td>host</td><td>Host</td></tr>\n<tr><td>peripheral</td><td>Device</td></tr></table>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-oobe-baseline-a76.zip",
            "documentations": [
                {
                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/baseline-a76/README.md"
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            "id": "-",
            "title": "HPS Baseline System Example Design with eMMC Boot for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS NAND Board. This board also offers eMMC.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.\n\n</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\\nRefer to the <a href='\\\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\\\"'>Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.\n\n</p><p>The design uses HPS First configuration mode.\n\n</p><h2>Baseline feature\n</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n<ul><li>Hard Processor System (HPS) enablement and configuration\n<ul><li>Enable dual core Arm Cortex-A76 processor\n</li><li>Enable dual core Arm Cortex-A55 processor\n</li><li>Hard Processor System enablement and configuration\n</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I2C, I3C, UART, TRACE, and GPIO)\n</li><li>HPS Clock and Reset\n</li><li>HPS FPGA Bridge and Interrupt\n</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n</li><li>System integration with FPGA IPs\n<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs\n</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n</li><li>256KB of FPGA On-Chip Memory</li></ul></li></li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-emmc-legacy-baseline.zip",
            "documentations": [
                {
                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
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                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-emmc/legacy-baseline/README.md"
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            "id": "-",
            "title": "HPS Time-Sensitive Network (RGMII from HVIO) System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Time-Sensitive Networking (TSN): PHY configuration 2 (RGMII from FPGA HVIO) Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.\n\n</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\\nRefer to the <a href='\\\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\\\"'>Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.\n\n</p><p>The design uses HPS First configuration mode.\n\n</p><h2>Baseline feature\n\n</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n<ul><li>Hard Processor System (HPS) enablement and configuration\n<ul><li>Enable dual core Arm Cortex-A76 processor\n</li><li>Enable dual core Arm Cortex-A55 processor\n</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)\n</li><li>HPS Clock and Reset\n</li><li>HPS FPGA Bridge and Interrupt\n</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n</li><li>System integration with FPGA IPs\n<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs\n</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n</li><li>256KB of FPGA On-Chip Memory\n\n</li></ul></li></li></ul></p><h3>USB modes\n</h3><p>This design supports USB 3.1 in both host and device mode.<br/>Once power up, the USB mode will remain and cannot be changed during runtime.\n\n</p><p>The linux device tree (dts) needs to be configured.<br/>The dts can be set with \"dr_mode\".\n\n</p><table border='\\\"1\\\"' cellpadding='\\\"10\\\"'><tr><th>dr_mode value</th><th>Equivalent USB mode\n</th></tr><tr><td>host</td><td>Host</td></tr>\n<tr><td>peripheral</td><td>Device</td></tr></table><h2>Advanced feature\n</h2><p>FPGA RGMII subsystem that consists of GMII-to-RGMII conversion for HPS XGMAC into FPGA IO connection</p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-oobe-legacy-tsn-cfg2.zip",
            "documentations": [
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                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
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                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/legacy-tsn-cfg2/README.md"
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            "id": "-",
            "title": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 013B Development Kit",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.3.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 013B Development Kit DK-A5E013BM16AEA",
            "device_part": "A5ED013BM16AE4SCS",
            "description": "This is the baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 013B Development Kit.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.\n\n</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\n\n</p><p>The design uses HPS First configuration mode.\n\n</p><h2>Baseline feature\n\n</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n<ul><li>Hard Processor System (HPS) enablement and configuration\n<ul><li>Enable dual core Arm Cortex-A55 processor\n</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)\n</li><li>HPS Clock and Reset\n</li><li>HPS FPGA Bridge and Interrupt\n</li></ul><li>HPS EMIF configuration (Inline ECC for LPDDR4 is enabled by default)\n</li><li>System integration with FPGA IPs\n<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling PushButton and LEDs.\n</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n</li><li>256KB of FPGA On-Chip Memory</li></ul></li></li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed013-devkit-oobe-legacy-baseline.zip",
            "documentations": [
                {
                    "title": "GHRD README for the Agilex 5 FPGA E-Series 013B Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed013-devkit-oobe/legacy-baseline/README.md"
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        {
            "id": "-",
            "title": "HPS Baseline System Example Design for Modular Development Kit for Agilex 5 FPGA E-Series 065B Modular Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Modular Development Kit.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/\">Agilex 5 E-Series Modular Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration<ul><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I2C, JTAG, UART, and GPIO)  - HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-modular-devkit-som-legacy-baseline.zip",
            "documentations": [
                {
                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Modular Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/"
                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Modular Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-modular-devkit-som/legacy-baseline/README.md"
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        {
            "id": "-",
            "title": "HPS Baseline System Example Design with eMMC Boot for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS NAND Board. This board also offers eMMC.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration<ul><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>Hard Processor System enablement and configuration</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I2C, I3C, UART, TRACE, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
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                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
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                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
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            "id": "-",
            "title": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 013B Development Kit",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.3",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 013B Development Kit DK-A5E013BM16AEA",
            "device_part": "A5ED013BM16AE4SCS",
            "description": "This is the baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 013B Development Kit.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration<ul><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li></ul><li>HPS EMIF configuration (Inline ECC for LPDDR4 is enabled by default)</li><li>System integration with FPGA IPs<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling PushButton and LEDs.</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></li></ul></p>",
            "category": "HPS",
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            "id": "-",
            "title": "HPS Legacy Baseline System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "This is the legacy baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Legacy Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration<ul><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></li></ul></p><h3>USB modes</h3><p>This design supports USB 3.1 in both host and device mode.\nOnce power up, the USB mode will remain and cannot be changed during runtime.</p><p>The linux device tree (dts) needs to be configured.\nThe dts can be set with \"dr_mode\".</p><table border=\"1\" cellpadding=\"10\" ><tr><th>dr_mode value</th><th>Equivalent USB mode</th></tr><tr><td>host</td><td>Host</td></tr><tr><td>peripheral</td><td>Device</td></tr></table>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-oobe-legacy-baseline.zip",
            "documentations": [
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                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
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                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/legacy-baseline/README.md"
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            "id": "-",
            "title": "HPS Baseline System Example Design with HPS Test Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS Test Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration<ul><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I3C, JTAG, UART, TRACE, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
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                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-debug2/legacy-baseline/README.md"
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            "id": "-",
            "title": "HPS Time-Sensitive Network (RGMII from HVIO) System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Time-Sensitive Networking (TSN): PHY configuration 2 (RGMII from FPGA HVIO) Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration<ul><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs<ul><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></li></ul></p><h3>USB modes</h3><p>This design supports USB 3.1 in both host and device mode.\nOnce power up, the USB mode will remain and cannot be changed during runtime.</p><p>The linux device tree (dts) needs to be configured.\nThe dts can be set with \"dr_mode\".</p><table border=\"1\" cellpadding=\"10\"><tr><th>dr_mode value</th><th>Equivalent USB mode</th></tr><tr><td>host</td><td>Host</td></tr><tr><td>peripheral</td><td>Device</td></tr></table><h2>Advanced feature</h2><p>FPGA RGMII subsystem that consists of GMII-to-RGMII conversion for HPS XGMAC into FPGA IO connection</p>",
            "category": "HPS",
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                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/legacy-tsn-cfg2/README.md"
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            "id": "-",
            "title": "HPS Baseline System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.3",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Altera Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration<ul><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li></ul><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs<ul><li>Core subsystem that consists of NiosV subsystem, 256KB of FPGA On-Chip Memory, System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs.</li><li>NiosV subsystem that consists of JTAG Avalon Master Bridge IP and Address Span Extender IP to allow System-Console debug activity and FPGA content access through JTAG.</p><h3>USB modes</h3><p>This design supports USB 3.1 in both host and device mode.\nOnce power up, the USB mode will remain and cannot be changed during runtime.</p><p>The linux device tree (dts) needs to be configured.\nThe dts can be set with \"dr_mode\".</p><table border=\"1\" cellpadding=\"10\" ><tr><th>dr_mode value</th><th>Equivalent USB mode</th></tr><tr><td>host</td><td>Host</td></tr><tr><td>peripheral</td><td>Device</td></tr></table>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
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                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/baseline/README.md"
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        {
            "id": "-",
            "title": "HPS Baseline System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul><h3>USB modes</h3><p>This design supports USB 3.1 in both host and device mode.\nOnce power up, the USB mode will remain and cannot be changed during runtime.</p><p>The linux device tree (dts) needs to be configured.\nThe dts can be set with \"dr_mode\".</p><table border=\"1\" cellpadding=\"10\" ><tr><th>dr_mode value</th><th>Equivalent USB mode</th></tr><tr><td>host</td><td>Host</td></tr><tr><td>peripheral</td><td>Device</td></tr></table>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
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                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/legacy-baseline/README.md"
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        {
            "id": "-",
            "title": "HPS Time-Sensitive Network (RGMII from HVIO) System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Time-Sensitive Networking (TSN): PHY configuration 2 (RGMII from FPGA HVIO) System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul><h3>USB modes</h3><p>This design supports USB 3.1 in both host and device mode.\nOnce power up, the USB mode will remain and cannot be changed during runtime.</p><p>The linux device tree (dts) needs to be configured.\nThe dts can be set with \"dr_mode\".</p><table border=\"1\" cellpadding=\"10\"><tr><th>dr_mode value</th><th>Equivalent USB mode</th></tr><tr><td>host</td><td>Host</td></tr><tr><td>peripheral</td><td>Device</td></tr></table><h2>Advanced feature</h2><p>FPGA RGMII subsystem that consists of GMII-to-RGMII conversion for HPS XGMAC into FPGA IO connection</p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
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                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
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                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/legacy-tsn-cfg2/README.md"
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            "id": "-",
            "title": "HPS Baseline System Example Design with eMMC Boot for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS NAND Board. This board also offers eMMC.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>Hard Processor System enablement and configuration</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I2C, I3C, UART, TRACE, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul>",
            "category": "HPS",
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                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
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            "id": "-",
            "title": "HPS Baseline System Example Design with HPS Test Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.1.1",
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            "device_part": "A5ED065BB32AE6SR0",
            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS Test Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I3C, JTAG, UART, TRACE, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul>",
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            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
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            "documentations": [
                {
                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
                },
                {
                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-debug2/legacy-baseline/README.md"
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            "id": "-",
            "title": "HPS Baseline System Example Design for Modular Development Kit for Agilex 5 FPGA E-Series 065B Modular Development Kit",
            "source": "GitHub",
            "family": "Agilex 5 E-Series",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Modular Development Kit.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/\">Agilex 5 E-Series Modular Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I2C, JTAG, UART, and GPIO)  - HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-modular-devkit-som-legacy-baseline.zip",
            "documentations": [
                {
                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Modular Development Kit",
                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/"
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                {
                    "title": "GHRD README for the Agilex 5 E-Series Modular Development Kit",
                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-modular-devkit-som/legacy-baseline/README.md"
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        {
            "id": "-",
            "title": "HPS Time-Sensitive Network (RGMII from HVIO) System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.1",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Time-Sensitive Networking (TSN): PHY configuration 2 (RGMII from FPGA HVIO) System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out-of-Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li> Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li> Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul><h2>Advanced feature</h2><ul><li>FPGA RGMII subsystem that consists of GMII-to-RGMII conversion for HPS XGMAC into FPGA IO connection</li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-oobe-legacy-tsn-cfg2.zip",
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            "id": "-",
            "title": "HPS Baseline System Example Design for Modular Development Kit for Agilex 5 FPGA E-Series 065B Modular Development Kit",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.1",
            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Modular Development Kit",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/\">Agilex 5 E-Series Modular Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li> Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I2C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset<li></li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration<li></li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-modular-devkit-som-legacy-baseline.zip",
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            "id": "-",
            "title": "HPS Baseline System Example Design with NAND Boot for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.1",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS NAND Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.</li><li>Refer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (NAND, EMAC, SPI, MDIO, I2C, I3C, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-nand-legacy-baseline.zip",
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            "Q_GITHUB_RELEASE": "QPDS25.1_REL_GSRD_PR",
            "Q_VALIDATED": true
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        {
            "id": "-",
            "title": "HPS Baseline System Example Design with eMMC Boot for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.1",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS NAND Board. This board also offers eMMC.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration</li><li> Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>Hard Processor System enablement and configuration</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I2C, I3C, UART, TRACE, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-emmc-legacy-baseline.zip",
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            "Q_GITHUB_RELEASE": "QPDS25.1_REL_GSRD_PR",
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        {
            "id": "-",
            "title": "HPS Baseline System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.1",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED013BB32AE5S",
            "description": "This is the baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-oobe-legacy-baseline.zip",
            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/245602315",
            "Q_GITHUB_RELEASE": "QPDS25.1_REL_GSRD_PR",
            "Q_VALIDATED": true
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        {
            "id": "-",
            "title": "HPS Baseline System Example Design with HPS Test Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
            "source": "GitHub",
            "family": "Agilex 5",
            "quartus_version": "25.1",
            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
            "device_part": "A5ED065BB32AE6SR0",
            "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS Test Board.",
            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:<ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I3C, JTAG, UART, TRACE, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul></p>",
            "category": "HPS",
            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
            "downloadUrl": "a5ed065es-premium-devkit-debug2-legacy-baseline.zip",
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            "Q_GITHUB_RELEASE": "QPDS25.1_REL_GSRD_PR",
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        {
            "id": "-",
            "title": "Agilex 3 FPGA - Nios® V/m Baseline Golden Hardware Reference Design (GHRD)",
            "source": "GitHub",
            "family": "Agilex 3",
            "quartus_version": "25.1.1",
            "patch_number": "Unknown",
            "devkit": "Agilex™ 3 FPGA C-Series 135 (M16A) A3CW135BM16AE6S",
            "device_part": "A3CW135BM16AE6S",
            "description": "This design demonstrates the Baseline Golden Hardware Reference Design (GHRD) for a Nios® V/m processor with basic bare minimum peripherals required for any application execution",
            "rich_description": "<p>This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel- IO and System ID peripheral core. </p><p>The objective of the design is to accomplish data transfer between the processor and on chip memory. </p><h6>Note: The sof (binary) generation is not supported for Agilex 3 devices starting from Quartus 25.1.1 version. Hence, you will observe \"sof not generated\" critical warning while compiling this design.</h6><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex3e-nios-ed/rel/25.1.1/niosv_m/baseline_ghrd/img/baseline_ghrd_block_design.png\"/></p>",
            "category": "GHRD",
            "url": "https://github.com/altera-fpga/agilex3e-nios-ed/blob/rel/25.1.1/niosv_m/baseline_ghrd/docs/Nios_Vm_Processor_Baseline_GHRD_Design_on_Agilex_3_FPGA.md",
            "downloadUrl": "agilex3_niosv_m_baseline_ghrd.zip",
            "documentations": [],
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            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
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        },
        {
            "id": "-",
            "title": "Agilex 3 FPGA - Nios® V/m Baseline Golden Hardware Reference Design (GHRD)",
            "source": "GitHub",
            "family": "Agilex 3",
            "quartus_version": "25.1.0",
            "devkit": "Agilex™ 3 FPGA C-Series 135 (M16A) A3CW135BM16AE6S",
            "device_part": "A3CW135BM16AE6S",
            "description": "This design demonstrates the Baseline Golden Hardware Reference Design (GHRD) for a Nios® V/m processor with basic bare minimum peripherals required for any application execution",
            "rich_description": "<p>This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel- IO and System ID peripheral core. </p><p>The objective of the design is to accomplish data transfer between the processor and on chip memory. </p><h6>Note: The sof (binary) generation is not supported for Agilex 3 devices on Quartus 25.1 version. Hence, you will observe \"sof not generated\" critical warning while compiling this design.</h6><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex3e-nios-ed/rel/25.1.0/niosv_m/baseline_ghrd/img/baseline_ghrd_block_design.png\"/></p>",
            "category": "GHRD",
            "url": "https://github.com/altera-fpga/agilex3e-nios-ed/releases/download/25.1-v1.0/agilex3_niosv_m_baseline_ghrd.zip",
            "downloadUrl": "agilex3_niosv_m_baseline_ghrd.zip",
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    "force_always_regenerate": []
}