@@ -414,6 +414,16 @@ class FooRegister(Register, access="r"):
414414 self .assertEqual (reg .element .access , Element .Access .R )
415415 self .assertEqual (reg .element .width , 2 )
416416
417+ def test_fields_single (self ):
418+ reg = Register (Field (action .R , unsigned (1 )), access = "r" )
419+
420+ field_r_u1 = Field (action .R , unsigned (1 )).create ()
421+
422+ self .assertTrue (_compatible_fields (reg .f , field_r_u1 ))
423+
424+ self .assertEqual (reg .element .access , Element .Access .R )
425+ self .assertEqual (reg .element .width , 1 )
426+
417427 def test_wrong_access (self ):
418428 with self .assertRaisesRegex (ValueError , r"'foo' is not a valid Element.Access" ):
419429 Register ({"a" : Field (action .R , unsigned (1 ))}, access = "foo" )
@@ -450,7 +460,7 @@ def test_wrong_fields(self):
450460 class FooRegister (Register , access = "w" ):
451461 pass
452462 with self .assertRaisesRegex (TypeError ,
453- r"Field collection must be a dict or a list , not 'foo'" ):
463+ r"Field collection must be a dict, list, or Field , not 'foo'" ):
454464 FooRegister (fields = "foo" )
455465
456466 def test_annotations_conflict (self ):
@@ -497,6 +507,12 @@ class FooRegister(Register, access="rw"):
497507 (("e" , 1 ), reg .f .e [1 ]),
498508 ])
499509
510+ def test_iter_single (self ):
511+ reg = Register (Field (action .R , unsigned (1 )), access = "rw" )
512+ self .assertEqual (list (reg ), [
513+ ((), reg .f ),
514+ ])
515+
500516 def test_sim (self ):
501517 class FooRegister (Register , access = "rw" ):
502518 a : Field (action .R , unsigned (1 ))
@@ -629,6 +645,44 @@ def process():
629645 with sim .write_vcd (vcd_file = open ("test.vcd" , "w" )):
630646 sim .run ()
631647
648+ def test_sim_single (self ):
649+ dut = Register (Field (action .RW , unsigned (1 ), init = 1 ), access = "rw" )
650+
651+ def process ():
652+ # Check init values:
653+
654+ self .assertEqual ((yield dut .f .data ), 1 )
655+ self .assertEqual ((yield dut .f .port .r_data ), 1 )
656+
657+ # Initiator read:
658+
659+ yield dut .element .r_stb .eq (1 )
660+ yield Delay ()
661+
662+ self .assertEqual ((yield dut .f .port .r_stb ), 1 )
663+
664+ yield dut .element .r_stb .eq (0 )
665+
666+ # Initiator write:
667+
668+ yield dut .element .w_stb .eq (1 )
669+ yield dut .element .w_data .eq (0 )
670+ yield Delay ()
671+
672+ self .assertEqual ((yield dut .f .port .w_stb ), 1 )
673+ self .assertEqual ((yield dut .f .port .w_data ), 0 )
674+
675+ yield Tick ()
676+ yield dut .element .w_stb .eq (0 )
677+ yield Delay ()
678+
679+ self .assertEqual ((yield dut .f .data ), 0 )
680+
681+ sim = Simulator (dut )
682+ sim .add_clock (1e-6 )
683+ sim .add_testbench (process )
684+ with sim .write_vcd (vcd_file = open ("test.vcd" , "w" )):
685+ sim .run ()
632686
633687class _MockRegister (Register , access = "rw" ):
634688 def __init__ (self , name , width = 1 ):
0 commit comments