vendor.lattice_machxo_2_3l: fix sdl generation

Author: anuejn

nmigen/build/plat.py

@@ -392,6 +392,9 @@ def escape_one(match):
         def tcl_escape(string):
             return "{" + re.sub(r"([{}\\])", r"\\\1", string) + "}"
 
+        def tcl_escape_synplify(string):
+            return "{" + re.sub(r"([${}\\])", r"\\\1", string) + "}"
+
         def tcl_quote(string):
             return '"' + re.sub(r"([$[\\])", r"\\\1", string) + '"'
 

nmigen/vendor/lattice_machxo_2_3l.py

@@ -104,11 +104,12 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
         """,
         "{{name}}.sdc": r"""
+            set_hierarchy_separator {/}
             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
                 {% if port_signal is not none -%}
-                    create_clock -name {{port_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
+                    create_clock -name {{port_signal.name|tcl_escape_synplify}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape_synplify}}]
                 {% else -%}
-                    create_clock -name {{net_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
+                    create_clock -name {{net_signal.name|tcl_escape_synplify}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape_synplify}}]
                 {% endif %}
             {% endfor %}
             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}