ir: kill Fragment.ports

Author: wanda-phi

amaranth/back/rtlil.py

@@ -401,7 +401,7 @@ def emit_port_wires(self):
                                      port_id=port_id, port_kind=flow.value,
                                      name=name, attrs=self.value_attrs.get(value, {}))
             self.sigport_wires[name] = (wire, value)
-            if flow == _nir.ModuleNetFlow.OUTPUT:
+            if flow == _nir.ModuleNetFlow.Output:
                 continue
             # If we just emitted an input or inout port, it is driving the value.
             self.driven_sigports.add(name)
@@ -463,7 +463,7 @@ def emit_submodule_wires(self):
         for submodule_idx in self.module.submodules:
             submodule = self.netlist.modules[submodule_idx]
             for _name, (value, flow) in submodule.ports.items():
-                if flow == _nir.ModuleNetFlow.OUTPUT:
+                if flow == _nir.ModuleNetFlow.Output:
                     self.emit_driven_wire(value)
 
     def sigspec(self, *parts: '_nir.Net | Iterable[_nir.Net]'):
@@ -989,10 +989,10 @@ def is_empty(self, module_idx):
         return module_idx in self.empty
 
 
-def convert_fragment(fragment, name="top", *, emit_src=True):
+def convert_fragment(fragment, ports, name="top", *, emit_src=True, **kwargs):
     assert isinstance(fragment, _ir.Fragment)
     name_map = _ast.SignalDict()
-    netlist = _ir.build_netlist(fragment, name=name)
+    netlist = _ir.build_netlist(fragment, ports=ports, name=name, **kwargs)
     empty_checker = EmptyModuleChecker(netlist)
     builder = _Builder(emit_src=emit_src)
     for module_idx, module in enumerate(netlist.modules):
@@ -1011,14 +1011,18 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
     if (ports is None and
             hasattr(elaboratable, "signature") and
             isinstance(elaboratable.signature, wiring.Signature)):
-        ports = []
-        for _path, _member, value in elaboratable.signature.flatten(elaboratable):
+        ports = {}
+        for path, member, value in elaboratable.signature.flatten(elaboratable):
             if isinstance(value, _ast.ValueCastable):
                 value = value.as_value()
             if isinstance(value, _ast.Value):
-                ports.append(value)
+                if member.flow == wiring.In:
+                    dir = _ir.PortDirection.Input
+                else:
+                    dir = _ir.PortDirection.Output
+                ports["__".join(path)] = (value, dir)
     elif ports is None:
         raise TypeError("The `convert()` function requires a `ports=` argument")
-    fragment = _ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
-    il_text, _name_map = convert_fragment(fragment, name, emit_src=emit_src)
+    fragment = _ir.Fragment.get(elaboratable, platform)
+    il_text, _name_map = convert_fragment(fragment, ports, name, emit_src=emit_src, **kwargs)
     return il_text

amaranth/back/verilog.py

@@ -45,14 +45,18 @@ def convert(elaboratable, name="top", platform=None, *, ports=None, emit_src=Tru
     if (ports is None and
             hasattr(elaboratable, "signature") and
             isinstance(elaboratable.signature, wiring.Signature)):
-        ports = []
+        ports = {}
         for path, member, value in elaboratable.signature.flatten(elaboratable):
             if isinstance(value, _ast.ValueCastable):
                 value = value.as_value()
             if isinstance(value, _ast.Value):
-                ports.append(value)
+                if member.flow == wiring.In:
+                    dir = _ir.PortDirection.Input
+                else:
+                    dir = _ir.PortDirection.Output
+                ports["__".join(path)] = (value, dir)
     elif ports is None:
         raise TypeError("The `convert()` function requires a `ports=` argument")
-    fragment = _ir.Fragment.get(elaboratable, platform).prepare(ports=ports, **kwargs)
-    verilog_text, name_map = convert_fragment(fragment, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs)
+    fragment = _ir.Fragment.get(elaboratable, platform)
+    verilog_text, name_map = convert_fragment(fragment, ports, name, emit_src=emit_src, strip_internal_attrs=strip_internal_attrs, **kwargs)
     return verilog_text

amaranth/build/plat.py

@@ -163,11 +163,11 @@ def add_pin_fragment(pin, pin_fragment):
             if pin.dir == "io":
                 add_pin_fragment(pin, self.get_diff_input_output(pin, port, attrs, invert))
 
-        fragment._propagate_ports(ports=self.iter_ports(), all_undef_as_ports=False)
-        return self.toolchain_prepare(fragment, name, **kwargs)
+        ports = list(self.iter_ports())
+        return self.toolchain_prepare(fragment, ports, name, **kwargs)
 
     @abstractmethod
-    def toolchain_prepare(self, fragment, name, **kwargs):
+    def toolchain_prepare(self, fragment, ports, name, **kwargs):
         """
         Convert the ``fragment`` and constraints recorded in this :class:`Platform` into
         a :class:`BuildPlan`.
@@ -290,7 +290,7 @@ def iter_clock_constraints(self):
                 continue
             yield net_signal, port_signal, frequency
 
-    def toolchain_prepare(self, fragment, name, *, emit_src=True, **kwargs):
+    def toolchain_prepare(self, fragment, ports, name, *, emit_src=True, **kwargs):
         # Restrict the name of the design to a strict alphanumeric character set. Platforms will
         # interpolate the name of the design in many different contexts: filesystem paths, Python
         # scripts, Tcl scripts, ad-hoc constraint files, and so on. It is not practical to add
@@ -306,7 +306,8 @@ def toolchain_prepare(self, fragment, name, *, emit_src=True, **kwargs):
         # and to incorporate the Amaranth version into generated code.
         autogenerated = f"Automatically generated by Amaranth {__version__}. Do not edit."
 
-        rtlil_text, self._name_map = rtlil.convert_fragment(fragment, name=name, emit_src=emit_src)
+        rtlil_text, self._name_map = rtlil.convert_fragment(fragment, ports=ports, name=name,
+                                                            emit_src=emit_src)
 
         # Retrieve an override specified in either the environment or as a kwarg.
         # expected_type parameter is used to assert the type of kwargs, passing `None` will disable