[Codegen][ROCm] Add repro instructions for .rocmasm files (iree-org#21874)

The instructions will be printed inside the `.ll` files we already dump.

`.rocmasm` files can be generated using the `llc` command, making
bisecting llvm easier, since it doesn't require IREE to be in sync with
MLIR and LLVM.

Because `llc` is not built by default, you will have to run something
like `ninja llc` to use it from within the IREE build.

Author: kuhar

compiler/plugins/target/ROCM/ROCMTarget.cpp

@@ -711,29 +711,27 @@ class ROCMTargetBackend final : public TargetBackend {
                          ".linked.ll", *llvmModule);
       }
 
-      // For example 'gfx942'
+      // For example 'gfx942'.
       StringRef targetCPU = targetMachine->getTargetCPU();
 
-      // For example 'amdgcn-amd-amdhsa'
+      // For example 'amdgcn-amd-amdhsa'.
       std::string targetTriple = targetMachine->getTargetTriple().str();
 
       // Run LLVM optimization passes.
       std::string passesString;
       optimizeModule(*llvmModule, *targetMachine, options.slpVectorization,
                      passesString);
       if (!serializationOptions.dumpIntermediatesPath.empty()) {
-
         // Additional context on '-mcpu' flag in PR comments, see for example:
         // https://github.com/iree-org/iree/pull/20716#issuecomment-2851650421
-        std::string header =
-            llvm::formatv(R"TXT(
-; To reproduce the .optimized.ll from the .linked.ll, run:
-; opt -S -mtriple={} -mcpu={} --passes='{}'
-; The flag '-S' to emit LLVMIR.
-; The behavior of some passes depends on '-mtriple' and '-mcpu'
+        std::string header = llvm::formatv(
+            R"TXT(; To reproduce the .optimized.ll from the .linked.ll, run:
+; opt -S -mtriple={} -mcpu={} --passes='{}' <.linked.ll>
+; The flag '-S' is to emit LLVMIR.
+; The behavior of some passes depends on '-mtriple' and '-mcpu'.
 
 )TXT",
-                          targetTriple, targetCPU, passesString);
+            targetTriple, targetCPU, passesString);
 
         dumpModuleToPath(serializationOptions.dumpIntermediatesPath,
                          serializationOptions.dumpBaseName, variantOp.getName(),
@@ -751,11 +749,18 @@ class ROCMTargetBackend final : public TargetBackend {
           llvm::errs() << "Error: cloning LLVM IR failed\n";
           return failure();
         }
+        std::string asmHeader = llvm::formatv(
+            R"TXT(; To reproduce the .rocmasm from .optimized.ll, run:
+; llc -mtriple={} -mcpu={} -mattr='{}' -O3 <.optimized.ll> -o <out.rocmasm>
+
+)TXT",
+            targetTriple, targetCPU, targetMachine->getTargetFeatureString());
+
         std::string targetISA =
             translateModuleToISA(*moduleCopy.get(), *targetMachine);
         dumpDataToPath(serializationOptions.dumpIntermediatesPath,
                        serializationOptions.dumpBaseName, variantOp.getName(),
-                       ".rocmasm", targetISA);
+                       ".rocmasm", asmHeader + targetISA);
       }
 
       // Serialize hsaco kernel into the binary that we will embed in the