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cn0585: Rename cn0585_fmcz to cn0585
1 parent d69da64 commit 2d217da

33 files changed

+122
-46
lines changed

‎CI/scripts_hdl/matlab_processors.tcl‎

Lines changed: 16 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -3,13 +3,12 @@ proc preprocess_bd {project carrier rxtx} {
33
puts "Preprocessing $project $carrier $rxtx"
44

55
switch $project {
6-
cn0585_fmcz {
6+
cn0585 {
77
# Disconnect the ADC PACK pins
8-
delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
9-
delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
10-
delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data]
11-
delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data]
12-
8+
delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
9+
delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
10+
delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data]
11+
delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data]
1312

1413
set sys_cstring "matlab $rxtx"
1514
sysid_gen_sys_init_file $sys_cstring
@@ -20,21 +19,21 @@ proc preprocess_bd {project carrier rxtx} {
2019
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en]
2120

2221
if {$rxtx == "rx"} {
23-
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a]
22+
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a]
2423
connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b]
2524
connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a]
2625
connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b]
2726
}
2827

2928
if {$rxtx == "tx"} {
30-
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0]
29+
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0]
3130
connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1]
3231
connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2]
3332
connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3]
3433
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en]
3534
}
3635

37-
if {$rxtx == "tx" || $rxtx == "rxtx"} {
36+
if {$rxtx == "tx" || $rxtx == "rxtx"} {
3837

3938
delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid]
4039
delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid]
@@ -45,14 +44,14 @@ proc preprocess_bd {project carrier rxtx} {
4544
connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b]
4645
connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a]
4746
connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b]
48-
}
49-
switch $carrier {
50-
zed {
51-
set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
52-
connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0]
53-
connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
54-
}
55-
}
47+
}
48+
switch $carrier {
49+
zed {
50+
set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
51+
connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0]
52+
connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
53+
}
54+
}
5655
}
5756
}
5857
}

hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/hdlcoder_ref_design_customization.m renamed to hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/hdlcoder_ref_design_customization.m

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,9 @@
1212
% Copyright 2013-2014 The MathWorks, Inc.
1313

1414
rd = {...
15-
'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rx', ...
16-
'AnalogDevices.cn0585_fmcz.zed.plugin_rd_tx', ...
17-
'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rxtx', ...
15+
'AnalogDevices.cn0585.zed.plugin_rd_rx', ...
16+
'AnalogDevices.cn0585.zed.plugin_rd_tx', ...
17+
'AnalogDevices.cn0585.zed.plugin_rd_rxtx', ...
1818
};
1919

2020
boardName = 'AnalogDevices CN0585 ZED';

hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_board.m renamed to hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_board.m

File renamed without changes.

hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_rx.m renamed to hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_rx.m

File renamed without changes.

hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_rxtx.m renamed to hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_rxtx.m

File renamed without changes.

hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/plugin_rd_tx.m renamed to hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585/+zed/plugin_rd_tx.m

File renamed without changes.

‎hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
pname = upper(project);
77
ppath = project;
88
if strcmpi(project, 'cn0585')
9-
ppath = 'cn0585_fmcz';
9+
ppath = 'cn0585';
1010
end
1111

1212
% Construct reference design object

‎hdl/vendor/AnalogDevices/hdlcoder_board_customization.m‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
% Copyright 2012-2013 The MathWorks, Inc.
1010

1111
r = { ...
12-
'AnalogDevices.cn0585_fmcz.zed.plugin_board' ...,
12+
'AnalogDevices.cn0585.zed.plugin_board' ...,
1313
};
1414
end
1515
% LocalWords: Zynq ZC

‎hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
proc preprocess_bd {project carrier rxtx} {
2+
3+
puts "Preprocessing $project $carrier $rxtx"
4+
5+
switch $project {
6+
cn0585 {
7+
# Disconnect the ADC PACK pins
8+
delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
9+
delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
10+
delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data]
11+
delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data]
12+
13+
set sys_cstring "matlab $rxtx"
14+
sysid_gen_sys_init_file $sys_cstring
15+
16+
#Disconnect adc_valid
17+
delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid]
18+
# Reconnect the adc_valid in the system
19+
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en]
20+
21+
if {$rxtx == "rx"} {
22+
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a]
23+
connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b]
24+
connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a]
25+
connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b]
26+
}
27+
28+
if {$rxtx == "tx"} {
29+
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0]
30+
connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1]
31+
connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2]
32+
connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3]
33+
connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en]
34+
}
35+
36+
if {$rxtx == "tx" || $rxtx == "rxtx"} {
37+
38+
delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid]
39+
delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid]
40+
delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_valid]
41+
delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_valid]
42+
43+
# Connect dac valids together
44+
connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b]
45+
connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a]
46+
connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b]
47+
}
48+
switch $carrier {
49+
zed {
50+
set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
51+
connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0]
52+
connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
53+
}
54+
}
55+
}
56+
}
57+
}

pcx_examples/streaming/cn0585_fmcz/CN0585_streaming.m renamed to pcx_examples/streaming/cn0585/CN0585_streaming.m

File renamed without changes.

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