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| 1 | +--- |
| 2 | +# HWC (little data) configuration for Spectrum Sense (UNet) |
| 3 | +# UNet Model |
| 4 | + |
| 5 | +arch: ai85unetlarge |
| 6 | +dataset: SpectrumSense_s352_c2 |
| 7 | + |
| 8 | +layers: |
| 9 | + # Layer 0: prep0 |
| 10 | + - out_offset: 0x0600 |
| 11 | + in_offset: 0x0700 |
| 12 | + processors: 0x0000ffffffffffff |
| 13 | + output_processors: 0xffffffffffffffff |
| 14 | + operation: conv2d |
| 15 | + kernel_size: 1x1 |
| 16 | + pad: 0 |
| 17 | + activate: ReLU |
| 18 | + # Layer 1: prep1 |
| 19 | + - out_offset: 0x0400 |
| 20 | + processors: 0xffffffffffffffff |
| 21 | + output_processors: 0xffffffffffffffff |
| 22 | + operation: conv2d |
| 23 | + kernel_size: 1x1 |
| 24 | + pad: 0 |
| 25 | + activate: ReLU |
| 26 | + # Layer 2: prep2 |
| 27 | + - out_offset: 0x0200 |
| 28 | + processors: 0xffffffffffffffff |
| 29 | + output_processors: 0x00000000ffffffff |
| 30 | + operation: conv2d |
| 31 | + kernel_size: 1x1 |
| 32 | + pad: 0 |
| 33 | + activate: ReLU |
| 34 | + # Layer 3: enc1 |
| 35 | + - out_offset: 0x0000 |
| 36 | + processors: 0x00000000ffffffff |
| 37 | + output_processors: 0xff00000000000000 |
| 38 | + operation: conv2d |
| 39 | + kernel_size: 3x3 |
| 40 | + pad: 1 |
| 41 | + activate: ReLU |
| 42 | + # Layer 4: enc2 |
| 43 | + - out_offset: 0x0000 |
| 44 | + processors: 0xff00000000000000 |
| 45 | + output_processors: 0x00fffffff0000000 |
| 46 | + operation: conv2d |
| 47 | + kernel_size: 3x3 |
| 48 | + pad: 1 |
| 49 | + max_pool: 2 |
| 50 | + pool_stride: 2 |
| 51 | + activate: ReLU |
| 52 | + # Layer 5: enc3 |
| 53 | + - out_offset: 0x5000 |
| 54 | + processors: 0x00fffffff0000000 |
| 55 | + output_processors: 0x00ffffffffffffff |
| 56 | + operation: conv2d |
| 57 | + kernel_size: 3x3 |
| 58 | + pad: 1 |
| 59 | + max_pool: 2 |
| 60 | + pool_stride: 2 |
| 61 | + activate: ReLU |
| 62 | + # Layer 6: bneck |
| 63 | + - out_offset: 0x6000 |
| 64 | + processors: 0x00ffffffffffffff |
| 65 | + output_processors: 0x00ffffffffffffff |
| 66 | + operation: conv2d |
| 67 | + kernel_size: 3x3 |
| 68 | + pad: 1 |
| 69 | + max_pool: 2 |
| 70 | + pool_stride: 2 |
| 71 | + activate: ReLU |
| 72 | + # Layer 7: pt |
| 73 | + - in_offset: 0x5000 |
| 74 | + out_offset: 0x4004 |
| 75 | + processors: 0x00ffffffffffffff |
| 76 | + output_processors: 0x00ffffffffffffff |
| 77 | + operation: conv2d |
| 78 | + kernel_size: 1x1 |
| 79 | + pad: 0 |
| 80 | + write_gap: 1 |
| 81 | + in_sequences: [5] |
| 82 | + activate: None |
| 83 | + # Layer 8: upconv3 |
| 84 | + - in_offset: 0x6000 |
| 85 | + out_offset: 0x4000 |
| 86 | + processors: 0x00ffffffffffffff |
| 87 | + output_processors: 0x00ffffffffffffff |
| 88 | + operation: convtranspose2d |
| 89 | + kernel_size: 3x3 |
| 90 | + pad: 1 |
| 91 | + activate: None |
| 92 | + write_gap: 1 |
| 93 | + in_sequences: [6] |
| 94 | + # Layer 9: dec3 |
| 95 | + - out_offset: 0x2000 |
| 96 | + in_offset: 0x4000 |
| 97 | + processors: 0x00ffffffffffffff |
| 98 | + output_processors: 0x00ffffffffffffff |
| 99 | + operation: conv2d |
| 100 | + kernel_size: 3x3 |
| 101 | + pad: 1 |
| 102 | + activate: ReLU |
| 103 | + in_sequences: [8, 7] |
| 104 | + # Layer 10: upconv2 |
| 105 | + - out_offset: 0x0000 |
| 106 | + in_offset: 0x2000 |
| 107 | + processors: 0x00ffffffffffffff |
| 108 | + output_processors: 0x000000000fffffff |
| 109 | + operation: convtranspose2d |
| 110 | + kernel_size: 3x3 |
| 111 | + pad: 1 |
| 112 | + activate: None |
| 113 | + # Layer 11: dec2 |
| 114 | + - out_offset: 0x2000 |
| 115 | + in_offset: 0x0000 |
| 116 | + processors: 0x00ffffffffffffff |
| 117 | + output_processors: 0x000000000fffffff |
| 118 | + operation: conv2d |
| 119 | + kernel_size: 3x3 |
| 120 | + pad: 1 |
| 121 | + activate: ReLU |
| 122 | + in_sequences: [10, 4] |
| 123 | + # Layer 12: upconv1 |
| 124 | + - out_offset: 0x0000 |
| 125 | + processors: 0x000000000fffffff |
| 126 | + output_processors: 0x00ff000000000000 |
| 127 | + operation: convtranspose2d |
| 128 | + kernel_size: 3x3 |
| 129 | + pad: 1 |
| 130 | + activate: None |
| 131 | + # Layer 13: dec1 |
| 132 | + - out_offset: 0x0700 |
| 133 | + in_offset: 0x0000 |
| 134 | + processors: 0xffff000000000000 |
| 135 | + output_processors: 0x0000ffffffffffff |
| 136 | + operation: conv2d |
| 137 | + kernel_size: 3x3 |
| 138 | + pad: 1 |
| 139 | + activate: ReLU |
| 140 | + in_sequences: [12, 3] |
| 141 | + # Layer 14: dec0 |
| 142 | + - out_offset: 0x0550 |
| 143 | + processors: 0x0000ffffffffffff |
| 144 | + output_processors: 0xffffffffffffffff |
| 145 | + operation: conv2d |
| 146 | + kernel_size: 3x3 |
| 147 | + pad: 1 |
| 148 | + activate: ReLU |
| 149 | + # Layer 15: conv_p1 |
| 150 | + - out_offset: 0x0400 |
| 151 | + processors: 0xffffffffffffffff |
| 152 | + output_processors: 0xffffffffffffffff |
| 153 | + operation: conv2d |
| 154 | + kernel_size: 1x1 |
| 155 | + pad: 0 |
| 156 | + activate: ReLU |
| 157 | + # Layer 16: conv_p2 |
| 158 | + - out_offset: 0x0250 |
| 159 | + processors: 0xffffffffffffffff |
| 160 | + output_processors: 0xffffffffffffffff |
| 161 | + operation: conv2d |
| 162 | + kernel_size: 1x1 |
| 163 | + pad: 0 |
| 164 | + activate: ReLU |
| 165 | + # Layer 17: conv_p3 |
| 166 | + - out_offset: 0x0100 |
| 167 | + processors: 0xffffffffffffffff |
| 168 | + output_processors: 0xffffffffffffffff |
| 169 | + operation: conv2d |
| 170 | + kernel_size: 1x1 |
| 171 | + pad: 0 |
| 172 | + activate: None |
| 173 | + # Layer 18: conv |
| 174 | + - out_offset: 0x0000 |
| 175 | + processors: 0xffffffffffffffff |
| 176 | + output_processors: 0x0000ffffffffffff |
| 177 | + operation: conv2d |
| 178 | + kernel_size: 1x1 |
| 179 | + pad: 0 |
| 180 | + activate: None |
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